src/arch/sparc/isa/operands.isa - amd/gem5 - Git at Google


            
            // Copyright (c) 2006-2007 The Regents of The University of Michigan

            
            // All rights reserved.

            
            //

            
            // Redistribution and use in source and binary forms, with or without

            
            // modification, are permitted provided that the following conditions are

            
            // met: redistributions of source code must retain the above copyright

            
            // notice, this list of conditions and the following disclaimer;

            
            // redistributions in binary form must reproduce the above copyright

            
            // notice, this list of conditions and the following disclaimer in the

            
            // documentation and/or other materials provided with the distribution;

            
            // neither the name of the copyright holders nor the names of its

            
            // contributors may be used to endorse or promote products derived from

            
            // this software without specific prior written permission.

            
            //

            
            // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

            
            // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

            
            // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

            
            // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

            
            // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

            
            // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

            
            // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

            
            // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

            
            // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

            
            // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

            
            // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

            
            //

            
            // Authors: Ali Saidi

            
            //          Gabe Black

            
            //          Steve Reinhardt


            def operand_types {{

            
                'sb' : 'int8_t',

            
                'ub' : 'uint8_t',

            
                'shw' : 'int16_t',

            
                'uhw' : 'uint16_t',

            
                'sw' : 'int32_t',

            
                'uw' : 'uint32_t',

            
                'sdw' : 'int64_t',

            
                'udw' : 'uint64_t',

            
                'tudw' : 'std::array<uint64_t, 2>',

            
                'tuw' : 'std::array<uint32_t, 2>',

            
                'sf' : 'float',

            
                'df' : 'double',


                'pstate' : 'PSTATE',

            
                'hpstate' : 'HPSTATE'

            
            }};


            output header {{

            
                // A function to "decompress" double and quad floating point

            
                // register numbers stuffed into 5 bit fields. These have their

            
                // MSB put in the LSB position but are otherwise normal.

            
                static inline unsigned int

            
                dfpr(unsigned int regNum)

            
                {

            
                    return (regNum & (~1)) | ((regNum & 1) << 5);

            
                }


                static inline unsigned int

            
                dfprl(unsigned int regNum)

            
                {

            
                    return dfpr(regNum) & (~0x1);

            
                }


                static inline unsigned int

            
                dfprh(unsigned int regNum)

            
                {

            
                    return dfpr(regNum) | 0x1;

            
                }

            
            }};


            def operands {{

            
                # Int regs default to unsigned, but code should not count on this.

            
                # For clarity, descriptions that depend on unsigned behavior should

            
                # explicitly specify '.uq'.


                'Rd':               ('IntReg', 'udw', 'RD', 'IsInteger', 1),

            
                # The Rd from the previous window

            
                'Rd_prev':          ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),

            
                # The Rd from the next window

            
                'Rd_next':          ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),

            
                # For microcoded twin load instructions, RdTwin appears in the "code"

            
                # for the instruction is replaced by RdLow or RdHigh by the format

            
                # before it's processed by the iop.

            
                # The low (even) register of a two register pair

            
                'RdLow':            ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4),

            
                # The high (odd) register of a two register pair

            
                'RdHigh':           ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5),

            
                'Rs1':              ('IntReg', 'udw', 'RS1', 'IsInteger', 6),

            
                'Rs2':              ('IntReg', 'udw', 'RS2', 'IsInteger', 7),

            
                # A microcode register. Right now, this is the only one.

            
                'uReg0':            ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),

            
                # Because double and quad precision register numbers are decoded

            
                # differently, they get different operands. The single precision versions

            
                # have an s post pended to their name.

            
                'Frds':             ('FloatReg', 'sf', 'RD', 'IsFloating', 10),

            
                #'Frd':             ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),

            
                'Frd_low':          ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),

            
                'Frd_high':         ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),

            
                # Each Frd_N refers to the Nth double precision register from Frd.

            
                # Note that this adds twice N to the register number.

            
                #'Frd_0':           ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),

            
                'Frd_0_low':        ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),

            
                'Frd_0_high':       ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),

            
                #'Frd_1':           ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),

            
                'Frd_1_low':        ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10),

            
                'Frd_1_high':       ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10),

            
                #'Frd_2':           ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),

            
                'Frd_2_low':        ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10),

            
                'Frd_2_high':       ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10),

            
                #'Frd_3':           ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),

            
                'Frd_3_low':        ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10),

            
                'Frd_3_high':       ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10),

            
                #'Frd_4':           ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),

            
                'Frd_4_low':        ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10),

            
                'Frd_4_high':       ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10),

            
                #'Frd_5':           ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),

            
                'Frd_5_low':        ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10),

            
                'Frd_5_high':       ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10),

            
                #'Frd_6':           ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),

            
                'Frd_6_low':        ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10),

            
                'Frd_6_high':       ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10),

            
                #'Frd_7':           ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),

            
                'Frd_7_low':        ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10),

            
                'Frd_7_high':       ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10),

            
                'Frs1s':            ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),

            
                #'Frs1':            ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),

            
                'Frs1_low':         ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11),

            
                'Frs1_high':        ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11),

            
                'Frs2s':            ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),

            
                #'Frs2':            ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),

            
                'Frs2_low':         ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12),

            
                'Frs2_high':        ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12),

            
                'PC':               ('PCState', 'udw', 'pc', (None, None, 'IsControl'), 30),

            
                'NPC':              ('PCState', 'udw', 'npc', (None, None, 'IsControl'), 30),

            
                'NNPC':             ('PCState', 'udw', 'nnpc', (None, None, 'IsControl'), 30),

            
                # Registers which are used explicitly in instructions

            
                'R0':               ('IntReg', 'udw', '0', None, 6),

            
                'R1':               ('IntReg', 'udw', '1', None, 7),

            
                'R15':              ('IntReg', 'udw', '15', 'IsInteger', 8),

            
                'R16':              ('IntReg', 'udw', '16', None, 9),

            
                'O0':               ('IntReg', 'udw', '8', 'IsInteger', 10),

            
                'O1':               ('IntReg', 'udw', '9', 'IsInteger', 11),

            
                'O2':               ('IntReg', 'udw', '10', 'IsInteger', 12),

            
                'O3':               ('IntReg', 'udw', '11', 'IsInteger', 13),

            
                'O4':               ('IntReg', 'udw', '12', 'IsInteger', 14),

            
                'O5':               ('IntReg', 'udw', '13', 'IsInteger', 15),


                # Control registers

            
            #   'Y':                ('ControlReg', 'udw', 'MISCREG_Y', None, 40),

            
            #   'Ccr':              ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),

            
                'Y':                ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40),

            
                'Ccr':              ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41),

            
                'Asi':              ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),

            
                'Fprs':             ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),

            
                'Pcr':              ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),

            
                'Pic':              ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),

            
            #   'Gsr':              ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46),

            
                'Gsr':              ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46),

            
                'Softint':          ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),

            
                'SoftintSet':       ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),

            
                'SoftintClr':       ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),

            
                'TickCmpr':         ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),

            
                'Stick':            ('ControlReg', 'udw', 'MISCREG_STICK', None, 51),

            
                'StickCmpr':        ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),


                'Tpc':              ('ControlReg', 'udw', 'MISCREG_TPC', None, 53),

            
                'Tnpc':             ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),

            
                'Tstate':           ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),

            
                'Tt':               ('ControlReg', 'udw', 'MISCREG_TT', None, 56),

            
                'Tick':             ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),

            
                'Tba':              ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),

            
                'Pstate':           ('ControlReg', 'pstate', 'MISCREG_PSTATE', None, 59),

            
                'Tl':               ('ControlReg', 'udw', 'MISCREG_TL', None, 60),

            
                'Pil':              ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),

            
                'Cwp':              ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62),

            
            #   'Cansave':          ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),

            
            #   'Canrestore':       ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),

            
            #   'Cleanwin':         ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),

            
            #   'Otherwin':         ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),

            
            #   'Wstate':           ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),

            
                'Cansave':          ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63),

            
                'Canrestore':       ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64),

            
                'Cleanwin':         ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65),

            
                'Otherwin':         ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66),

            
                'Wstate':           ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67),

            
                'Gl':               ('ControlReg', 'udw', 'MISCREG_GL', None, 68),


                'Hpstate':          ('ControlReg', 'hpstate', 'MISCREG_HPSTATE', None, 69),

            
                'Htstate':          ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),

            
                'Hintp':            ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),

            
                'Htba':             ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),

            
                'HstickCmpr':       ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),

            
                'Hver':             ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),

            
                'StrandStsReg':     ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),


                'Fsr':              ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),

            
                # Mem gets a large number so it's always last

            
                'Mem':              ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)


            }};
	// Copyright (c) 2006-2007 The Regents of The University of Michigan
	// All rights reserved.
	//
	// Redistribution and use in source and binary forms, with or without
	// modification, are permitted provided that the following conditions are
	// met: redistributions of source code must retain the above copyright
	// notice, this list of conditions and the following disclaimer;
	// redistributions in binary form must reproduce the above copyright
	// notice, this list of conditions and the following disclaimer in the
	// documentation and/or other materials provided with the distribution;
	// neither the name of the copyright holders nor the names of its
	// contributors may be used to endorse or promote products derived from
	// this software without specific prior written permission.
	//
	// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	//
	// Authors: Ali Saidi
	// Gabe Black
	// Steve Reinhardt

	def operand_types {{
	'sb' : 'int8_t',
	'ub' : 'uint8_t',
	'shw' : 'int16_t',
	'uhw' : 'uint16_t',
	'sw' : 'int32_t',
	'uw' : 'uint32_t',
	'sdw' : 'int64_t',
	'udw' : 'uint64_t',
	'tudw' : 'std::array<uint64_t, 2>',
	'tuw' : 'std::array<uint32_t, 2>',
	'sf' : 'float',
	'df' : 'double',

	'pstate' : 'PSTATE',
	'hpstate' : 'HPSTATE'
	}};

	output header {{
	// A function to "decompress" double and quad floating point
	// register numbers stuffed into 5 bit fields. These have their
	// MSB put in the LSB position but are otherwise normal.
	static inline unsigned int
	dfpr(unsigned int regNum)
	{
	return (regNum & (~1)) \| ((regNum & 1) << 5);
	}

	static inline unsigned int
	dfprl(unsigned int regNum)
	{
	return dfpr(regNum) & (~0x1);
	}

	static inline unsigned int
	dfprh(unsigned int regNum)
	{
	return dfpr(regNum) \| 0x1;
	}
	}};

	def operands {{
	# Int regs default to unsigned, but code should not count on this.
	# For clarity, descriptions that depend on unsigned behavior should
	# explicitly specify '.uq'.

	'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
	# The Rd from the previous window
	'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),
	# The Rd from the next window
	'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),
	# For microcoded twin load instructions, RdTwin appears in the "code"
	# for the instruction is replaced by RdLow or RdHigh by the format
	# before it's processed by the iop.
	# The low (even) register of a two register pair
	'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4),
	# The high (odd) register of a two register pair
	'RdHigh': ('IntReg', 'udw', 'RD \| 1', 'IsInteger', 5),
	'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6),
	'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7),
	# A microcode register. Right now, this is the only one.
	'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),
	# Because double and quad precision register numbers are decoded
	# differently, they get different operands. The single precision versions
	# have an s post pended to their name.
	'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
	#'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
	'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
	'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
	# Each Frd_N refers to the Nth double precision register from Frd.
	# Note that this adds twice N to the register number.
	#'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
	'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
	'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
	#'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
	'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10),
	'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10),
	#'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
	'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10),
	'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10),
	#'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
	'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10),
	'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10),
	#'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
	'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10),
	'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10),
	#'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
	'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10),
	'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10),
	#'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
	'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10),
	'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10),
	#'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
	'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10),
	'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10),
	'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
	#'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
	'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11),
	'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11),
	'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
	#'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
	'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12),
	'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12),
	'PC': ('PCState', 'udw', 'pc', (None, None, 'IsControl'), 30),
	'NPC': ('PCState', 'udw', 'npc', (None, None, 'IsControl'), 30),
	'NNPC': ('PCState', 'udw', 'nnpc', (None, None, 'IsControl'), 30),
	# Registers which are used explicitly in instructions
	'R0': ('IntReg', 'udw', '0', None, 6),
	'R1': ('IntReg', 'udw', '1', None, 7),
	'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
	'R16': ('IntReg', 'udw', '16', None, 9),
	'O0': ('IntReg', 'udw', '8', 'IsInteger', 10),
	'O1': ('IntReg', 'udw', '9', 'IsInteger', 11),
	'O2': ('IntReg', 'udw', '10', 'IsInteger', 12),
	'O3': ('IntReg', 'udw', '11', 'IsInteger', 13),
	'O4': ('IntReg', 'udw', '12', 'IsInteger', 14),
	'O5': ('IntReg', 'udw', '13', 'IsInteger', 15),

	# Control registers
	# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
	# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
	'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40),
	'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41),
	'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
	'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
	'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
	'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
	# 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46),
	'Gsr': ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46),
	'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
	'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
	'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
	'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
	'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
	'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),

	'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53),
	'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
	'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
	'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
	'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
	'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
	'Pstate': ('ControlReg', 'pstate', 'MISCREG_PSTATE', None, 59),
	'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
	'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
	'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62),
	# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
	# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
	# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
	# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
	# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
	'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63),
	'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64),
	'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65),
	'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66),
	'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67),
	'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),

	'Hpstate': ('ControlReg', 'hpstate', 'MISCREG_HPSTATE', None, 69),
	'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
	'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
	'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
	'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
	'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
	'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),

	'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
	# Mem gets a large number so it's always last
	'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)

	}};