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# Copyright (c) 2012-2013 ARM Limited
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# Authors: Ali Saidi
# Andreas Hansson
from m5.params import *
from MemObject import MemObject
class Bridge(MemObject):
type = 'Bridge'
cxx_header = "mem/bridge.hh"
slave = SlavePort('Slave port')
master = MasterPort('Master port')
req_size = Param.Unsigned(16, "The number of requests to buffer")
resp_size = Param.Unsigned(16, "The number of responses to buffer")
delay = Param.Latency('0ns', "The latency of this bridge")
ranges = VectorParam.AddrRange([AllMemory],
"Address ranges to pass through the bridge")