ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011-2013 ARM Limited |
| 3 | * All rights reserved |
| 4 | * |
| 5 | * The license below extends only to copyright in the software and shall |
| 6 | * not be construed as granting a license to any other intellectual |
| 7 | * property including but not limited to intellectual property relating |
| 8 | * to a hardware implementation of the functionality of the software |
| 9 | * licensed hereunder. You may use the software subject to the license |
| 10 | * terms below provided that you ensure that this notice is replicated |
| 11 | * unmodified and in its entirety in all distributions of the software, |
| 12 | * modified or unmodified, in source code or in binary form. |
| 13 | * |
| 14 | * Redistribution and use in source and binary forms, with or without |
| 15 | * modification, are permitted provided that the following conditions are |
| 16 | * met: redistributions of source code must retain the above copyright |
| 17 | * notice, this list of conditions and the following disclaimer; |
| 18 | * redistributions in binary form must reproduce the above copyright |
| 19 | * notice, this list of conditions and the following disclaimer in the |
| 20 | * documentation and/or other materials provided with the distribution; |
| 21 | * neither the name of the copyright holders nor the names of its |
| 22 | * contributors may be used to endorse or promote products derived from |
| 23 | * this software without specific prior written permission. |
| 24 | * |
| 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 26 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 27 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 28 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 29 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 30 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 31 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 32 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 33 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 34 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 35 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 36 | * |
| 37 | * Authors: Gabe Black |
| 38 | */ |
| 39 | #ifndef __ARCH_ARM_INSTS_DATA64_HH__ |
| 40 | #define __ARCH_ARM_INSTS_DATA64_HH__ |
| 41 | |
| 42 | #include "arch/arm/insts/static_inst.hh" |
| 43 | #include "base/trace.hh" |
| 44 | |
| 45 | namespace ArmISA |
| 46 | { |
| 47 | |
| 48 | class DataXImmOp : public ArmStaticInst |
| 49 | { |
| 50 | protected: |
| 51 | IntRegIndex dest, op1; |
| 52 | uint64_t imm; |
| 53 | |
| 54 | DataXImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, |
| 55 | IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) : |
| 56 | ArmStaticInst(mnem, _machInst, __opClass), |
| 57 | dest(_dest), op1(_op1), imm(_imm) |
| 58 | {} |
| 59 | |
Gabe Black | cdf3cc2 | 2018-03-23 17:39:32 -0700 | [diff] [blame] | 60 | std::string generateDisassembly( |
| 61 | Addr pc, const SymbolTable *symtab) const override; |
ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 62 | }; |
| 63 | |
| 64 | class DataXImmOnlyOp : public ArmStaticInst |
| 65 | { |
| 66 | protected: |
| 67 | IntRegIndex dest; |
| 68 | uint64_t imm; |
| 69 | |
| 70 | DataXImmOnlyOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, |
| 71 | IntRegIndex _dest, uint64_t _imm) : |
| 72 | ArmStaticInst(mnem, _machInst, __opClass), |
| 73 | dest(_dest), imm(_imm) |
| 74 | {} |
| 75 | |
Gabe Black | cdf3cc2 | 2018-03-23 17:39:32 -0700 | [diff] [blame] | 76 | std::string generateDisassembly( |
| 77 | Addr pc, const SymbolTable *symtab) const override; |
ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 78 | }; |
| 79 | |
| 80 | class DataXSRegOp : public ArmStaticInst |
| 81 | { |
| 82 | protected: |
| 83 | IntRegIndex dest, op1, op2; |
| 84 | int32_t shiftAmt; |
| 85 | ArmShiftType shiftType; |
| 86 | |
| 87 | DataXSRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, |
| 88 | IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, |
| 89 | int32_t _shiftAmt, ArmShiftType _shiftType) : |
| 90 | ArmStaticInst(mnem, _machInst, __opClass), |
| 91 | dest(_dest), op1(_op1), op2(_op2), |
| 92 | shiftAmt(_shiftAmt), shiftType(_shiftType) |
| 93 | {} |
| 94 | |
Gabe Black | cdf3cc2 | 2018-03-23 17:39:32 -0700 | [diff] [blame] | 95 | std::string generateDisassembly( |
| 96 | Addr pc, const SymbolTable *symtab) const override; |
ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 97 | }; |
| 98 | |
| 99 | class DataXERegOp : public ArmStaticInst |
| 100 | { |
| 101 | protected: |
| 102 | IntRegIndex dest, op1, op2; |
| 103 | ArmExtendType extendType; |
| 104 | int32_t shiftAmt; |
| 105 | |
| 106 | DataXERegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, |
| 107 | IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, |
| 108 | ArmExtendType _extendType, int32_t _shiftAmt) : |
| 109 | ArmStaticInst(mnem, _machInst, __opClass), |
| 110 | dest(_dest), op1(_op1), op2(_op2), |
| 111 | extendType(_extendType), shiftAmt(_shiftAmt) |
| 112 | {} |
| 113 | |
Gabe Black | cdf3cc2 | 2018-03-23 17:39:32 -0700 | [diff] [blame] | 114 | std::string generateDisassembly( |
| 115 | Addr pc, const SymbolTable *symtab) const override; |
ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 116 | }; |
| 117 | |
| 118 | class DataX1RegOp : public ArmStaticInst |
| 119 | { |
| 120 | protected: |
| 121 | IntRegIndex dest, op1; |
| 122 | |
| 123 | DataX1RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, |
| 124 | IntRegIndex _dest, IntRegIndex _op1) : |
| 125 | ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1) |
| 126 | {} |
| 127 | |
Gabe Black | cdf3cc2 | 2018-03-23 17:39:32 -0700 | [diff] [blame] | 128 | std::string generateDisassembly( |
| 129 | Addr pc, const SymbolTable *symtab) const override; |
ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 130 | }; |
| 131 | |
| 132 | class DataX1RegImmOp : public ArmStaticInst |
| 133 | { |
| 134 | protected: |
| 135 | IntRegIndex dest, op1; |
| 136 | uint64_t imm; |
| 137 | |
| 138 | DataX1RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, |
| 139 | IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) : |
| 140 | ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1), |
| 141 | imm(_imm) |
| 142 | {} |
| 143 | |
Gabe Black | cdf3cc2 | 2018-03-23 17:39:32 -0700 | [diff] [blame] | 144 | std::string generateDisassembly( |
| 145 | Addr pc, const SymbolTable *symtab) const override; |
ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 146 | }; |
| 147 | |
| 148 | class DataX1Reg2ImmOp : public ArmStaticInst |
| 149 | { |
| 150 | protected: |
| 151 | IntRegIndex dest, op1; |
| 152 | uint64_t imm1, imm2; |
| 153 | |
| 154 | DataX1Reg2ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, |
| 155 | IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1, |
| 156 | uint64_t _imm2) : |
| 157 | ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1), |
| 158 | imm1(_imm1), imm2(_imm2) |
| 159 | {} |
| 160 | |
Gabe Black | cdf3cc2 | 2018-03-23 17:39:32 -0700 | [diff] [blame] | 161 | std::string generateDisassembly( |
| 162 | Addr pc, const SymbolTable *symtab) const override; |
ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 163 | }; |
| 164 | |
| 165 | class DataX2RegOp : public ArmStaticInst |
| 166 | { |
| 167 | protected: |
| 168 | IntRegIndex dest, op1, op2; |
| 169 | |
| 170 | DataX2RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, |
| 171 | IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) : |
| 172 | ArmStaticInst(mnem, _machInst, __opClass), |
| 173 | dest(_dest), op1(_op1), op2(_op2) |
| 174 | {} |
| 175 | |
Gabe Black | cdf3cc2 | 2018-03-23 17:39:32 -0700 | [diff] [blame] | 176 | std::string generateDisassembly( |
| 177 | Addr pc, const SymbolTable *symtab) const override; |
ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 178 | }; |
| 179 | |
| 180 | class DataX2RegImmOp : public ArmStaticInst |
| 181 | { |
| 182 | protected: |
| 183 | IntRegIndex dest, op1, op2; |
| 184 | uint64_t imm; |
| 185 | |
| 186 | DataX2RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, |
| 187 | IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, |
| 188 | uint64_t _imm) : |
| 189 | ArmStaticInst(mnem, _machInst, __opClass), |
| 190 | dest(_dest), op1(_op1), op2(_op2), imm(_imm) |
| 191 | {} |
| 192 | |
Gabe Black | cdf3cc2 | 2018-03-23 17:39:32 -0700 | [diff] [blame] | 193 | std::string generateDisassembly( |
| 194 | Addr pc, const SymbolTable *symtab) const override; |
ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 195 | }; |
| 196 | |
| 197 | class DataX3RegOp : public ArmStaticInst |
| 198 | { |
| 199 | protected: |
| 200 | IntRegIndex dest, op1, op2, op3; |
| 201 | |
| 202 | DataX3RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, |
| 203 | IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, |
| 204 | IntRegIndex _op3) : |
| 205 | ArmStaticInst(mnem, _machInst, __opClass), |
| 206 | dest(_dest), op1(_op1), op2(_op2), op3(_op3) |
| 207 | {} |
| 208 | |
Gabe Black | cdf3cc2 | 2018-03-23 17:39:32 -0700 | [diff] [blame] | 209 | std::string generateDisassembly( |
| 210 | Addr pc, const SymbolTable *symtab) const override; |
ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 211 | }; |
| 212 | |
| 213 | class DataXCondCompImmOp : public ArmStaticInst |
| 214 | { |
| 215 | protected: |
| 216 | IntRegIndex op1; |
| 217 | uint64_t imm; |
| 218 | ConditionCode condCode; |
| 219 | uint8_t defCc; |
| 220 | |
| 221 | DataXCondCompImmOp(const char *mnem, ExtMachInst _machInst, |
| 222 | OpClass __opClass, IntRegIndex _op1, uint64_t _imm, |
| 223 | ConditionCode _condCode, uint8_t _defCc) : |
| 224 | ArmStaticInst(mnem, _machInst, __opClass), |
| 225 | op1(_op1), imm(_imm), condCode(_condCode), defCc(_defCc) |
| 226 | {} |
| 227 | |
Gabe Black | cdf3cc2 | 2018-03-23 17:39:32 -0700 | [diff] [blame] | 228 | std::string generateDisassembly( |
| 229 | Addr pc, const SymbolTable *symtab) const override; |
ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 230 | }; |
| 231 | |
| 232 | class DataXCondCompRegOp : public ArmStaticInst |
| 233 | { |
| 234 | protected: |
| 235 | IntRegIndex op1, op2; |
| 236 | ConditionCode condCode; |
| 237 | uint8_t defCc; |
| 238 | |
| 239 | DataXCondCompRegOp(const char *mnem, ExtMachInst _machInst, |
| 240 | OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2, |
| 241 | ConditionCode _condCode, uint8_t _defCc) : |
| 242 | ArmStaticInst(mnem, _machInst, __opClass), |
| 243 | op1(_op1), op2(_op2), condCode(_condCode), defCc(_defCc) |
| 244 | {} |
| 245 | |
Gabe Black | cdf3cc2 | 2018-03-23 17:39:32 -0700 | [diff] [blame] | 246 | std::string generateDisassembly( |
| 247 | Addr pc, const SymbolTable *symtab) const override; |
ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 248 | }; |
| 249 | |
| 250 | class DataXCondSelOp : public ArmStaticInst |
| 251 | { |
| 252 | protected: |
| 253 | IntRegIndex dest, op1, op2; |
| 254 | ConditionCode condCode; |
| 255 | |
| 256 | DataXCondSelOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, |
| 257 | IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, |
| 258 | ConditionCode _condCode) : |
| 259 | ArmStaticInst(mnem, _machInst, __opClass), |
| 260 | dest(_dest), op1(_op1), op2(_op2), condCode(_condCode) |
| 261 | {} |
| 262 | |
Gabe Black | cdf3cc2 | 2018-03-23 17:39:32 -0700 | [diff] [blame] | 263 | std::string generateDisassembly( |
| 264 | Addr pc, const SymbolTable *symtab) const override; |
ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 265 | }; |
| 266 | |
| 267 | } |
| 268 | |
| 269 | #endif //__ARCH_ARM_INSTS_PREDINST_HH__ |