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Nathan Binkert7e4229f2004-11-13 17:10:48 -05001/*
Steve Reinhardtad8b9632005-06-05 05:16:00 -04002 * Copyright (c) 2004-2005 The Regents of The University of Michigan
Nathan Binkert7e4229f2004-11-13 17:10:48 -05003 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Ali Saidicb0cf2d2006-05-31 19:26:56 -040027 *
28 * Authors: Nathan Binkert
Nathan Binkert7e4229f2004-11-13 17:10:48 -050029 */
30
Andreas Sandberg23c961a2015-12-10 10:35:18 +000031#ifndef __DEV_NET_SINIC_HH__
32#define __DEV_NET_SINIC_HH__
Nathan Binkert7e4229f2004-11-13 17:10:48 -050033
34#include "base/inet.hh"
35#include "base/statistics.hh"
Nathan Binkert7e4229f2004-11-13 17:10:48 -050036#include "dev/io_device.hh"
Andreas Sandberg23c961a2015-12-10 10:35:18 +000037#include "dev/net/etherdevice.hh"
38#include "dev/net/etherint.hh"
39#include "dev/net/etherpkt.hh"
40#include "dev/net/pktfifo.hh"
41#include "dev/net/sinicreg.hh"
Andreas Sandberg139c97c2015-12-10 10:35:15 +000042#include "dev/pci/device.hh"
Nathan Binkertabc76f22007-07-23 21:51:38 -070043#include "params/Sinic.hh"
Nathan Binkert7e4229f2004-11-13 17:10:48 -050044#include "sim/eventq.hh"
45
46namespace Sinic {
47
48class Interface;
Andreas Sandbergdf020472012-11-02 11:32:01 -050049class Base : public EtherDevBase
Nathan Binkert7e4229f2004-11-13 17:10:48 -050050{
51 protected:
52 bool rxEnable;
53 bool txEnable;
54
55 protected:
56 Tick intrDelay;
57 Tick intrTick;
58 bool cpuIntrEnable;
59 bool cpuPendingIntr;
60 void cpuIntrPost(Tick when);
61 void cpuInterrupt();
62 void cpuIntrClear();
63
Sean Wilsonc8668a62017-06-07 16:32:15 -050064 EventFunctionWrapper *intrEvent;
Nathan Binkert7e4229f2004-11-13 17:10:48 -050065 Interface *interface;
66
67 bool cpuIntrPending() const;
68 void cpuIntrAck() { cpuIntrClear(); }
69
70/**
71 * Serialization stuff
72 */
73 public:
Andreas Hansson22c04192015-10-12 04:07:59 -040074 void serialize(CheckpointOut &cp) const override;
75 void unserialize(CheckpointIn &cp) override;
Nathan Binkert7e4229f2004-11-13 17:10:48 -050076
77/**
78 * Construction/Destruction/Parameters
79 */
80 public:
Nathan Binkertabc76f22007-07-23 21:51:38 -070081 typedef SinicParams Params;
82 const Params *params() const { return (const Params *)_params; }
Ali Saidi773cb772007-08-16 16:49:02 -040083 Base(const Params *p);
Nathan Binkert7e4229f2004-11-13 17:10:48 -050084};
85
86class Device : public Base
87{
88 protected:
Nathan Binkert7e4229f2004-11-13 17:10:48 -050089 /** Receive State Machine States */
90 enum RxState {
91 rxIdle,
92 rxFifoBlock,
93 rxBeginCopy,
94 rxCopy,
95 rxCopyDone
96 };
97
98 /** Transmit State Machine states */
99 enum TxState {
100 txIdle,
101 txFifoBlock,
102 txBeginCopy,
103 txCopy,
104 txCopyDone
105 };
106
107 /** device register file */
108 struct {
Nathan Binkertb7b8ffa2005-10-21 20:28:21 -0400109 uint32_t Config; // 0x00
110 uint32_t Command; // 0x04
111 uint32_t IntrStatus; // 0x08
112 uint32_t IntrMask; // 0x0c
113 uint32_t RxMaxCopy; // 0x10
114 uint32_t TxMaxCopy; // 0x14
Nathan Binkert886c5f82008-10-09 04:58:23 -0700115 uint32_t ZeroCopySize; // 0x18
116 uint32_t ZeroCopyMark; // 0x1c
117 uint32_t VirtualCount; // 0x20
118 uint32_t RxMaxIntr; // 0x24
119 uint32_t RxFifoSize; // 0x28
120 uint32_t TxFifoSize; // 0x2c
121 uint32_t RxFifoLow; // 0x30
122 uint32_t TxFifoLow; // 0x34
123 uint32_t RxFifoHigh; // 0x38
124 uint32_t TxFifoHigh; // 0x3c
125 uint64_t RxData; // 0x40
126 uint64_t RxDone; // 0x48
127 uint64_t RxWait; // 0x50
128 uint64_t TxData; // 0x58
129 uint64_t TxDone; // 0x60
130 uint64_t TxWait; // 0x68
131 uint64_t HwAddr; // 0x70
132 uint64_t RxStatus; // 0x78
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500133 } regs;
134
Nathan Binkert47ff0af2005-11-25 13:33:36 -0500135 struct VirtualReg {
136 uint64_t RxData;
137 uint64_t RxDone;
138 uint64_t TxData;
139 uint64_t TxDone;
140
Nathan Binkert886c5f82008-10-09 04:58:23 -0700141 PacketFifo::iterator rxIndex;
Nathan Binkert6faf3772009-06-04 23:21:12 -0700142 unsigned rxPacketOffset;
143 unsigned rxPacketBytes;
Nathan Binkert47ff0af2005-11-25 13:33:36 -0500144 uint64_t rxDoneData;
145
Nathan Binkert8e9d4442006-04-26 17:52:33 -0400146 Counter rxUnique;
147 Counter txUnique;
148
Nathan Binkert47ff0af2005-11-25 13:33:36 -0500149 VirtualReg()
150 : RxData(0), RxDone(0), TxData(0), TxDone(0),
151 rxPacketOffset(0), rxPacketBytes(0), rxDoneData(0)
152 { }
153 };
154 typedef std::vector<VirtualReg> VirtualRegs;
Nathan Binkert6faf3772009-06-04 23:21:12 -0700155 typedef std::list<unsigned> VirtualList;
Nathan Binkert8e9d4442006-04-26 17:52:33 -0400156 Counter rxUnique;
157 Counter txUnique;
Nathan Binkert47ff0af2005-11-25 13:33:36 -0500158 VirtualRegs virtualRegs;
159 VirtualList rxList;
Nathan Binkert8e9d4442006-04-26 17:52:33 -0400160 VirtualList rxBusy;
161 int rxActive;
Nathan Binkert47ff0af2005-11-25 13:33:36 -0500162 VirtualList txList;
163
Nathan Binkert886c5f82008-10-09 04:58:23 -0700164 int rxBusyCount;
165 int rxMappedCount;
166 int rxDirtyCount;
167
Nathan Binkertb7b8ffa2005-10-21 20:28:21 -0400168 uint8_t &regData8(Addr daddr) { return *((uint8_t *)&regs + daddr); }
169 uint32_t &regData32(Addr daddr) { return *(uint32_t *)&regData8(daddr); }
170 uint64_t &regData64(Addr daddr) { return *(uint64_t *)&regData8(daddr); }
171
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500172 protected:
173 RxState rxState;
174 PacketFifo rxFifo;
Nathan Binkert47ff0af2005-11-25 13:33:36 -0500175 PacketFifo::iterator rxFifoPtr;
Nathan Binkertb7b8ffa2005-10-21 20:28:21 -0400176 bool rxEmpty;
Nathan Binkert8e9d4442006-04-26 17:52:33 -0400177 bool rxLow;
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500178 Addr rxDmaAddr;
179 uint8_t *rxDmaData;
Nathan Binkert6faf3772009-06-04 23:21:12 -0700180 unsigned rxDmaLen;
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500181
182 TxState txState;
183 PacketFifo txFifo;
Nathan Binkertb7b8ffa2005-10-21 20:28:21 -0400184 bool txFull;
Ali Saidi8f8d0952006-04-24 19:31:50 -0400185 EthPacketPtr txPacket;
Nathan Binkert47ff0af2005-11-25 13:33:36 -0500186 int txPacketOffset;
187 int txPacketBytes;
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500188 Addr txDmaAddr;
189 uint8_t *txDmaData;
190 int txDmaLen;
191
192 protected:
193 void reset();
194
195 void rxKick();
196 Tick rxKickTick;
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500197
198 void txKick();
199 Tick txKickTick;
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500200
201 /**
202 * Retransmit event
203 */
204 void transmit();
205 void txEventTransmit()
206 {
207 transmit();
208 if (txState == txFifoBlock)
209 txKick();
210 }
Sean Wilsonc8668a62017-06-07 16:32:15 -0500211 EventFunctionWrapper txEvent;
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500212
213 void txDump() const;
214 void rxDump() const;
215
216 /**
217 * receive address filter
218 */
Ali Saidi8f8d0952006-04-24 19:31:50 -0400219 bool rxFilter(const EthPacketPtr &packet);
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500220
221/**
222 * device configuration
223 */
224 void changeConfig(uint32_t newconfig);
Nathan Binkertb7b8ffa2005-10-21 20:28:21 -0400225 void command(uint32_t command);
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500226
227/**
228 * device ethernet interface
229 */
230 public:
Ali Saidi8f8d0952006-04-24 19:31:50 -0400231 bool recvPacket(EthPacketPtr packet);
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500232 void transferDone();
Andreas Hansson2ac04c12015-10-12 04:08:01 -0400233 EtherInt *getEthPort(const std::string &if_name, int idx) override;
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500234
235/**
236 * DMA parameters
237 */
238 protected:
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500239 void rxDmaDone();
Sean Wilsonc8668a62017-06-07 16:32:15 -0500240 EventFunctionWrapper rxDmaEvent;
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500241
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500242 void txDmaDone();
Sean Wilsonc8668a62017-06-07 16:32:15 -0500243 EventFunctionWrapper txDmaEvent;
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500244
245 Tick dmaReadDelay;
246 Tick dmaReadFactor;
247 Tick dmaWriteDelay;
248 Tick dmaWriteFactor;
249
250/**
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500251 * Interrupt management
252 */
253 protected:
254 void devIntrPost(uint32_t interrupts);
255 void devIntrClear(uint32_t interrupts = Regs::Intr_All);
256 void devIntrChangeMask(uint32_t newmask);
257
258/**
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500259 * Memory Interface
260 */
261 public:
Andreas Hansson2ac04c12015-10-12 04:08:01 -0400262 Tick read(PacketPtr pkt) override;
263 Tick write(PacketPtr pkt) override;
Andreas Hansson22c04192015-10-12 04:07:59 -0400264 virtual void drainResume() override;
Nathan Binkert2b76b412005-11-21 21:52:04 -0500265
Andreas Sandberg53e777d2015-08-07 09:59:13 +0100266 void prepareIO(ContextID cpu, int index);
267 void prepareRead(ContextID cpu, int index);
268 void prepareWrite(ContextID cpu, int index);
269 // Fault iprRead(Addr daddr, ContextID cpu, uint64_t &result);
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500270
271/**
272 * Statistics
273 */
274 private:
Nathan Binkertcc95b572009-03-05 19:09:53 -0800275 Stats::Scalar totalVnicDistance;
276 Stats::Scalar numVnicDistance;
277 Stats::Scalar maxVnicDistance;
Nathan Binkert886c5f82008-10-09 04:58:23 -0700278 Stats::Formula avgVnicDistance;
279
280 int _maxVnicDistance;
281
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500282 public:
Andreas Hansson2ac04c12015-10-12 04:08:01 -0400283 void regStats() override;
284 void resetStats() override;
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500285
286/**
287 * Serialization stuff
288 */
289 public:
Andreas Hansson22c04192015-10-12 04:07:59 -0400290 void serialize(CheckpointOut &cp) const override;
291 void unserialize(CheckpointIn &cp) override;
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500292
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500293 public:
Ali Saidi773cb772007-08-16 16:49:02 -0400294 Device(const Params *p);
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500295 ~Device();
296};
297
298/*
299 * Ethernet Interface for an Ethernet Device
300 */
301class Interface : public EtherInt
302{
303 private:
304 Device *dev;
305
306 public:
307 Interface(const std::string &name, Device *d)
Ali Saidi773cb772007-08-16 16:49:02 -0400308 : EtherInt(name), dev(d)
309 { }
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500310
Ali Saidi8f8d0952006-04-24 19:31:50 -0400311 virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500312 virtual void sendDone() { dev->transferDone(); }
313};
314
Steve Reinhardtc69d48f2011-01-03 14:35:43 -0800315} // namespace Sinic
Nathan Binkert7e4229f2004-11-13 17:10:48 -0500316
Andreas Sandberg23c961a2015-12-10 10:35:18 +0000317#endif // __DEV_NET_SINIC_HH__