Stephen Hines | 7a7c4c5 | 2009-04-05 18:53:15 -0700 | [diff] [blame] | 1 | /* |
ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 2 | * Copyright (c) 2010, 2012 ARM Limited |
Gabe Black | 3430b34 | 2010-06-02 12:58:03 -0500 | [diff] [blame] | 3 | * All rights reserved |
| 4 | * |
| 5 | * The license below extends only to copyright in the software and shall |
| 6 | * not be construed as granting a license to any other intellectual |
| 7 | * property including but not limited to intellectual property relating |
| 8 | * to a hardware implementation of the functionality of the software |
| 9 | * licensed hereunder. You may use the software subject to the license |
| 10 | * terms below provided that you ensure that this notice is replicated |
| 11 | * unmodified and in its entirety in all distributions of the software, |
| 12 | * modified or unmodified, in source code or in binary form. |
| 13 | * |
Stephen Hines | 7a7c4c5 | 2009-04-05 18:53:15 -0700 | [diff] [blame] | 14 | * Copyright (c) 2003-2005 The Regents of The University of Michigan |
| 15 | * Copyright (c) 2007-2008 The Florida State University |
| 16 | * All rights reserved. |
| 17 | * |
| 18 | * Redistribution and use in source and binary forms, with or without |
| 19 | * modification, are permitted provided that the following conditions are |
| 20 | * met: redistributions of source code must retain the above copyright |
| 21 | * notice, this list of conditions and the following disclaimer; |
| 22 | * redistributions in binary form must reproduce the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer in the |
| 24 | * documentation and/or other materials provided with the distribution; |
| 25 | * neither the name of the copyright holders nor the names of its |
| 26 | * contributors may be used to endorse or promote products derived from |
| 27 | * this software without specific prior written permission. |
| 28 | * |
| 29 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 30 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 31 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 32 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 33 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 34 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 35 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 36 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 37 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 38 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 39 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 40 | * |
| 41 | * Authors: Gabe Black |
| 42 | * Stephen Hines |
| 43 | */ |
| 44 | |
| 45 | #ifndef __ARCH_ARM_ISA_TRAITS_HH__ |
| 46 | #define __ARCH_ARM_ISA_TRAITS_HH__ |
| 47 | |
| 48 | #include "arch/arm/types.hh" |
Nathan Binkert | eef3a2e | 2009-05-17 14:34:50 -0700 | [diff] [blame] | 49 | #include "base/types.hh" |
Gabe Black | 49a7ed0 | 2011-09-09 02:40:11 -0700 | [diff] [blame] | 50 | #include "cpu/static_inst_fwd.hh" |
Stephen Hines | 7a7c4c5 | 2009-04-05 18:53:15 -0700 | [diff] [blame] | 51 | |
Steve Reinhardt | c69d48f | 2011-01-03 14:35:43 -0800 | [diff] [blame] | 52 | namespace LittleEndianGuest {} |
Stephen Hines | 7a7c4c5 | 2009-04-05 18:53:15 -0700 | [diff] [blame] | 53 | |
Stephen Hines | 7a7c4c5 | 2009-04-05 18:53:15 -0700 | [diff] [blame] | 54 | namespace ArmISA |
| 55 | { |
| 56 | using namespace LittleEndianGuest; |
| 57 | |
| 58 | StaticInstPtr decodeInst(ExtMachInst); |
| 59 | |
Stephen Hines | 7a7c4c5 | 2009-04-05 18:53:15 -0700 | [diff] [blame] | 60 | const Addr PageShift = 12; |
| 61 | const Addr PageBytes = ULL(1) << PageShift; |
| 62 | const Addr Page_Mask = ~(PageBytes - 1); |
| 63 | const Addr PageOffset = PageBytes - 1; |
| 64 | |
| 65 | |
| 66 | //////////////////////////////////////////////////////////////////////// |
| 67 | // |
| 68 | // Translation stuff |
| 69 | // |
| 70 | |
| 71 | const Addr PteShift = 3; |
| 72 | const Addr NPtePageShift = PageShift - PteShift; |
| 73 | const Addr NPtePage = ULL(1) << NPtePageShift; |
| 74 | const Addr PteMask = NPtePage - 1; |
| 75 | |
| 76 | //// All 'Mapped' segments go through the TLB |
| 77 | //// All other segments are translated by dropping the MSB, to give |
| 78 | //// the corresponding physical address |
| 79 | // User Segment - Mapped |
| 80 | const Addr USegBase = ULL(0x0); |
| 81 | const Addr USegEnd = ULL(0x7FFFFFFF); |
| 82 | |
Stephen Hines | 7a7c4c5 | 2009-04-05 18:53:15 -0700 | [diff] [blame] | 83 | const unsigned VABits = 32; |
| 84 | const unsigned PABits = 32; // Is this correct? |
| 85 | const Addr VAddrImplMask = (ULL(1) << VABits) - 1; |
| 86 | const Addr VAddrUnImplMask = ~VAddrImplMask; |
| 87 | inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } |
| 88 | inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; } |
| 89 | inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; } |
| 90 | |
| 91 | const Addr PAddrImplMask = (ULL(1) << PABits) - 1; |
| 92 | |
ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 93 | // Max. physical address range in bits supported by the architecture |
| 94 | const unsigned MaxPhysAddrRange = 48; |
| 95 | |
Stephen Hines | 7a7c4c5 | 2009-04-05 18:53:15 -0700 | [diff] [blame] | 96 | const int MachineBytes = 4; |
Gabe Black | 2e28da5 | 2009-11-10 20:34:38 -0800 | [diff] [blame] | 97 | |
| 98 | const uint32_t HighVecs = 0xFFFF0000; |
Timothy M. Jones | 29e8bce | 2010-02-12 19:53:20 +0000 | [diff] [blame] | 99 | |
| 100 | // Memory accesses cannot be unaligned |
Min Kyu Jeong | dee8f3d | 2010-08-25 19:10:43 -0500 | [diff] [blame] | 101 | const bool HasUnalignedMemAcc = true; |
Ali Saidi | 5e6d289 | 2010-06-02 12:58:13 -0500 | [diff] [blame] | 102 | |
Dam Sunwoo | ac161c1 | 2012-11-02 11:32:00 -0500 | [diff] [blame] | 103 | const bool CurThreadInfoImplemented = false; |
| 104 | const int CurThreadInfoReg = -1; |
| 105 | |
Ali Saidi | b8ec214 | 2010-06-02 12:58:16 -0500 | [diff] [blame] | 106 | enum InterruptTypes |
| 107 | { |
| 108 | INT_RST, |
| 109 | INT_ABT, |
| 110 | INT_IRQ, |
| 111 | INT_FIQ, |
Geoffrey Blake | 5f425b8 | 2011-08-19 15:08:07 -0500 | [diff] [blame] | 112 | INT_SEV, // Special interrupt for recieving SEV's |
ARM gem5 Developers | 612f8f0 | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 113 | INT_VIRT_IRQ, |
| 114 | INT_VIRT_FIQ, |
Ali Saidi | b8ec214 | 2010-06-02 12:58:16 -0500 | [diff] [blame] | 115 | NumInterruptTypes |
| 116 | }; |
Steve Reinhardt | c69d48f | 2011-01-03 14:35:43 -0800 | [diff] [blame] | 117 | } // namespace ArmISA |
Stephen Hines | 7a7c4c5 | 2009-04-05 18:53:15 -0700 | [diff] [blame] | 118 | |
| 119 | using namespace ArmISA; |
| 120 | |
| 121 | #endif // __ARCH_ARM_ISA_TRAITS_HH__ |