Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 1 | /* |
Andreas Sandberg | 7be9d4e | 2015-03-02 04:00:44 -0500 | [diff] [blame] | 2 | * Copyright (c) 2010-2015 ARM Limited |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 3 | * All rights reserved |
| 4 | * |
| 5 | * The license below extends only to copyright in the software and shall |
| 6 | * not be construed as granting a license to any other intellectual |
| 7 | * property including but not limited to intellectual property relating |
| 8 | * to a hardware implementation of the functionality of the software |
| 9 | * licensed hereunder. You may use the software subject to the license |
| 10 | * terms below provided that you ensure that this notice is replicated |
| 11 | * unmodified and in its entirety in all distributions of the software, |
| 12 | * modified or unmodified, in source code or in binary form. |
| 13 | * |
| 14 | * Copyright (c) 2005 The Regents of The University of Michigan |
| 15 | * All rights reserved. |
| 16 | * |
| 17 | * Redistribution and use in source and binary forms, with or without |
| 18 | * modification, are permitted provided that the following conditions are |
| 19 | * met: redistributions of source code must retain the above copyright |
| 20 | * notice, this list of conditions and the following disclaimer; |
| 21 | * redistributions in binary form must reproduce the above copyright |
| 22 | * notice, this list of conditions and the following disclaimer in the |
| 23 | * documentation and/or other materials provided with the distribution; |
| 24 | * neither the name of the copyright holders nor the names of its |
| 25 | * contributors may be used to endorse or promote products derived from |
| 26 | * this software without specific prior written permission. |
| 27 | * |
| 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 29 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 30 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 31 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 32 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 33 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 34 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 35 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 36 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 38 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 39 | * |
| 40 | * Authors: Ali Saidi |
Andreas Sandberg | 7be9d4e | 2015-03-02 04:00:44 -0500 | [diff] [blame] | 41 | * Andreas Sandberg |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 42 | */ |
| 43 | |
| 44 | |
| 45 | /** @file |
| 46 | * Implementiation of a PL011 UART |
| 47 | */ |
| 48 | |
| 49 | #ifndef __DEV_ARM_PL011_H__ |
| 50 | #define __DEV_ARM_PL011_H__ |
| 51 | |
Steve Reinhardt | 2737650 | 2013-07-11 21:56:39 -0500 | [diff] [blame] | 52 | #include "dev/arm/amba_device.hh" |
Andreas Sandberg | 20de3bb | 2017-07-20 11:58:06 +0100 | [diff] [blame] | 53 | #include "dev/serial/uart.hh" |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 54 | |
Andreas Sandberg | 81be8b9 | 2012-10-25 14:05:24 +0100 | [diff] [blame] | 55 | class BaseGic; |
Andreas Sandberg | 7be9d4e | 2015-03-02 04:00:44 -0500 | [diff] [blame] | 56 | struct Pl011Params; |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 57 | |
Steve Reinhardt | 2737650 | 2013-07-11 21:56:39 -0500 | [diff] [blame] | 58 | class Pl011 : public Uart, public AmbaDevice |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 59 | { |
Andreas Sandberg | 7be9d4e | 2015-03-02 04:00:44 -0500 | [diff] [blame] | 60 | public: |
| 61 | Pl011(const Pl011Params *p); |
| 62 | |
Andreas Hansson | 22c0419 | 2015-10-12 04:07:59 -0400 | [diff] [blame] | 63 | void serialize(CheckpointOut &cp) const override; |
| 64 | void unserialize(CheckpointIn &cp) override; |
Andreas Sandberg | 7be9d4e | 2015-03-02 04:00:44 -0500 | [diff] [blame] | 65 | |
| 66 | public: // PioDevice |
Andreas Hansson | 22c0419 | 2015-10-12 04:07:59 -0400 | [diff] [blame] | 67 | Tick read(PacketPtr pkt) override; |
| 68 | Tick write(PacketPtr pkt) override; |
Andreas Sandberg | 7be9d4e | 2015-03-02 04:00:44 -0500 | [diff] [blame] | 69 | |
| 70 | public: // Uart |
Andreas Hansson | 22c0419 | 2015-10-12 04:07:59 -0400 | [diff] [blame] | 71 | void dataAvailable() override; |
Andreas Sandberg | 7be9d4e | 2015-03-02 04:00:44 -0500 | [diff] [blame] | 72 | |
| 73 | |
| 74 | protected: // Interrupt handling |
| 75 | /** Function to generate interrupt */ |
| 76 | void generateInterrupt(); |
| 77 | |
| 78 | /** |
| 79 | * Assign new interrupt values and update interrupt signals |
| 80 | * |
| 81 | * A new interrupt is scheduled signalled if the set of unmasked |
| 82 | * interrupts goes empty to non-empty. Conversely, if the set of |
| 83 | * unmasked interrupts goes from non-empty to empty, the interrupt |
| 84 | * signal is cleared. |
| 85 | * |
| 86 | * @param ints New <i>raw</i> interrupt status |
| 87 | * @param mask New interrupt mask |
| 88 | */ |
| 89 | void setInterrupts(uint16_t ints, uint16_t mask); |
| 90 | /** |
| 91 | * Convenience function to update the interrupt mask |
| 92 | * |
| 93 | * @see setInterrupts |
| 94 | * @param mask New interrupt mask |
| 95 | */ |
| 96 | void setInterruptMask(uint16_t mask) { setInterrupts(rawInt, mask); } |
| 97 | /** |
| 98 | * Convenience function to raise a new interrupt |
| 99 | * |
| 100 | * @see setInterrupts |
| 101 | * @param ints Set of interrupts to raise |
| 102 | */ |
| 103 | void raiseInterrupts(uint16_t ints) { setInterrupts(rawInt | ints, imsc); } |
| 104 | /** |
| 105 | * Convenience function to clear interrupts |
| 106 | * |
| 107 | * @see setInterrupts |
| 108 | * @param ints Set of interrupts to clear |
| 109 | */ |
| 110 | void clearInterrupts(uint16_t ints) { setInterrupts(rawInt & ~ints, imsc); } |
| 111 | |
| 112 | /** Masked interrupt status register */ |
Andreas Hansson | 12eb034 | 2016-01-11 05:52:20 -0500 | [diff] [blame] | 113 | inline uint16_t maskInt() const { return rawInt & imsc; } |
Andreas Sandberg | 7be9d4e | 2015-03-02 04:00:44 -0500 | [diff] [blame] | 114 | |
| 115 | /** Wrapper to create an event out of the thing */ |
Sean Wilson | 475f613 | 2017-06-07 13:23:09 -0500 | [diff] [blame] | 116 | EventFunctionWrapper intEvent; |
Andreas Sandberg | 7be9d4e | 2015-03-02 04:00:44 -0500 | [diff] [blame] | 117 | |
| 118 | protected: // Registers |
Ali Saidi | c0ca01e | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 119 | static const uint64_t AMBA_ID = ULL(0xb105f00d00341011); |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 120 | static const int UART_DR = 0x000; |
| 121 | static const int UART_FR = 0x018; |
| 122 | static const int UART_FR_CTS = 0x001; |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 123 | static const int UART_FR_RXFE = 0x010; |
Bjoern A. Zeeb | a6b00c0 | 2016-05-19 15:19:35 -0500 | [diff] [blame] | 124 | static const int UART_FR_TXFF = 0x020; |
| 125 | static const int UART_FR_RXFF = 0x040; |
| 126 | static const int UART_FR_TXFE = 0x080; |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 127 | static const int UART_IBRD = 0x024; |
| 128 | static const int UART_FBRD = 0x028; |
| 129 | static const int UART_LCRH = 0x02C; |
| 130 | static const int UART_CR = 0x030; |
| 131 | static const int UART_IFLS = 0x034; |
| 132 | static const int UART_IMSC = 0x038; |
| 133 | static const int UART_RIS = 0x03C; |
| 134 | static const int UART_MIS = 0x040; |
| 135 | static const int UART_ICR = 0x044; |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 136 | |
Andreas Sandberg | 7be9d4e | 2015-03-02 04:00:44 -0500 | [diff] [blame] | 137 | static const uint16_t UART_RIINTR = 1 << 0; |
| 138 | static const uint16_t UART_CTSINTR = 1 << 1; |
| 139 | static const uint16_t UART_CDCINTR = 1 << 2; |
| 140 | static const uint16_t UART_DSRINTR = 1 << 3; |
| 141 | static const uint16_t UART_RXINTR = 1 << 4; |
| 142 | static const uint16_t UART_TXINTR = 1 << 5; |
| 143 | static const uint16_t UART_RTINTR = 1 << 6; |
| 144 | static const uint16_t UART_FEINTR = 1 << 7; |
| 145 | static const uint16_t UART_PEINTR = 1 << 8; |
| 146 | static const uint16_t UART_BEINTR = 1 << 9; |
| 147 | static const uint16_t UART_OEINTR = 1 << 10; |
| 148 | |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 149 | uint16_t control; |
| 150 | |
| 151 | /** fractional baud rate divisor. Not used for anything but reporting |
| 152 | * written value */ |
| 153 | uint16_t fbrd; |
| 154 | |
| 155 | /** integer baud rate divisor. Not used for anything but reporting |
| 156 | * written value */ |
| 157 | uint16_t ibrd; |
| 158 | |
| 159 | /** Line control register. Not used for anything but reporting |
| 160 | * written value */ |
| 161 | uint16_t lcrh; |
| 162 | |
| 163 | /** interrupt fifo level register. Not used for anything but reporting |
| 164 | * written value */ |
| 165 | uint16_t ifls; |
| 166 | |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 167 | /** interrupt mask register. */ |
Andreas Sandberg | 7be9d4e | 2015-03-02 04:00:44 -0500 | [diff] [blame] | 168 | uint16_t imsc; |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 169 | |
| 170 | /** raw interrupt status register */ |
Andreas Sandberg | 7be9d4e | 2015-03-02 04:00:44 -0500 | [diff] [blame] | 171 | uint16_t rawInt; |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 172 | |
Andreas Sandberg | 7be9d4e | 2015-03-02 04:00:44 -0500 | [diff] [blame] | 173 | protected: // Configuration |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 174 | /** Gic to use for interrupting */ |
Andreas Sandberg | 7be9d4e | 2015-03-02 04:00:44 -0500 | [diff] [blame] | 175 | BaseGic * const gic; |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 176 | |
| 177 | /** Should the simulation end on an EOT */ |
Andreas Sandberg | 7be9d4e | 2015-03-02 04:00:44 -0500 | [diff] [blame] | 178 | const bool endOnEOT; |
| 179 | |
| 180 | /** Interrupt number to generate */ |
| 181 | const int intNum; |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 182 | |
| 183 | /** Delay before interrupting */ |
Andreas Sandberg | 7be9d4e | 2015-03-02 04:00:44 -0500 | [diff] [blame] | 184 | const Tick intDelay; |
Ali Saidi | 8ed4f0a | 2010-08-23 11:18:40 -0500 | [diff] [blame] | 185 | }; |
| 186 | |
| 187 | #endif //__DEV_ARM_PL011_H__ |