Lisa Hsu | 161b8d1 | 2006-12-01 01:24:01 -0500 | [diff] [blame] | 1 | # Copyright (c) 2006 The Regents of The University of Michigan |
| 2 | # All rights reserved. |
| 3 | # |
| 4 | # Redistribution and use in source and binary forms, with or without |
| 5 | # modification, are permitted provided that the following conditions are |
| 6 | # met: redistributions of source code must retain the above copyright |
| 7 | # notice, this list of conditions and the following disclaimer; |
| 8 | # redistributions in binary form must reproduce the above copyright |
| 9 | # notice, this list of conditions and the following disclaimer in the |
| 10 | # documentation and/or other materials provided with the distribution; |
| 11 | # neither the name of the copyright holders nor the names of its |
| 12 | # contributors may be used to endorse or promote products derived from |
| 13 | # this software without specific prior written permission. |
| 14 | # |
| 15 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 16 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 17 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 18 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 19 | # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 20 | # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 21 | # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 22 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 23 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 24 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 25 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | # |
| 27 | # Authors: Lisa Hsu |
| 28 | |
| 29 | import m5 |
| 30 | from m5.objects import * |
Nathan Binkert | 9a8cb7d | 2009-09-22 15:24:16 -0700 | [diff] [blame] | 31 | m5.util.addToPath('../configs/common') |
Lisa Hsu | 161b8d1 | 2006-12-01 01:24:01 -0500 | [diff] [blame] | 32 | from FSConfig import * |
| 33 | from Benchmarks import * |
| 34 | |
Andreas Hansson | 3bc4ecd | 2013-05-30 12:54:14 -0400 | [diff] [blame] | 35 | test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory, |
Lisa Hsu | 161b8d1 | 2006-12-01 01:24:01 -0500 | [diff] [blame] | 36 | SysConfig('netperf-stream-client.rcS')) |
Akash Bagdia | 7d7ab73 | 2013-06-27 05:49:49 -0400 | [diff] [blame^] | 37 | |
| 38 | # Create the system clock domain |
| 39 | test_sys.clk_domain = SrcClockDomain(clock = '1GHz') |
| 40 | |
Lisa Hsu | 161b8d1 | 2006-12-01 01:24:01 -0500 | [diff] [blame] | 41 | test_sys.cpu = AtomicSimpleCPU(cpu_id=0) |
Andreas Hansson | 32eae80 | 2012-03-02 09:21:48 -0500 | [diff] [blame] | 42 | # create the interrupt controller |
| 43 | test_sys.cpu.createInterruptController() |
Gabe Black | 00f24ae | 2011-02-03 20:23:00 -0800 | [diff] [blame] | 44 | test_sys.cpu.connectAllPorts(test_sys.membus) |
Akash Bagdia | 7d7ab73 | 2013-06-27 05:49:49 -0400 | [diff] [blame^] | 45 | |
| 46 | # Create a seperate clock domain for components that should run at |
| 47 | # CPUs frequency |
| 48 | test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz') |
| 49 | |
| 50 | # Create a separate clock domain for Ethernet |
| 51 | test_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz') |
| 52 | |
Andreas Hansson | 2208ea0 | 2012-01-17 12:55:09 -0600 | [diff] [blame] | 53 | # In contrast to the other (one-system) Tsunami configurations we do |
| 54 | # not have an IO cache but instead rely on an IO bridge for accesses |
| 55 | # from masters on the IO bus to the memory bus |
Andreas Hansson | e65de3f | 2013-01-07 13:05:38 -0500 | [diff] [blame] | 56 | test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) |
Andreas Hansson | 5a9a743 | 2012-02-13 06:43:09 -0500 | [diff] [blame] | 57 | test_sys.iobridge.slave = test_sys.iobus.master |
| 58 | test_sys.iobridge.master = test_sys.membus.slave |
Lisa Hsu | 161b8d1 | 2006-12-01 01:24:01 -0500 | [diff] [blame] | 59 | |
Andreas Hansson | 3bc4ecd | 2013-05-30 12:54:14 -0400 | [diff] [blame] | 60 | drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory, |
Lisa Hsu | 161b8d1 | 2006-12-01 01:24:01 -0500 | [diff] [blame] | 61 | SysConfig('netperf-server.rcS')) |
Akash Bagdia | 7d7ab73 | 2013-06-27 05:49:49 -0400 | [diff] [blame^] | 62 | # Create the system clock domain |
| 63 | drive_sys.clk_domain = SrcClockDomain(clock = '1GHz') |
Lisa Hsu | 161b8d1 | 2006-12-01 01:24:01 -0500 | [diff] [blame] | 64 | drive_sys.cpu = AtomicSimpleCPU(cpu_id=0) |
Andreas Hansson | 32eae80 | 2012-03-02 09:21:48 -0500 | [diff] [blame] | 65 | # create the interrupt controller |
| 66 | drive_sys.cpu.createInterruptController() |
Gabe Black | 00f24ae | 2011-02-03 20:23:00 -0800 | [diff] [blame] | 67 | drive_sys.cpu.connectAllPorts(drive_sys.membus) |
Akash Bagdia | 7d7ab73 | 2013-06-27 05:49:49 -0400 | [diff] [blame^] | 68 | |
| 69 | # Create a seperate clock domain for components that should run at |
| 70 | # CPUs frequency |
| 71 | drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz') |
| 72 | |
| 73 | # Create a separate clock domain for Ethernet |
| 74 | drive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz') |
| 75 | |
Andreas Hansson | e65de3f | 2013-01-07 13:05:38 -0500 | [diff] [blame] | 76 | drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges) |
Andreas Hansson | 5a9a743 | 2012-02-13 06:43:09 -0500 | [diff] [blame] | 77 | drive_sys.iobridge.slave = drive_sys.iobus.master |
| 78 | drive_sys.iobridge.master = drive_sys.membus.slave |
Lisa Hsu | 161b8d1 | 2006-12-01 01:24:01 -0500 | [diff] [blame] | 79 | |
Gabe Black | ec20ee2 | 2012-01-28 07:24:34 -0800 | [diff] [blame] | 80 | root = makeDualRoot(True, test_sys, drive_sys, "ethertrace") |
Lisa Hsu | 161b8d1 | 2006-12-01 01:24:01 -0500 | [diff] [blame] | 81 | |
| 82 | maxtick = 199999999 |