Ali Saidi | 0e805e1 | 2004-01-21 20:14:10 -0500 | [diff] [blame] | 1 | /* |
Steve Reinhardt | ad8b963 | 2005-06-05 05:16:00 -0400 | [diff] [blame] | 2 | * Copyright (c) 2004-2005 The Regents of The University of Michigan |
Ali Saidi | 0e805e1 | 2004-01-21 20:14:10 -0500 | [diff] [blame] | 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions are |
| 7 | * met: redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer; |
| 9 | * redistributions in binary form must reproduce the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer in the |
| 11 | * documentation and/or other materials provided with the distribution; |
| 12 | * neither the name of the copyright holders nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived from |
| 14 | * this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 19 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 20 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 22 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 26 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Ali Saidi | cb0cf2d | 2006-05-31 19:26:56 -0400 | [diff] [blame] | 27 | * |
| 28 | * Authors: Ali Saidi |
| 29 | * Andrew Schultz |
| 30 | * Miguel Serrano |
Ali Saidi | 0e805e1 | 2004-01-21 20:14:10 -0500 | [diff] [blame] | 31 | */ |
| 32 | |
Ali Saidi | 8bbaaa7 | 2005-06-04 23:56:53 -0400 | [diff] [blame] | 33 | /** @file |
| 34 | * Tsunami I/O Space mapping including RTC/timer interrupts |
Ali Saidi | 0e805e1 | 2004-01-21 20:14:10 -0500 | [diff] [blame] | 35 | */ |
| 36 | |
Nathan Binkert | 92ed0df | 2005-02-21 17:32:57 -0500 | [diff] [blame] | 37 | #ifndef __DEV_TSUNAMI_IO_HH__ |
| 38 | #define __DEV_TSUNAMI_IO_HH__ |
Ali Saidi | 0e805e1 | 2004-01-21 20:14:10 -0500 | [diff] [blame] | 39 | |
Gabe Black | dd14c86 | 2006-11-06 19:45:00 -0500 | [diff] [blame] | 40 | #include "dev/alpha/tsunami.hh" |
Andreas Sandberg | c0ab527 | 2012-11-02 11:32:01 -0500 | [diff] [blame] | 41 | #include "dev/alpha/tsunami_cchip.hh" |
Gabe Black | 4f9a040 | 2008-06-12 00:54:48 -0400 | [diff] [blame] | 42 | #include "dev/intel_8254_timer.hh" |
Nathan Binkert | abc76f2 | 2007-07-23 21:51:38 -0700 | [diff] [blame] | 43 | #include "dev/io_device.hh" |
Nathan Binkert | 39a0556 | 2011-04-15 10:44:06 -0700 | [diff] [blame] | 44 | #include "dev/mc146818.hh" |
Nathan Binkert | abc76f2 | 2007-07-23 21:51:38 -0700 | [diff] [blame] | 45 | #include "params/TsunamiIO.hh" |
Ali Saidi | 54b49f9 | 2004-06-26 21:26:28 -0400 | [diff] [blame] | 46 | #include "sim/eventq.hh" |
Ali Saidi | 0e805e1 | 2004-01-21 20:14:10 -0500 | [diff] [blame] | 47 | |
Ali Saidi | 8bbaaa7 | 2005-06-04 23:56:53 -0400 | [diff] [blame] | 48 | /** |
Ali Saidi | 9d0aa13 | 2004-05-30 17:45:46 -0400 | [diff] [blame] | 49 | * Tsunami I/O device is a catch all for all the south bridge stuff we care |
| 50 | * to implement. |
Ali Saidi | 0e805e1 | 2004-01-21 20:14:10 -0500 | [diff] [blame] | 51 | */ |
Ali Saidi | f6fc18f | 2006-04-11 13:42:47 -0400 | [diff] [blame] | 52 | class TsunamiIO : public BasicPioDevice |
Ali Saidi | 0e805e1 | 2004-01-21 20:14:10 -0500 | [diff] [blame] | 53 | { |
Ali Saidi | b7f44f6 | 2004-01-26 13:26:34 -0500 | [diff] [blame] | 54 | |
Ali Saidi | 0e805e1 | 2004-01-21 20:14:10 -0500 | [diff] [blame] | 55 | protected: |
Gabe Black | e5bdae1 | 2008-03-25 02:15:06 -0400 | [diff] [blame] | 56 | |
Nathan Binkert | e063210 | 2008-10-09 04:58:24 -0700 | [diff] [blame] | 57 | class RTC : public MC146818 |
Ali Saidi | f9f4a74 | 2004-01-22 19:02:07 -0500 | [diff] [blame] | 58 | { |
Andrew Schultz | c76675b | 2004-02-05 18:23:16 -0500 | [diff] [blame] | 59 | public: |
Nathan Binkert | e063210 | 2008-10-09 04:58:24 -0700 | [diff] [blame] | 60 | Tsunami *tsunami; |
| 61 | RTC(const std::string &n, const TsunamiIOParams *p); |
Miguel Serrano | b64eae5 | 2005-08-15 16:59:58 -0400 | [diff] [blame] | 62 | |
Gabe Black | e5bdae1 | 2008-03-25 02:15:06 -0400 | [diff] [blame] | 63 | protected: |
| 64 | void handleEvent() |
| 65 | { |
| 66 | //Actually interrupt the processor here |
| 67 | tsunami->cchip->postRTC(); |
| 68 | } |
Miguel Serrano | b64eae5 | 2005-08-15 16:59:58 -0400 | [diff] [blame] | 69 | }; |
Ali Saidi | f9f4a74 | 2004-01-22 19:02:07 -0500 | [diff] [blame] | 70 | |
Ali Saidi | 9d0aa13 | 2004-05-30 17:45:46 -0400 | [diff] [blame] | 71 | /** Mask of the PIC1 */ |
Andrew Schultz | c76675b | 2004-02-05 18:23:16 -0500 | [diff] [blame] | 72 | uint8_t mask1; |
Ali Saidi | 9d0aa13 | 2004-05-30 17:45:46 -0400 | [diff] [blame] | 73 | |
| 74 | /** Mask of the PIC2 */ |
Andrew Schultz | c76675b | 2004-02-05 18:23:16 -0500 | [diff] [blame] | 75 | uint8_t mask2; |
Ali Saidi | 9d0aa13 | 2004-05-30 17:45:46 -0400 | [diff] [blame] | 76 | |
| 77 | /** Mode of PIC1. Not used for anything */ |
Andrew Schultz | c76675b | 2004-02-05 18:23:16 -0500 | [diff] [blame] | 78 | uint8_t mode1; |
Ali Saidi | 9d0aa13 | 2004-05-30 17:45:46 -0400 | [diff] [blame] | 79 | |
| 80 | /** Mode of PIC2. Not used for anything */ |
Andrew Schultz | c76675b | 2004-02-05 18:23:16 -0500 | [diff] [blame] | 81 | uint8_t mode2; |
Ali Saidi | de17a03 | 2004-01-22 00:08:48 -0500 | [diff] [blame] | 82 | |
Ali Saidi | 9d0aa13 | 2004-05-30 17:45:46 -0400 | [diff] [blame] | 83 | /** Raw PIC interrupt register before masking */ |
| 84 | uint8_t picr; //Raw PIC interrput register |
| 85 | |
| 86 | /** Is the pic interrupting right now or not. */ |
Ron Dreslinski | d41c904 | 2004-01-28 19:18:29 -0500 | [diff] [blame] | 87 | bool picInterrupting; |
| 88 | |
Ali Saidi | 9d0aa13 | 2004-05-30 17:45:46 -0400 | [diff] [blame] | 89 | /** A pointer to the Tsunami device which be belong to */ |
Ron Dreslinski | 3ccc0b1 | 2004-01-27 21:36:46 -0500 | [diff] [blame] | 90 | Tsunami *tsunami; |
| 91 | |
Miguel Serrano | b64eae5 | 2005-08-15 16:59:58 -0400 | [diff] [blame] | 92 | /** Intel 8253 Periodic Interval Timer */ |
Gabe Black | 4f9a040 | 2008-06-12 00:54:48 -0400 | [diff] [blame] | 93 | Intel8254Timer pitimer; |
Ali Saidi | b7f44f6 | 2004-01-26 13:26:34 -0500 | [diff] [blame] | 94 | |
Nathan Binkert | e063210 | 2008-10-09 04:58:24 -0700 | [diff] [blame] | 95 | RTC rtc; |
Gabe Black | e5bdae1 | 2008-03-25 02:15:06 -0400 | [diff] [blame] | 96 | |
| 97 | uint8_t rtcAddr; |
Ali Saidi | b7f44f6 | 2004-01-26 13:26:34 -0500 | [diff] [blame] | 98 | |
Ali Saidi | 9d0aa13 | 2004-05-30 17:45:46 -0400 | [diff] [blame] | 99 | /** The interval is set via two writes to the PIT. |
| 100 | * This variable contains a flag as to how many writes have happened, and |
| 101 | * the time so far. |
| 102 | */ |
Miguel Serrano | b64eae5 | 2005-08-15 16:59:58 -0400 | [diff] [blame] | 103 | uint16_t timerData; |
Ali Saidi | f9f4a74 | 2004-01-22 19:02:07 -0500 | [diff] [blame] | 104 | |
Ali Saidi | 0e805e1 | 2004-01-21 20:14:10 -0500 | [diff] [blame] | 105 | public: |
Ali Saidi | 6010f63 | 2004-06-01 17:36:38 -0400 | [diff] [blame] | 106 | /** |
| 107 | * Return the freqency of the RTC |
| 108 | * @return interrupt rate of the RTC |
| 109 | */ |
Nathan Binkert | 5eab6c4 | 2005-04-11 15:32:06 -0400 | [diff] [blame] | 110 | Tick frequency() const; |
Ron Dreslinski | 3ccc0b1 | 2004-01-27 21:36:46 -0500 | [diff] [blame] | 111 | |
Ali Saidi | e8b6eb4 | 2006-04-10 14:14:06 -0400 | [diff] [blame] | 112 | public: |
Nathan Binkert | abc76f2 | 2007-07-23 21:51:38 -0700 | [diff] [blame] | 113 | typedef TsunamiIOParams Params; |
Ali Saidi | 9d0aa13 | 2004-05-30 17:45:46 -0400 | [diff] [blame] | 114 | /** |
| 115 | * Initialize all the data for devices supported by Tsunami I/O. |
Ali Saidi | e8b6eb4 | 2006-04-10 14:14:06 -0400 | [diff] [blame] | 116 | * @param p pointer to Params struct |
Ali Saidi | 9d0aa13 | 2004-05-30 17:45:46 -0400 | [diff] [blame] | 117 | */ |
Nathan Binkert | abc76f2 | 2007-07-23 21:51:38 -0700 | [diff] [blame] | 118 | TsunamiIO(const Params *p); |
| 119 | |
| 120 | const Params * |
| 121 | params() const |
| 122 | { |
| 123 | return dynamic_cast<const Params *>(_params); |
| 124 | } |
Ali Saidi | 0e805e1 | 2004-01-21 20:14:10 -0500 | [diff] [blame] | 125 | |
Andreas Hansson | 2ac04c1 | 2015-10-12 04:08:01 -0400 | [diff] [blame] | 126 | Tick read(PacketPtr pkt) override; |
| 127 | Tick write(PacketPtr pkt) override; |
Ali Saidi | 0e805e1 | 2004-01-21 20:14:10 -0500 | [diff] [blame] | 128 | |
Ali Saidi | 9d0aa13 | 2004-05-30 17:45:46 -0400 | [diff] [blame] | 129 | /** |
| 130 | * Post an PIC interrupt to the CPU via the CChip |
| 131 | * @param bitvector interrupt to post. |
| 132 | */ |
Ron Dreslinski | d41c904 | 2004-01-28 19:18:29 -0500 | [diff] [blame] | 133 | void postPIC(uint8_t bitvector); |
Ali Saidi | 9d0aa13 | 2004-05-30 17:45:46 -0400 | [diff] [blame] | 134 | |
| 135 | /** |
| 136 | * Clear a posted interrupt |
| 137 | * @param bitvector interrupt to clear |
| 138 | */ |
Ron Dreslinski | d41c904 | 2004-01-28 19:18:29 -0500 | [diff] [blame] | 139 | void clearPIC(uint8_t bitvector); |
| 140 | |
Andreas Hansson | 22c0419 | 2015-10-12 04:07:59 -0400 | [diff] [blame] | 141 | void serialize(CheckpointOut &cp) const override; |
| 142 | void unserialize(CheckpointIn &cp) override; |
Ali Saidi | 02f69b9 | 2004-06-10 13:30:58 -0400 | [diff] [blame] | 143 | |
Cagdas Dirik | 02c376a | 2015-01-03 17:51:48 -0600 | [diff] [blame] | 144 | /** |
| 145 | * Start running. |
| 146 | */ |
Andreas Hansson | 2ac04c1 | 2015-10-12 04:08:01 -0400 | [diff] [blame] | 147 | void startup() override; |
Cagdas Dirik | 02c376a | 2015-01-03 17:51:48 -0600 | [diff] [blame] | 148 | |
Ali Saidi | 0e805e1 | 2004-01-21 20:14:10 -0500 | [diff] [blame] | 149 | }; |
| 150 | |
Nathan Binkert | 92ed0df | 2005-02-21 17:32:57 -0500 | [diff] [blame] | 151 | #endif // __DEV_TSUNAMI_IO_HH__ |