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Stephen Hines7a7c4c52009-04-05 18:53:15 -07001/*
ARM gem5 Developers612f8f02014-01-24 15:29:34 -06002 * Copyright (c) 2010, 2012-2013 ARM Limited
Ali Saidi521d68c2010-10-01 16:03:27 -05003 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
Stephen Hines7a7c4c52009-04-05 18:53:15 -070014 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 * Nathan Binkert
43 * Stephen Hines
44 */
45
Brandon Potter7a8dda42016-11-09 14:27:37 -060046#include "arch/arm/vtophys.hh"
47
Stephen Hines7a7c4c52009-04-05 18:53:15 -070048#include <string>
49
ARM gem5 Developers612f8f02014-01-24 15:29:34 -060050#include "arch/arm/faults.hh"
Ali Saidi521d68c2010-10-01 16:03:27 -050051#include "arch/arm/table_walker.hh"
52#include "arch/arm/tlb.hh"
Stephen Hines7a7c4c52009-04-05 18:53:15 -070053#include "base/chunk_generator.hh"
54#include "base/trace.hh"
55#include "cpu/thread_context.hh"
Andreas Hanssonf85286b2012-01-17 12:55:08 -060056#include "mem/fs_translating_port_proxy.hh"
Stephen Hines7a7c4c52009-04-05 18:53:15 -070057
58using namespace std;
59using namespace ArmISA;
60
61Addr
62ArmISA::vtophys(Addr vaddr)
63{
Ali Saidi521d68c2010-10-01 16:03:27 -050064 fatal("VTOPHYS: Can't convert vaddr to paddr on ARM without a thread context");
Stephen Hines7a7c4c52009-04-05 18:53:15 -070065}
66
Andreas Sandberg34dcd902015-03-02 04:00:27 -050067static std::pair<bool, Addr>
68try_translate(ThreadContext *tc, Addr addr)
Stephen Hines7a7c4c52009-04-05 18:53:15 -070069{
ARM gem5 Developers612f8f02014-01-24 15:29:34 -060070 Fault fault;
71 // Set up a functional memory Request to pass to the TLB
72 // to get it to translate the vaddr to a paddr
Mitch Hayengac75ff712016-04-07 09:30:20 -050073 Request req(0, addr, 64, 0x40, -1, 0, 0);
Ali Saidi521d68c2010-10-01 16:03:27 -050074 ArmISA::TLB *tlb;
75
ARM gem5 Developers612f8f02014-01-24 15:29:34 -060076 // Check the TLBs for a translation
77 // It's possible that there is a valid translation in the tlb
Ali Saidi521d68c2010-10-01 16:03:27 -050078 // that is no loger valid in the page table in memory
79 // so we need to check here first
ARM gem5 Developers612f8f02014-01-24 15:29:34 -060080 //
81 // Calling translateFunctional invokes a table-walk if required
82 // so we should always succeed
Ali Saidi521d68c2010-10-01 16:03:27 -050083 tlb = static_cast<ArmISA::TLB*>(tc->getDTBPtr());
ARM gem5 Developers612f8f02014-01-24 15:29:34 -060084 fault = tlb->translateFunctional(&req, tc, BaseTLB::Read, TLB::NormalTran);
85 if (fault == NoFault)
Andreas Sandberg34dcd902015-03-02 04:00:27 -050086 return std::make_pair(true, req.getPaddr());
Ali Saidi521d68c2010-10-01 16:03:27 -050087
88 tlb = static_cast<ArmISA::TLB*>(tc->getITBPtr());
ARM gem5 Developers612f8f02014-01-24 15:29:34 -060089 fault = tlb->translateFunctional(&req, tc, BaseTLB::Read, TLB::NormalTran);
90 if (fault == NoFault)
Andreas Sandberg34dcd902015-03-02 04:00:27 -050091 return std::make_pair(true, req.getPaddr());
Ali Saidi521d68c2010-10-01 16:03:27 -050092
Andreas Sandberg34dcd902015-03-02 04:00:27 -050093 return std::make_pair(false, 0);
94}
95
96Addr
97ArmISA::vtophys(ThreadContext *tc, Addr addr)
98{
99 const std::pair<bool, Addr> translation(try_translate(tc, addr));
100
101 if (translation.first)
102 return translation.second;
103 else
104 panic("Table walkers support functional accesses. We should never get here\n");
Stephen Hines7a7c4c52009-04-05 18:53:15 -0700105}
106
Ali Saidi521d68c2010-10-01 16:03:27 -0500107bool
108ArmISA::virtvalid(ThreadContext *tc, Addr vaddr)
109{
Andreas Sandberg34dcd902015-03-02 04:00:27 -0500110 const std::pair<bool, Addr> translation(try_translate(tc, vaddr));
111
112 return translation.first;
Ali Saidi521d68c2010-10-01 16:03:27 -0500113}
114
115