| Real time: Mar/06/2013 20:42:21 |
| |
| Profiler Stats |
| -------------- |
| Elapsed_time_in_seconds: 1 |
| Elapsed_time_in_minutes: 0.0166667 |
| Elapsed_time_in_hours: 0.000277778 |
| Elapsed_time_in_days: 1.15741e-05 |
| |
| Virtual_time_in_seconds: 0.82 |
| Virtual_time_in_minutes: 0.0136667 |
| Virtual_time_in_hours: 0.000227778 |
| Virtual_time_in_days: 9.49074e-06 |
| |
| Ruby_current_time: 117611 |
| Ruby_start_time: 0 |
| Ruby_cycles: 117611 |
| |
| mbytes_resident: 56.1211 |
| mbytes_total: 148.367 |
| resident_ratio: 0.378311 |
| |
| ruby_cycles_executed: [ 117612 ] |
| |
| Busy Controller Counts: |
| L1Cache-0:0 |
| L2Cache-0:0 |
| |
| Directory-0:0 |
| |
| Busy Bank Count:0 |
| |
| sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8449 average: 1 | standard deviation: 0 | 0 8449 ] |
| |
| All Non-Zero Cycle Demand Cache Accesses |
| ---------------------------------------- |
| miss_latency: [binsize: 1 max: 113 count: 8448 average: 12.9218 | standard deviation: 24.261 | 0 0 0 7086 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 88 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 316 301 294 68 55 13 19 22 2 2 1 2 1 0 0 0 0 0 0 0 3 2 3 0 0 0 0 0 2 0 0 1 1 0 0 0 0 0 0 0 1 ] |
| miss_latency_LD: [binsize: 1 max: 113 count: 1183 average: 29.4725 | standard deviation: 33.3864 | 0 0 0 658 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 99 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 136 145 102 9 2 2 3 3 1 0 0 1 0 0 0 0 0 0 0 0 2 2 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 ] |
| miss_latency_ST: [binsize: 1 max: 95 count: 865 average: 15.259 | standard deviation: 26.186 | 0 0 0 674 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 47 44 1 2 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 2 ] |
| miss_latency_IFETCH: [binsize: 1 max: 105 count: 6400 average: 9.54656 | standard deviation: 20.3893 | 0 0 0 5754 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 180 156 161 12 9 10 14 19 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 ] |
| miss_latency_NULL: [binsize: 1 max: 113 count: 8448 average: 12.9218 | standard deviation: 24.261 | 0 0 0 7086 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 88 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 316 301 294 68 55 13 19 22 2 2 1 2 1 0 0 0 0 0 0 0 3 2 3 0 0 0 0 0 2 0 0 1 1 0 0 0 0 0 0 0 1 ] |
| miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| imcomplete_wCC_Times: 0 |
| miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| imcomplete_dir_Times: 0 |
| miss_latency_LD_NULL: [binsize: 1 max: 113 count: 1183 average: 29.4725 | standard deviation: 33.3864 | 0 0 0 658 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 99 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 136 145 102 9 2 2 3 3 1 0 0 1 0 0 0 0 0 0 0 0 2 2 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 ] |
| miss_latency_ST_NULL: [binsize: 1 max: 95 count: 865 average: 15.259 | standard deviation: 26.186 | 0 0 0 674 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 47 44 1 2 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 2 ] |
| miss_latency_IFETCH_NULL: [binsize: 1 max: 105 count: 6400 average: 9.54656 | standard deviation: 20.3893 | 0 0 0 5754 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 65 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 180 156 161 12 9 10 14 19 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 ] |
| |
| All Non-Zero Cycle SW Prefetch Requests |
| ------------------------------------ |
| prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| Request vs. RubySystem State Profile |
| -------------------------------- |
| |
| |
| filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| |
| Message Delayed Cycles |
| ---------------------- |
| Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] |
| |
| Resource Usage |
| -------------- |
| page_size: 4096 |
| user_time: 0 |
| system_time: 0 |
| page_reclaims: 13682 |
| page_faults: 0 |
| swaps: 0 |
| block_inputs: 0 |
| block_outputs: 96 |
| |
| Network Stats |
| ------------- |
| |
| total_msg_count_Request_Control: 7413 59304 |
| total_msg_count_Response_Data: 6654 479088 |
| total_msg_count_ResponseL2hit_Data: 759 54648 |
| total_msg_count_Writeback_Data: 4644 334368 |
| total_msg_count_Writeback_Control: 17379 139032 |
| total_msg_count_Unblock_Control: 7413 59304 |
| total_msgs: 44262 total_bytes: 1125744 |
| |
| switch_0_inlinks: 2 |
| switch_0_outlinks: 2 |
| links_utilized_percent_switch_0: 6.3506 |
| links_utilized_percent_switch_0_link_0: 5.78687 bw: 16000 base_latency: 1 |
| links_utilized_percent_switch_0_link_1: 6.91432 bw: 16000 base_latency: 1 |
| |
| outgoing_messages_switch_0_link_0_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 253 18216 [ 0 0 253 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_0_link_0_Writeback_Control: 1354 10832 [ 1354 0 0 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_0_link_1_Request_Control: 1362 10896 [ 1362 0 0 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_0_link_1_Writeback_Data: 1354 97488 [ 0 0 1354 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_0_link_1_Writeback_Control: 1354 10832 [ 1354 0 0 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_0_link_1_Unblock_Control: 1362 10896 [ 0 0 1362 0 0 0 0 0 0 0 ] base_latency: 1 |
| |
| switch_1_inlinks: 2 |
| switch_1_outlinks: 2 |
| links_utilized_percent_switch_1: 9.97058 |
| links_utilized_percent_switch_1_link_0: 11.6222 bw: 16000 base_latency: 1 |
| links_utilized_percent_switch_1_link_1: 8.31895 bw: 16000 base_latency: 1 |
| |
| outgoing_messages_switch_1_link_0_Request_Control: 1362 10896 [ 1362 0 0 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_1_link_0_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_1_link_0_Writeback_Data: 1354 97488 [ 0 0 1354 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_1_link_0_Writeback_Control: 2447 19576 [ 1354 1093 0 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_1_link_0_Unblock_Control: 1362 10896 [ 0 0 1362 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_1_link_1_Request_Control: 1109 8872 [ 0 1109 0 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_1_link_1_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 253 18216 [ 0 0 253 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_1_link_1_Writeback_Data: 194 13968 [ 0 0 194 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_1_link_1_Writeback_Control: 3346 26768 [ 1354 1093 899 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_1_link_1_Unblock_Control: 1109 8872 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 |
| |
| switch_2_inlinks: 2 |
| switch_2_outlinks: 2 |
| links_utilized_percent_switch_2: 3.61998 |
| links_utilized_percent_switch_2_link_0: 2.53208 bw: 16000 base_latency: 1 |
| links_utilized_percent_switch_2_link_1: 4.70789 bw: 16000 base_latency: 1 |
| |
| outgoing_messages_switch_2_link_0_Request_Control: 1109 8872 [ 0 1109 0 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_2_link_0_Writeback_Data: 194 13968 [ 0 0 194 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_2_link_0_Writeback_Control: 1992 15936 [ 0 1093 899 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_2_link_0_Unblock_Control: 1109 8872 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_2_link_1_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_2_link_1_Writeback_Control: 1093 8744 [ 0 1093 0 0 0 0 0 0 0 0 ] base_latency: 1 |
| |
| switch_3_inlinks: 3 |
| switch_3_outlinks: 3 |
| links_utilized_percent_switch_3: 6.64705 |
| links_utilized_percent_switch_3_link_0: 5.78687 bw: 16000 base_latency: 1 |
| links_utilized_percent_switch_3_link_1: 11.6222 bw: 16000 base_latency: 1 |
| links_utilized_percent_switch_3_link_2: 2.53208 bw: 16000 base_latency: 1 |
| |
| outgoing_messages_switch_3_link_0_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 253 18216 [ 0 0 253 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_3_link_0_Writeback_Control: 1354 10832 [ 1354 0 0 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_3_link_1_Request_Control: 1362 10896 [ 1362 0 0 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_3_link_1_Response_Data: 1109 79848 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_3_link_1_Writeback_Data: 1354 97488 [ 0 0 1354 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_3_link_1_Writeback_Control: 2447 19576 [ 1354 1093 0 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_3_link_1_Unblock_Control: 1362 10896 [ 0 0 1362 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_3_link_2_Request_Control: 1109 8872 [ 0 1109 0 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_3_link_2_Writeback_Data: 194 13968 [ 0 0 194 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_3_link_2_Writeback_Control: 1992 15936 [ 0 1093 899 0 0 0 0 0 0 0 ] base_latency: 1 |
| outgoing_messages_switch_3_link_2_Unblock_Control: 1109 8872 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 |
| |
| Cache Stats: system.ruby.l1_cntrl0.L1IcacheMemory |
| system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 0 |
| system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0 |
| system.ruby.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 |
| system.ruby.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 |
| system.ruby.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 |
| |
| |
| Cache Stats: system.ruby.l1_cntrl0.L1DcacheMemory |
| system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 0 |
| system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0 |
| system.ruby.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 |
| system.ruby.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 |
| system.ruby.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 |
| |
| |
| --- L1Cache --- |
| - Event Counts - |
| Load [1183 ] 1183 |
| Ifetch [6400 ] 6400 |
| Store [865 ] 865 |
| L1_Replacement [1379 ] 1379 |
| Own_GETX [0 ] 0 |
| Fwd_GETX [0 ] 0 |
| Fwd_GETS [0 ] 0 |
| Fwd_DMA [0 ] 0 |
| Inv [0 ] 0 |
| Ack [0 ] 0 |
| Data [0 ] 0 |
| Exclusive_Data [1362 ] 1362 |
| Writeback_Ack [0 ] 0 |
| Writeback_Ack_Data [1354 ] 1354 |
| Writeback_Nack [0 ] 0 |
| All_acks [191 ] 191 |
| Use_Timeout [1361 ] 1361 |
| |
| - Transitions - |
| I Load [525 ] 525 |
| I Ifetch [646 ] 646 |
| I Store [191 ] 191 |
| I L1_Replacement [0 ] 0 |
| I Inv [0 ] 0 |
| |
| S Load [0 ] 0 |
| S Ifetch [0 ] 0 |
| S Store [0 ] 0 |
| S L1_Replacement [0 ] 0 |
| S Fwd_GETS [0 ] 0 |
| S Fwd_DMA [0 ] 0 |
| S Inv [0 ] 0 |
| |
| O Load [0 ] 0 |
| O Ifetch [0 ] 0 |
| O Store [0 ] 0 |
| O L1_Replacement [0 ] 0 |
| O Fwd_GETX [0 ] 0 |
| O Fwd_GETS [0 ] 0 |
| O Fwd_DMA [0 ] 0 |
| |
| M Load [305 ] 305 |
| M Ifetch [3467 ] 3467 |
| M Store [51 ] 51 |
| M L1_Replacement [1086 ] 1086 |
| M Fwd_GETX [0 ] 0 |
| M Fwd_GETS [0 ] 0 |
| M Fwd_DMA [0 ] 0 |
| |
| M_W Load [112 ] 112 |
| M_W Ifetch [2287 ] 2287 |
| M_W Store [27 ] 27 |
| M_W L1_Replacement [17 ] 17 |
| M_W Own_GETX [0 ] 0 |
| M_W Fwd_GETX [0 ] 0 |
| M_W Fwd_GETS [0 ] 0 |
| M_W Fwd_DMA [0 ] 0 |
| M_W Inv [0 ] 0 |
| M_W Use_Timeout [1143 ] 1143 |
| |
| MM Load [234 ] 234 |
| MM Ifetch [0 ] 0 |
| MM Store [339 ] 339 |
| MM L1_Replacement [268 ] 268 |
| MM Fwd_GETX [0 ] 0 |
| MM Fwd_GETS [0 ] 0 |
| MM Fwd_DMA [0 ] 0 |
| |
| MM_W Load [7 ] 7 |
| MM_W Ifetch [0 ] 0 |
| MM_W Store [257 ] 257 |
| MM_W L1_Replacement [8 ] 8 |
| MM_W Own_GETX [0 ] 0 |
| MM_W Fwd_GETX [0 ] 0 |
| MM_W Fwd_GETS [0 ] 0 |
| MM_W Fwd_DMA [0 ] 0 |
| MM_W Inv [0 ] 0 |
| MM_W Use_Timeout [218 ] 218 |
| |
| IM Load [0 ] 0 |
| IM Ifetch [0 ] 0 |
| IM Store [0 ] 0 |
| IM L1_Replacement [0 ] 0 |
| IM Inv [0 ] 0 |
| IM Ack [0 ] 0 |
| IM Data [0 ] 0 |
| IM Exclusive_Data [191 ] 191 |
| |
| SM Load [0 ] 0 |
| SM Ifetch [0 ] 0 |
| SM Store [0 ] 0 |
| SM L1_Replacement [0 ] 0 |
| SM Fwd_GETS [0 ] 0 |
| SM Fwd_DMA [0 ] 0 |
| SM Inv [0 ] 0 |
| SM Ack [0 ] 0 |
| SM Data [0 ] 0 |
| SM Exclusive_Data [0 ] 0 |
| |
| OM Load [0 ] 0 |
| OM Ifetch [0 ] 0 |
| OM Store [0 ] 0 |
| OM L1_Replacement [0 ] 0 |
| OM Own_GETX [0 ] 0 |
| OM Fwd_GETX [0 ] 0 |
| OM Fwd_GETS [0 ] 0 |
| OM Fwd_DMA [0 ] 0 |
| OM Ack [0 ] 0 |
| OM All_acks [191 ] 191 |
| |
| IS Load [0 ] 0 |
| IS Ifetch [0 ] 0 |
| IS Store [0 ] 0 |
| IS L1_Replacement [0 ] 0 |
| IS Inv [0 ] 0 |
| IS Data [0 ] 0 |
| IS Exclusive_Data [1171 ] 1171 |
| |
| SI Load [0 ] 0 |
| SI Ifetch [0 ] 0 |
| SI Store [0 ] 0 |
| SI L1_Replacement [0 ] 0 |
| SI Fwd_GETS [0 ] 0 |
| SI Fwd_DMA [0 ] 0 |
| SI Inv [0 ] 0 |
| SI Writeback_Ack [0 ] 0 |
| SI Writeback_Ack_Data [0 ] 0 |
| SI Writeback_Nack [0 ] 0 |
| |
| OI Load [0 ] 0 |
| OI Ifetch [0 ] 0 |
| OI Store [0 ] 0 |
| OI L1_Replacement [0 ] 0 |
| OI Fwd_GETX [0 ] 0 |
| OI Fwd_GETS [0 ] 0 |
| OI Fwd_DMA [0 ] 0 |
| OI Writeback_Ack [0 ] 0 |
| OI Writeback_Ack_Data [0 ] 0 |
| OI Writeback_Nack [0 ] 0 |
| |
| MI Load [0 ] 0 |
| MI Ifetch [0 ] 0 |
| MI Store [0 ] 0 |
| MI L1_Replacement [0 ] 0 |
| MI Fwd_GETX [0 ] 0 |
| MI Fwd_GETS [0 ] 0 |
| MI Fwd_DMA [0 ] 0 |
| MI Writeback_Ack [0 ] 0 |
| MI Writeback_Ack_Data [1354 ] 1354 |
| MI Writeback_Nack [0 ] 0 |
| |
| II Load [0 ] 0 |
| II Ifetch [0 ] 0 |
| II Store [0 ] 0 |
| II L1_Replacement [0 ] 0 |
| II Inv [0 ] 0 |
| II Writeback_Ack [0 ] 0 |
| II Writeback_Ack_Data [0 ] 0 |
| II Writeback_Nack [0 ] 0 |
| |
| Cache Stats: system.ruby.l2_cntrl0.L2cacheMemory |
| system.ruby.l2_cntrl0.L2cacheMemory_total_misses: 0 |
| system.ruby.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 |
| system.ruby.l2_cntrl0.L2cacheMemory_total_prefetches: 0 |
| system.ruby.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 |
| system.ruby.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 |
| |
| |
| --- L2Cache --- |
| - Event Counts - |
| L1_GETS [1171 ] 1171 |
| L1_GETX [191 ] 191 |
| L1_PUTO [0 ] 0 |
| L1_PUTX [1354 ] 1354 |
| L1_PUTS_only [0 ] 0 |
| L1_PUTS [0 ] 0 |
| Fwd_GETX [0 ] 0 |
| Fwd_GETS [0 ] 0 |
| Fwd_DMA [0 ] 0 |
| Own_GETX [0 ] 0 |
| Inv [0 ] 0 |
| IntAck [0 ] 0 |
| ExtAck [0 ] 0 |
| All_Acks [130 ] 130 |
| Data [130 ] 130 |
| Data_Exclusive [979 ] 979 |
| L1_WBCLEANDATA [1058 ] 1058 |
| L1_WBDIRTYDATA [296 ] 296 |
| Writeback_Ack [1093 ] 1093 |
| Writeback_Nack [0 ] 0 |
| Unblock [0 ] 0 |
| Exclusive_Unblock [1362 ] 1362 |
| DmaAck [0 ] 0 |
| L2_Replacement [1093 ] 1093 |
| |
| - Transitions - |
| NP L1_GETS [979 ] 979 |
| NP L1_GETX [130 ] 130 |
| NP L1_PUTO [0 ] 0 |
| NP L1_PUTX [0 ] 0 |
| NP L1_PUTS [0 ] 0 |
| NP Inv [0 ] 0 |
| |
| I L1_GETS [0 ] 0 |
| I L1_GETX [0 ] 0 |
| I L1_PUTO [0 ] 0 |
| I L1_PUTX [0 ] 0 |
| I L1_PUTS [0 ] 0 |
| I Inv [0 ] 0 |
| I L2_Replacement [0 ] 0 |
| |
| ILS L1_GETS [0 ] 0 |
| ILS L1_GETX [0 ] 0 |
| ILS L1_PUTO [0 ] 0 |
| ILS L1_PUTX [0 ] 0 |
| ILS L1_PUTS_only [0 ] 0 |
| ILS L1_PUTS [0 ] 0 |
| ILS Inv [0 ] 0 |
| ILS L2_Replacement [0 ] 0 |
| |
| ILX L1_GETS [0 ] 0 |
| ILX L1_GETX [0 ] 0 |
| ILX L1_PUTO [0 ] 0 |
| ILX L1_PUTX [1354 ] 1354 |
| ILX L1_PUTS_only [0 ] 0 |
| ILX L1_PUTS [0 ] 0 |
| ILX Fwd_GETX [0 ] 0 |
| ILX Fwd_GETS [0 ] 0 |
| ILX Fwd_DMA [0 ] 0 |
| ILX Inv [0 ] 0 |
| ILX Data [0 ] 0 |
| ILX L2_Replacement [0 ] 0 |
| |
| ILO L1_GETS [0 ] 0 |
| ILO L1_GETX [0 ] 0 |
| ILO L1_PUTO [0 ] 0 |
| ILO L1_PUTX [0 ] 0 |
| ILO L1_PUTS [0 ] 0 |
| ILO Fwd_GETX [0 ] 0 |
| ILO Fwd_GETS [0 ] 0 |
| ILO Fwd_DMA [0 ] 0 |
| ILO Inv [0 ] 0 |
| ILO Data [0 ] 0 |
| ILO L2_Replacement [0 ] 0 |
| |
| ILOX L1_GETS [0 ] 0 |
| ILOX L1_GETX [0 ] 0 |
| ILOX L1_PUTO [0 ] 0 |
| ILOX L1_PUTX [0 ] 0 |
| ILOX L1_PUTS [0 ] 0 |
| ILOX Fwd_GETX [0 ] 0 |
| ILOX Fwd_GETS [0 ] 0 |
| ILOX Fwd_DMA [0 ] 0 |
| ILOX Data [0 ] 0 |
| |
| ILOS L1_GETS [0 ] 0 |
| ILOS L1_GETX [0 ] 0 |
| ILOS L1_PUTO [0 ] 0 |
| ILOS L1_PUTX [0 ] 0 |
| ILOS L1_PUTS_only [0 ] 0 |
| ILOS L1_PUTS [0 ] 0 |
| ILOS Fwd_GETX [0 ] 0 |
| ILOS Fwd_GETS [0 ] 0 |
| ILOS Fwd_DMA [0 ] 0 |
| ILOS Data [0 ] 0 |
| ILOS L2_Replacement [0 ] 0 |
| |
| ILOSX L1_GETS [0 ] 0 |
| ILOSX L1_GETX [0 ] 0 |
| ILOSX L1_PUTO [0 ] 0 |
| ILOSX L1_PUTX [0 ] 0 |
| ILOSX L1_PUTS_only [0 ] 0 |
| ILOSX L1_PUTS [0 ] 0 |
| ILOSX Fwd_GETX [0 ] 0 |
| ILOSX Fwd_GETS [0 ] 0 |
| ILOSX Fwd_DMA [0 ] 0 |
| ILOSX Data [0 ] 0 |
| |
| S L1_GETS [0 ] 0 |
| S L1_GETX [0 ] 0 |
| S L1_PUTX [0 ] 0 |
| S L1_PUTS [0 ] 0 |
| S Inv [0 ] 0 |
| S L2_Replacement [0 ] 0 |
| |
| O L1_GETS [0 ] 0 |
| O L1_GETX [0 ] 0 |
| O L1_PUTX [0 ] 0 |
| O Fwd_GETX [0 ] 0 |
| O Fwd_GETS [0 ] 0 |
| O Fwd_DMA [0 ] 0 |
| O L2_Replacement [0 ] 0 |
| |
| OLS L1_GETS [0 ] 0 |
| OLS L1_GETX [0 ] 0 |
| OLS L1_PUTX [0 ] 0 |
| OLS L1_PUTS_only [0 ] 0 |
| OLS L1_PUTS [0 ] 0 |
| OLS Fwd_GETX [0 ] 0 |
| OLS Fwd_GETS [0 ] 0 |
| OLS Fwd_DMA [0 ] 0 |
| OLS L2_Replacement [0 ] 0 |
| |
| OLSX L1_GETS [0 ] 0 |
| OLSX L1_GETX [0 ] 0 |
| OLSX L1_PUTO [0 ] 0 |
| OLSX L1_PUTX [0 ] 0 |
| OLSX L1_PUTS_only [0 ] 0 |
| OLSX L1_PUTS [0 ] 0 |
| OLSX Fwd_GETX [0 ] 0 |
| OLSX Fwd_GETS [0 ] 0 |
| OLSX Fwd_DMA [0 ] 0 |
| OLSX L2_Replacement [0 ] 0 |
| |
| SLS L1_GETS [0 ] 0 |
| SLS L1_GETX [0 ] 0 |
| SLS L1_PUTX [0 ] 0 |
| SLS L1_PUTS_only [0 ] 0 |
| SLS L1_PUTS [0 ] 0 |
| SLS Inv [0 ] 0 |
| SLS L2_Replacement [0 ] 0 |
| |
| M L1_GETS [192 ] 192 |
| M L1_GETX [61 ] 61 |
| M L1_PUTO [0 ] 0 |
| M L1_PUTX [0 ] 0 |
| M L1_PUTS [0 ] 0 |
| M Fwd_GETX [0 ] 0 |
| M Fwd_GETS [0 ] 0 |
| M Fwd_DMA [0 ] 0 |
| M L2_Replacement [1093 ] 1093 |
| |
| IFGX L1_GETS [0 ] 0 |
| IFGX L1_GETX [0 ] 0 |
| IFGX L1_PUTO [0 ] 0 |
| IFGX L1_PUTX [0 ] 0 |
| IFGX L1_PUTS_only [0 ] 0 |
| IFGX L1_PUTS [0 ] 0 |
| IFGX Fwd_GETX [0 ] 0 |
| IFGX Fwd_GETS [0 ] 0 |
| IFGX Fwd_DMA [0 ] 0 |
| IFGX Inv [0 ] 0 |
| IFGX Data [0 ] 0 |
| IFGX Data_Exclusive [0 ] 0 |
| IFGX L2_Replacement [0 ] 0 |
| |
| IFGS L1_GETS [0 ] 0 |
| IFGS L1_GETX [0 ] 0 |
| IFGS L1_PUTO [0 ] 0 |
| IFGS L1_PUTX [0 ] 0 |
| IFGS L1_PUTS_only [0 ] 0 |
| IFGS L1_PUTS [0 ] 0 |
| IFGS Fwd_GETX [0 ] 0 |
| IFGS Fwd_GETS [0 ] 0 |
| IFGS Fwd_DMA [0 ] 0 |
| IFGS Inv [0 ] 0 |
| IFGS Data [0 ] 0 |
| IFGS Data_Exclusive [0 ] 0 |
| IFGS L2_Replacement [0 ] 0 |
| |
| ISFGS L1_GETS [0 ] 0 |
| ISFGS L1_GETX [0 ] 0 |
| ISFGS L1_PUTO [0 ] 0 |
| ISFGS L1_PUTX [0 ] 0 |
| ISFGS L1_PUTS_only [0 ] 0 |
| ISFGS L1_PUTS [0 ] 0 |
| ISFGS Fwd_GETX [0 ] 0 |
| ISFGS Fwd_GETS [0 ] 0 |
| ISFGS Fwd_DMA [0 ] 0 |
| ISFGS Inv [0 ] 0 |
| ISFGS Data [0 ] 0 |
| ISFGS L2_Replacement [0 ] 0 |
| |
| IFGXX L1_GETS [0 ] 0 |
| IFGXX L1_GETX [0 ] 0 |
| IFGXX L1_PUTO [0 ] 0 |
| IFGXX L1_PUTX [0 ] 0 |
| IFGXX L1_PUTS_only [0 ] 0 |
| IFGXX L1_PUTS [0 ] 0 |
| IFGXX Fwd_GETX [0 ] 0 |
| IFGXX Fwd_GETS [0 ] 0 |
| IFGXX Fwd_DMA [0 ] 0 |
| IFGXX Inv [0 ] 0 |
| IFGXX IntAck [0 ] 0 |
| IFGXX All_Acks [0 ] 0 |
| IFGXX Data_Exclusive [0 ] 0 |
| IFGXX L2_Replacement [0 ] 0 |
| |
| OFGX L1_GETS [0 ] 0 |
| OFGX L1_GETX [0 ] 0 |
| OFGX L1_PUTO [0 ] 0 |
| OFGX L1_PUTX [0 ] 0 |
| OFGX L1_PUTS_only [0 ] 0 |
| OFGX L1_PUTS [0 ] 0 |
| OFGX Fwd_GETX [0 ] 0 |
| OFGX Fwd_GETS [0 ] 0 |
| OFGX Fwd_DMA [0 ] 0 |
| OFGX Inv [0 ] 0 |
| OFGX L2_Replacement [0 ] 0 |
| |
| OLSF L1_GETS [0 ] 0 |
| OLSF L1_GETX [0 ] 0 |
| OLSF L1_PUTO [0 ] 0 |
| OLSF L1_PUTX [0 ] 0 |
| OLSF L1_PUTS_only [0 ] 0 |
| OLSF L1_PUTS [0 ] 0 |
| OLSF Fwd_GETX [0 ] 0 |
| OLSF Fwd_GETS [0 ] 0 |
| OLSF Fwd_DMA [0 ] 0 |
| OLSF Inv [0 ] 0 |
| OLSF IntAck [0 ] 0 |
| OLSF All_Acks [0 ] 0 |
| OLSF L2_Replacement [0 ] 0 |
| |
| ILOW L1_GETS [0 ] 0 |
| ILOW L1_GETX [0 ] 0 |
| ILOW L1_PUTO [0 ] 0 |
| ILOW L1_PUTX [0 ] 0 |
| ILOW L1_PUTS_only [0 ] 0 |
| ILOW L1_PUTS [0 ] 0 |
| ILOW Fwd_GETX [0 ] 0 |
| ILOW Fwd_GETS [0 ] 0 |
| ILOW Fwd_DMA [0 ] 0 |
| ILOW Inv [0 ] 0 |
| ILOW L1_WBCLEANDATA [0 ] 0 |
| ILOW L1_WBDIRTYDATA [0 ] 0 |
| ILOW Unblock [0 ] 0 |
| ILOW L2_Replacement [0 ] 0 |
| |
| ILOXW L1_GETS [0 ] 0 |
| ILOXW L1_GETX [0 ] 0 |
| ILOXW L1_PUTO [0 ] 0 |
| ILOXW L1_PUTX [0 ] 0 |
| ILOXW L1_PUTS_only [0 ] 0 |
| ILOXW L1_PUTS [0 ] 0 |
| ILOXW Fwd_GETX [0 ] 0 |
| ILOXW Fwd_GETS [0 ] 0 |
| ILOXW Fwd_DMA [0 ] 0 |
| ILOXW Inv [0 ] 0 |
| ILOXW L1_WBCLEANDATA [0 ] 0 |
| ILOXW L1_WBDIRTYDATA [0 ] 0 |
| ILOXW Unblock [0 ] 0 |
| ILOXW L2_Replacement [0 ] 0 |
| |
| ILOSW L1_GETS [0 ] 0 |
| ILOSW L1_GETX [0 ] 0 |
| ILOSW L1_PUTO [0 ] 0 |
| ILOSW L1_PUTX [0 ] 0 |
| ILOSW L1_PUTS_only [0 ] 0 |
| ILOSW L1_PUTS [0 ] 0 |
| ILOSW Fwd_GETX [0 ] 0 |
| ILOSW Fwd_GETS [0 ] 0 |
| ILOSW Fwd_DMA [0 ] 0 |
| ILOSW Inv [0 ] 0 |
| ILOSW L1_WBCLEANDATA [0 ] 0 |
| ILOSW L1_WBDIRTYDATA [0 ] 0 |
| ILOSW Unblock [0 ] 0 |
| ILOSW L2_Replacement [0 ] 0 |
| |
| ILOSXW L1_GETS [0 ] 0 |
| ILOSXW L1_GETX [0 ] 0 |
| ILOSXW L1_PUTO [0 ] 0 |
| ILOSXW L1_PUTX [0 ] 0 |
| ILOSXW L1_PUTS_only [0 ] 0 |
| ILOSXW L1_PUTS [0 ] 0 |
| ILOSXW Fwd_GETX [0 ] 0 |
| ILOSXW Fwd_GETS [0 ] 0 |
| ILOSXW Fwd_DMA [0 ] 0 |
| ILOSXW Inv [0 ] 0 |
| ILOSXW L1_WBCLEANDATA [0 ] 0 |
| ILOSXW L1_WBDIRTYDATA [0 ] 0 |
| ILOSXW Unblock [0 ] 0 |
| ILOSXW L2_Replacement [0 ] 0 |
| |
| SLSW L1_GETS [0 ] 0 |
| SLSW L1_GETX [0 ] 0 |
| SLSW L1_PUTO [0 ] 0 |
| SLSW L1_PUTX [0 ] 0 |
| SLSW L1_PUTS_only [0 ] 0 |
| SLSW L1_PUTS [0 ] 0 |
| SLSW Fwd_GETX [0 ] 0 |
| SLSW Fwd_GETS [0 ] 0 |
| SLSW Fwd_DMA [0 ] 0 |
| SLSW Inv [0 ] 0 |
| SLSW Unblock [0 ] 0 |
| SLSW L2_Replacement [0 ] 0 |
| |
| OLSW L1_GETS [0 ] 0 |
| OLSW L1_GETX [0 ] 0 |
| OLSW L1_PUTO [0 ] 0 |
| OLSW L1_PUTX [0 ] 0 |
| OLSW L1_PUTS_only [0 ] 0 |
| OLSW L1_PUTS [0 ] 0 |
| OLSW Fwd_GETX [0 ] 0 |
| OLSW Fwd_GETS [0 ] 0 |
| OLSW Fwd_DMA [0 ] 0 |
| OLSW Inv [0 ] 0 |
| OLSW Unblock [0 ] 0 |
| OLSW L2_Replacement [0 ] 0 |
| |
| ILSW L1_GETS [0 ] 0 |
| ILSW L1_GETX [0 ] 0 |
| ILSW L1_PUTO [0 ] 0 |
| ILSW L1_PUTX [0 ] 0 |
| ILSW L1_PUTS_only [0 ] 0 |
| ILSW L1_PUTS [0 ] 0 |
| ILSW Fwd_GETX [0 ] 0 |
| ILSW Fwd_GETS [0 ] 0 |
| ILSW Fwd_DMA [0 ] 0 |
| ILSW Inv [0 ] 0 |
| ILSW L1_WBCLEANDATA [0 ] 0 |
| ILSW Unblock [0 ] 0 |
| ILSW L2_Replacement [0 ] 0 |
| |
| IW L1_GETS [0 ] 0 |
| IW L1_GETX [0 ] 0 |
| IW L1_PUTO [0 ] 0 |
| IW L1_PUTX [0 ] 0 |
| IW L1_PUTS_only [0 ] 0 |
| IW L1_PUTS [0 ] 0 |
| IW Fwd_GETX [0 ] 0 |
| IW Fwd_GETS [0 ] 0 |
| IW Fwd_DMA [0 ] 0 |
| IW Inv [0 ] 0 |
| IW L1_WBCLEANDATA [0 ] 0 |
| IW L2_Replacement [0 ] 0 |
| |
| OW L1_GETS [0 ] 0 |
| OW L1_GETX [0 ] 0 |
| OW L1_PUTO [0 ] 0 |
| OW L1_PUTX [0 ] 0 |
| OW L1_PUTS_only [0 ] 0 |
| OW L1_PUTS [0 ] 0 |
| OW Fwd_GETX [0 ] 0 |
| OW Fwd_GETS [0 ] 0 |
| OW Fwd_DMA [0 ] 0 |
| OW Inv [0 ] 0 |
| OW Unblock [0 ] 0 |
| OW L2_Replacement [0 ] 0 |
| |
| SW L1_GETS [0 ] 0 |
| SW L1_GETX [0 ] 0 |
| SW L1_PUTO [0 ] 0 |
| SW L1_PUTX [0 ] 0 |
| SW L1_PUTS_only [0 ] 0 |
| SW L1_PUTS [0 ] 0 |
| SW Fwd_GETX [0 ] 0 |
| SW Fwd_GETS [0 ] 0 |
| SW Fwd_DMA [0 ] 0 |
| SW Inv [0 ] 0 |
| SW Unblock [0 ] 0 |
| SW L2_Replacement [0 ] 0 |
| |
| OXW L1_GETS [0 ] 0 |
| OXW L1_GETX [0 ] 0 |
| OXW L1_PUTO [0 ] 0 |
| OXW L1_PUTX [0 ] 0 |
| OXW L1_PUTS_only [0 ] 0 |
| OXW L1_PUTS [0 ] 0 |
| OXW Fwd_GETX [0 ] 0 |
| OXW Fwd_GETS [0 ] 0 |
| OXW Fwd_DMA [0 ] 0 |
| OXW Inv [0 ] 0 |
| OXW Unblock [0 ] 0 |
| OXW L2_Replacement [0 ] 0 |
| |
| OLSXW L1_GETS [0 ] 0 |
| OLSXW L1_GETX [0 ] 0 |
| OLSXW L1_PUTO [0 ] 0 |
| OLSXW L1_PUTX [0 ] 0 |
| OLSXW L1_PUTS_only [0 ] 0 |
| OLSXW L1_PUTS [0 ] 0 |
| OLSXW Fwd_GETX [0 ] 0 |
| OLSXW Fwd_GETS [0 ] 0 |
| OLSXW Fwd_DMA [0 ] 0 |
| OLSXW Inv [0 ] 0 |
| OLSXW Unblock [0 ] 0 |
| OLSXW L2_Replacement [0 ] 0 |
| |
| ILXW L1_GETS [0 ] 0 |
| ILXW L1_GETX [0 ] 0 |
| ILXW L1_PUTO [0 ] 0 |
| ILXW L1_PUTX [0 ] 0 |
| ILXW L1_PUTS_only [0 ] 0 |
| ILXW L1_PUTS [0 ] 0 |
| ILXW Fwd_GETX [0 ] 0 |
| ILXW Fwd_GETS [0 ] 0 |
| ILXW Fwd_DMA [0 ] 0 |
| ILXW Inv [0 ] 0 |
| ILXW Data [0 ] 0 |
| ILXW L1_WBCLEANDATA [1058 ] 1058 |
| ILXW L1_WBDIRTYDATA [296 ] 296 |
| ILXW Unblock [0 ] 0 |
| ILXW L2_Replacement [0 ] 0 |
| |
| IFLS L1_GETS [0 ] 0 |
| IFLS L1_GETX [0 ] 0 |
| IFLS L1_PUTO [0 ] 0 |
| IFLS L1_PUTX [0 ] 0 |
| IFLS L1_PUTS_only [0 ] 0 |
| IFLS L1_PUTS [0 ] 0 |
| IFLS Fwd_GETX [0 ] 0 |
| IFLS Fwd_GETS [0 ] 0 |
| IFLS Fwd_DMA [0 ] 0 |
| IFLS Inv [0 ] 0 |
| IFLS Unblock [0 ] 0 |
| IFLS L2_Replacement [0 ] 0 |
| |
| IFLO L1_GETS [0 ] 0 |
| IFLO L1_GETX [0 ] 0 |
| IFLO L1_PUTO [0 ] 0 |
| IFLO L1_PUTX [0 ] 0 |
| IFLO L1_PUTS_only [0 ] 0 |
| IFLO L1_PUTS [0 ] 0 |
| IFLO Fwd_GETX [0 ] 0 |
| IFLO Fwd_GETS [0 ] 0 |
| IFLO Fwd_DMA [0 ] 0 |
| IFLO Inv [0 ] 0 |
| IFLO Unblock [0 ] 0 |
| IFLO L2_Replacement [0 ] 0 |
| |
| IFLOX L1_GETS [0 ] 0 |
| IFLOX L1_GETX [0 ] 0 |
| IFLOX L1_PUTO [0 ] 0 |
| IFLOX L1_PUTX [0 ] 0 |
| IFLOX L1_PUTS_only [0 ] 0 |
| IFLOX L1_PUTS [0 ] 0 |
| IFLOX Fwd_GETX [0 ] 0 |
| IFLOX Fwd_GETS [0 ] 0 |
| IFLOX Fwd_DMA [0 ] 0 |
| IFLOX Inv [0 ] 0 |
| IFLOX Unblock [0 ] 0 |
| IFLOX Exclusive_Unblock [0 ] 0 |
| IFLOX L2_Replacement [0 ] 0 |
| |
| IFLOXX L1_GETS [0 ] 0 |
| IFLOXX L1_GETX [0 ] 0 |
| IFLOXX L1_PUTO [0 ] 0 |
| IFLOXX L1_PUTX [0 ] 0 |
| IFLOXX L1_PUTS_only [0 ] 0 |
| IFLOXX L1_PUTS [0 ] 0 |
| IFLOXX Fwd_GETX [0 ] 0 |
| IFLOXX Fwd_GETS [0 ] 0 |
| IFLOXX Fwd_DMA [0 ] 0 |
| IFLOXX Inv [0 ] 0 |
| IFLOXX Unblock [0 ] 0 |
| IFLOXX Exclusive_Unblock [0 ] 0 |
| IFLOXX L2_Replacement [0 ] 0 |
| |
| IFLOSX L1_GETS [0 ] 0 |
| IFLOSX L1_GETX [0 ] 0 |
| IFLOSX L1_PUTO [0 ] 0 |
| IFLOSX L1_PUTX [0 ] 0 |
| IFLOSX L1_PUTS_only [0 ] 0 |
| IFLOSX L1_PUTS [0 ] 0 |
| IFLOSX Fwd_GETX [0 ] 0 |
| IFLOSX Fwd_GETS [0 ] 0 |
| IFLOSX Fwd_DMA [0 ] 0 |
| IFLOSX Inv [0 ] 0 |
| IFLOSX Unblock [0 ] 0 |
| IFLOSX Exclusive_Unblock [0 ] 0 |
| IFLOSX L2_Replacement [0 ] 0 |
| |
| IFLXO L1_GETS [0 ] 0 |
| IFLXO L1_GETX [0 ] 0 |
| IFLXO L1_PUTO [0 ] 0 |
| IFLXO L1_PUTX [0 ] 0 |
| IFLXO L1_PUTS_only [0 ] 0 |
| IFLXO L1_PUTS [0 ] 0 |
| IFLXO Fwd_GETX [0 ] 0 |
| IFLXO Fwd_GETS [0 ] 0 |
| IFLXO Fwd_DMA [0 ] 0 |
| IFLXO Inv [0 ] 0 |
| IFLXO Exclusive_Unblock [0 ] 0 |
| IFLXO L2_Replacement [0 ] 0 |
| |
| IGS L1_GETS [0 ] 0 |
| IGS L1_GETX [0 ] 0 |
| IGS L1_PUTO [0 ] 0 |
| IGS L1_PUTX [0 ] 0 |
| IGS L1_PUTS_only [0 ] 0 |
| IGS L1_PUTS [0 ] 0 |
| IGS Fwd_GETX [0 ] 0 |
| IGS Fwd_GETS [0 ] 0 |
| IGS Fwd_DMA [0 ] 0 |
| IGS Own_GETX [0 ] 0 |
| IGS Inv [0 ] 0 |
| IGS Data [0 ] 0 |
| IGS Data_Exclusive [979 ] 979 |
| IGS Unblock [0 ] 0 |
| IGS Exclusive_Unblock [979 ] 979 |
| IGS L2_Replacement [0 ] 0 |
| |
| IGM L1_GETS [0 ] 0 |
| IGM L1_GETX [0 ] 0 |
| IGM L1_PUTO [0 ] 0 |
| IGM L1_PUTX [0 ] 0 |
| IGM L1_PUTS_only [0 ] 0 |
| IGM L1_PUTS [0 ] 0 |
| IGM Fwd_GETX [0 ] 0 |
| IGM Fwd_GETS [0 ] 0 |
| IGM Fwd_DMA [0 ] 0 |
| IGM Own_GETX [0 ] 0 |
| IGM Inv [0 ] 0 |
| IGM ExtAck [0 ] 0 |
| IGM Data [130 ] 130 |
| IGM Data_Exclusive [0 ] 0 |
| IGM L2_Replacement [0 ] 0 |
| |
| IGMLS L1_GETS [0 ] 0 |
| IGMLS L1_GETX [0 ] 0 |
| IGMLS L1_PUTO [0 ] 0 |
| IGMLS L1_PUTX [0 ] 0 |
| IGMLS L1_PUTS_only [0 ] 0 |
| IGMLS L1_PUTS [0 ] 0 |
| IGMLS Inv [0 ] 0 |
| IGMLS IntAck [0 ] 0 |
| IGMLS ExtAck [0 ] 0 |
| IGMLS All_Acks [0 ] 0 |
| IGMLS Data [0 ] 0 |
| IGMLS Data_Exclusive [0 ] 0 |
| IGMLS L2_Replacement [0 ] 0 |
| |
| IGMO L1_GETS [0 ] 0 |
| IGMO L1_GETX [0 ] 0 |
| IGMO L1_PUTO [0 ] 0 |
| IGMO L1_PUTX [0 ] 0 |
| IGMO L1_PUTS_only [0 ] 0 |
| IGMO L1_PUTS [0 ] 0 |
| IGMO Fwd_GETX [0 ] 0 |
| IGMO Fwd_GETS [0 ] 0 |
| IGMO Fwd_DMA [0 ] 0 |
| IGMO Own_GETX [0 ] 0 |
| IGMO ExtAck [0 ] 0 |
| IGMO All_Acks [130 ] 130 |
| IGMO Exclusive_Unblock [130 ] 130 |
| IGMO L2_Replacement [0 ] 0 |
| |
| IGMIO L1_GETS [0 ] 0 |
| IGMIO L1_GETX [0 ] 0 |
| IGMIO L1_PUTO [0 ] 0 |
| IGMIO L1_PUTX [0 ] 0 |
| IGMIO L1_PUTS_only [0 ] 0 |
| IGMIO L1_PUTS [0 ] 0 |
| IGMIO Fwd_GETX [0 ] 0 |
| IGMIO Fwd_GETS [0 ] 0 |
| IGMIO Fwd_DMA [0 ] 0 |
| IGMIO Own_GETX [0 ] 0 |
| IGMIO ExtAck [0 ] 0 |
| IGMIO All_Acks [0 ] 0 |
| |
| OGMIO L1_GETS [0 ] 0 |
| OGMIO L1_GETX [0 ] 0 |
| OGMIO L1_PUTO [0 ] 0 |
| OGMIO L1_PUTX [0 ] 0 |
| OGMIO L1_PUTS_only [0 ] 0 |
| OGMIO L1_PUTS [0 ] 0 |
| OGMIO Fwd_GETX [0 ] 0 |
| OGMIO Fwd_GETS [0 ] 0 |
| OGMIO Fwd_DMA [0 ] 0 |
| OGMIO Own_GETX [0 ] 0 |
| OGMIO ExtAck [0 ] 0 |
| OGMIO All_Acks [0 ] 0 |
| |
| IGMIOF L1_GETS [0 ] 0 |
| IGMIOF L1_GETX [0 ] 0 |
| IGMIOF L1_PUTO [0 ] 0 |
| IGMIOF L1_PUTX [0 ] 0 |
| IGMIOF L1_PUTS_only [0 ] 0 |
| IGMIOF L1_PUTS [0 ] 0 |
| IGMIOF IntAck [0 ] 0 |
| IGMIOF All_Acks [0 ] 0 |
| IGMIOF Data_Exclusive [0 ] 0 |
| |
| IGMIOFS L1_GETS [0 ] 0 |
| IGMIOFS L1_GETX [0 ] 0 |
| IGMIOFS L1_PUTO [0 ] 0 |
| IGMIOFS L1_PUTX [0 ] 0 |
| IGMIOFS L1_PUTS_only [0 ] 0 |
| IGMIOFS L1_PUTS [0 ] 0 |
| IGMIOFS Fwd_GETX [0 ] 0 |
| IGMIOFS Fwd_GETS [0 ] 0 |
| IGMIOFS Fwd_DMA [0 ] 0 |
| IGMIOFS Inv [0 ] 0 |
| IGMIOFS Data [0 ] 0 |
| IGMIOFS L2_Replacement [0 ] 0 |
| |
| OGMIOF L1_GETS [0 ] 0 |
| OGMIOF L1_GETX [0 ] 0 |
| OGMIOF L1_PUTO [0 ] 0 |
| OGMIOF L1_PUTX [0 ] 0 |
| OGMIOF L1_PUTS_only [0 ] 0 |
| OGMIOF L1_PUTS [0 ] 0 |
| OGMIOF IntAck [0 ] 0 |
| OGMIOF All_Acks [0 ] 0 |
| |
| II L1_GETS [0 ] 0 |
| II L1_GETX [0 ] 0 |
| II L1_PUTO [0 ] 0 |
| II L1_PUTX [0 ] 0 |
| II L1_PUTS_only [0 ] 0 |
| II L1_PUTS [0 ] 0 |
| II IntAck [0 ] 0 |
| II All_Acks [0 ] 0 |
| |
| MM L1_GETS [0 ] 0 |
| MM L1_GETX [0 ] 0 |
| MM L1_PUTO [0 ] 0 |
| MM L1_PUTX [0 ] 0 |
| MM L1_PUTS_only [0 ] 0 |
| MM L1_PUTS [0 ] 0 |
| MM Fwd_GETX [0 ] 0 |
| MM Fwd_GETS [0 ] 0 |
| MM Fwd_DMA [0 ] 0 |
| MM Inv [0 ] 0 |
| MM Exclusive_Unblock [61 ] 61 |
| MM L2_Replacement [0 ] 0 |
| |
| SS L1_GETS [0 ] 0 |
| SS L1_GETX [0 ] 0 |
| SS L1_PUTO [0 ] 0 |
| SS L1_PUTX [0 ] 0 |
| SS L1_PUTS_only [0 ] 0 |
| SS L1_PUTS [0 ] 0 |
| SS Fwd_GETX [0 ] 0 |
| SS Fwd_GETS [0 ] 0 |
| SS Fwd_DMA [0 ] 0 |
| SS Inv [0 ] 0 |
| SS Unblock [0 ] 0 |
| SS L2_Replacement [0 ] 0 |
| |
| OO L1_GETS [0 ] 0 |
| OO L1_GETX [0 ] 0 |
| OO L1_PUTO [0 ] 0 |
| OO L1_PUTX [0 ] 0 |
| OO L1_PUTS_only [0 ] 0 |
| OO L1_PUTS [0 ] 0 |
| OO Fwd_GETX [0 ] 0 |
| OO Fwd_GETS [0 ] 0 |
| OO Fwd_DMA [0 ] 0 |
| OO Inv [0 ] 0 |
| OO Unblock [0 ] 0 |
| OO Exclusive_Unblock [192 ] 192 |
| OO L2_Replacement [0 ] 0 |
| |
| OLSS L1_GETS [0 ] 0 |
| OLSS L1_GETX [0 ] 0 |
| OLSS L1_PUTO [0 ] 0 |
| OLSS L1_PUTX [0 ] 0 |
| OLSS L1_PUTS_only [0 ] 0 |
| OLSS L1_PUTS [0 ] 0 |
| OLSS Fwd_GETX [0 ] 0 |
| OLSS Fwd_GETS [0 ] 0 |
| OLSS Fwd_DMA [0 ] 0 |
| OLSS Inv [0 ] 0 |
| OLSS Unblock [0 ] 0 |
| OLSS L2_Replacement [0 ] 0 |
| |
| OLSXS L1_GETS [0 ] 0 |
| OLSXS L1_GETX [0 ] 0 |
| OLSXS L1_PUTO [0 ] 0 |
| OLSXS L1_PUTX [0 ] 0 |
| OLSXS L1_PUTS_only [0 ] 0 |
| OLSXS L1_PUTS [0 ] 0 |
| OLSXS Fwd_GETX [0 ] 0 |
| OLSXS Fwd_GETS [0 ] 0 |
| OLSXS Fwd_DMA [0 ] 0 |
| OLSXS Inv [0 ] 0 |
| OLSXS Unblock [0 ] 0 |
| OLSXS L2_Replacement [0 ] 0 |
| |
| SLSS L1_GETS [0 ] 0 |
| SLSS L1_GETX [0 ] 0 |
| SLSS L1_PUTO [0 ] 0 |
| SLSS L1_PUTX [0 ] 0 |
| SLSS L1_PUTS_only [0 ] 0 |
| SLSS L1_PUTS [0 ] 0 |
| SLSS Fwd_GETX [0 ] 0 |
| SLSS Fwd_GETS [0 ] 0 |
| SLSS Fwd_DMA [0 ] 0 |
| SLSS Inv [0 ] 0 |
| SLSS Unblock [0 ] 0 |
| SLSS L2_Replacement [0 ] 0 |
| |
| OI L1_GETS [0 ] 0 |
| OI L1_GETX [0 ] 0 |
| OI L1_PUTO [0 ] 0 |
| OI L1_PUTX [0 ] 0 |
| OI L1_PUTS_only [0 ] 0 |
| OI L1_PUTS [0 ] 0 |
| OI Fwd_GETX [0 ] 0 |
| OI Fwd_GETS [0 ] 0 |
| OI Fwd_DMA [0 ] 0 |
| OI Writeback_Ack [0 ] 0 |
| OI Writeback_Nack [0 ] 0 |
| OI L2_Replacement [0 ] 0 |
| |
| MI L1_GETS [0 ] 0 |
| MI L1_GETX [0 ] 0 |
| MI L1_PUTO [0 ] 0 |
| MI L1_PUTX [0 ] 0 |
| MI L1_PUTS_only [0 ] 0 |
| MI L1_PUTS [0 ] 0 |
| MI Fwd_GETX [0 ] 0 |
| MI Fwd_GETS [0 ] 0 |
| MI Fwd_DMA [0 ] 0 |
| MI Writeback_Ack [1093 ] 1093 |
| MI L2_Replacement [0 ] 0 |
| |
| MII L1_GETS [0 ] 0 |
| MII L1_GETX [0 ] 0 |
| MII L1_PUTO [0 ] 0 |
| MII L1_PUTX [0 ] 0 |
| MII L1_PUTS_only [0 ] 0 |
| MII L1_PUTS [0 ] 0 |
| MII Writeback_Ack [0 ] 0 |
| MII Writeback_Nack [0 ] 0 |
| MII L2_Replacement [0 ] 0 |
| |
| OLSI L1_GETS [0 ] 0 |
| OLSI L1_GETX [0 ] 0 |
| OLSI L1_PUTO [0 ] 0 |
| OLSI L1_PUTX [0 ] 0 |
| OLSI L1_PUTS_only [0 ] 0 |
| OLSI L1_PUTS [0 ] 0 |
| OLSI Fwd_GETX [0 ] 0 |
| OLSI Fwd_GETS [0 ] 0 |
| OLSI Fwd_DMA [0 ] 0 |
| OLSI Writeback_Ack [0 ] 0 |
| OLSI L2_Replacement [0 ] 0 |
| |
| ILSI L1_GETS [0 ] 0 |
| ILSI L1_GETX [0 ] 0 |
| ILSI L1_PUTO [0 ] 0 |
| ILSI L1_PUTX [0 ] 0 |
| ILSI L1_PUTS_only [0 ] 0 |
| ILSI L1_PUTS [0 ] 0 |
| ILSI IntAck [0 ] 0 |
| ILSI All_Acks [0 ] 0 |
| ILSI Writeback_Ack [0 ] 0 |
| ILSI L2_Replacement [0 ] 0 |
| |
| ILOSD L1_GETS [0 ] 0 |
| ILOSD L1_GETX [0 ] 0 |
| ILOSD L1_PUTO [0 ] 0 |
| ILOSD L1_PUTX [0 ] 0 |
| ILOSD L1_PUTS_only [0 ] 0 |
| ILOSD L1_PUTS [0 ] 0 |
| ILOSD Fwd_GETX [0 ] 0 |
| ILOSD Fwd_GETS [0 ] 0 |
| ILOSD Fwd_DMA [0 ] 0 |
| ILOSD Own_GETX [0 ] 0 |
| ILOSD Inv [0 ] 0 |
| ILOSD DmaAck [0 ] 0 |
| ILOSD L2_Replacement [0 ] 0 |
| |
| ILOSXD L1_GETS [0 ] 0 |
| ILOSXD L1_GETX [0 ] 0 |
| ILOSXD L1_PUTO [0 ] 0 |
| ILOSXD L1_PUTX [0 ] 0 |
| ILOSXD L1_PUTS_only [0 ] 0 |
| ILOSXD L1_PUTS [0 ] 0 |
| ILOSXD Fwd_GETX [0 ] 0 |
| ILOSXD Fwd_GETS [0 ] 0 |
| ILOSXD Fwd_DMA [0 ] 0 |
| ILOSXD Own_GETX [0 ] 0 |
| ILOSXD Inv [0 ] 0 |
| ILOSXD DmaAck [0 ] 0 |
| ILOSXD L2_Replacement [0 ] 0 |
| |
| ILOD L1_GETS [0 ] 0 |
| ILOD L1_GETX [0 ] 0 |
| ILOD L1_PUTO [0 ] 0 |
| ILOD L1_PUTX [0 ] 0 |
| ILOD L1_PUTS_only [0 ] 0 |
| ILOD L1_PUTS [0 ] 0 |
| ILOD Fwd_GETX [0 ] 0 |
| ILOD Fwd_GETS [0 ] 0 |
| ILOD Fwd_DMA [0 ] 0 |
| ILOD Own_GETX [0 ] 0 |
| ILOD Inv [0 ] 0 |
| ILOD DmaAck [0 ] 0 |
| ILOD L2_Replacement [0 ] 0 |
| |
| ILXD L1_GETS [0 ] 0 |
| ILXD L1_GETX [0 ] 0 |
| ILXD L1_PUTO [0 ] 0 |
| ILXD L1_PUTX [0 ] 0 |
| ILXD L1_PUTS_only [0 ] 0 |
| ILXD L1_PUTS [0 ] 0 |
| ILXD Fwd_GETX [0 ] 0 |
| ILXD Fwd_GETS [0 ] 0 |
| ILXD Fwd_DMA [0 ] 0 |
| ILXD Own_GETX [0 ] 0 |
| ILXD Inv [0 ] 0 |
| ILXD DmaAck [0 ] 0 |
| ILXD L2_Replacement [0 ] 0 |
| |
| ILOXD L1_GETS [0 ] 0 |
| ILOXD L1_GETX [0 ] 0 |
| ILOXD L1_PUTO [0 ] 0 |
| ILOXD L1_PUTX [0 ] 0 |
| ILOXD L1_PUTS_only [0 ] 0 |
| ILOXD L1_PUTS [0 ] 0 |
| ILOXD Fwd_GETX [0 ] 0 |
| ILOXD Fwd_GETS [0 ] 0 |
| ILOXD Fwd_DMA [0 ] 0 |
| ILOXD Own_GETX [0 ] 0 |
| ILOXD Inv [0 ] 0 |
| ILOXD DmaAck [0 ] 0 |
| ILOXD L2_Replacement [0 ] 0 |
| |
| Memory controller: system.ruby.dir_cntrl0.memBuffer: |
| memory_total_requests: 1303 |
| memory_reads: 1109 |
| memory_writes: 194 |
| memory_refreshes: 817 |
| memory_total_request_delays: 115 |
| memory_delays_per_request: 0.0882579 |
| memory_delays_in_input_queue: 0 |
| memory_delays_behind_head_of_bank_queue: 0 |
| memory_delays_stalled_at_head_of_bank_queue: 115 |
| memory_stalls_for_bank_busy: 40 |
| memory_stalls_for_random_busy: 0 |
| memory_stalls_for_anti_starvation: 0 |
| memory_stalls_for_arbitration: 17 |
| memory_stalls_for_bus: 55 |
| memory_stalls_for_tfaw: 0 |
| memory_stalls_for_read_write_turnaround: 3 |
| memory_stalls_for_read_read_turnaround: 0 |
| accesses_per_bank: 74 17 45 40 54 99 29 16 19 22 31 34 52 48 38 30 39 21 21 27 28 37 55 22 31 21 32 69 84 103 13 52 |
| |
| --- Directory --- |
| - Event Counts - |
| GETX [130 ] 130 |
| GETS [979 ] 979 |
| PUTX [1093 ] 1093 |
| PUTO [0 ] 0 |
| PUTO_SHARERS [0 ] 0 |
| Unblock [0 ] 0 |
| Last_Unblock [0 ] 0 |
| Exclusive_Unblock [1109 ] 1109 |
| Clean_Writeback [899 ] 899 |
| Dirty_Writeback [194 ] 194 |
| Memory_Data [1109 ] 1109 |
| Memory_Ack [194 ] 194 |
| DMA_READ [0 ] 0 |
| DMA_WRITE [0 ] 0 |
| DMA_ACK [0 ] 0 |
| Data [0 ] 0 |
| |
| - Transitions - |
| I GETX [130 ] 130 |
| I GETS [979 ] 979 |
| I PUTX [0 ] 0 |
| I PUTO [0 ] 0 |
| I Memory_Data [0 ] 0 |
| I Memory_Ack [193 ] 193 |
| I DMA_READ [0 ] 0 |
| I DMA_WRITE [0 ] 0 |
| |
| S GETX [0 ] 0 |
| S GETS [0 ] 0 |
| S PUTX [0 ] 0 |
| S PUTO [0 ] 0 |
| S Memory_Data [0 ] 0 |
| S Memory_Ack [0 ] 0 |
| S DMA_READ [0 ] 0 |
| S DMA_WRITE [0 ] 0 |
| |
| O GETX [0 ] 0 |
| O GETS [0 ] 0 |
| O PUTX [0 ] 0 |
| O PUTO [0 ] 0 |
| O PUTO_SHARERS [0 ] 0 |
| O Memory_Data [0 ] 0 |
| O Memory_Ack [0 ] 0 |
| O DMA_READ [0 ] 0 |
| O DMA_WRITE [0 ] 0 |
| |
| M GETX [0 ] 0 |
| M GETS [0 ] 0 |
| M PUTX [1093 ] 1093 |
| M PUTO [0 ] 0 |
| M PUTO_SHARERS [0 ] 0 |
| M Memory_Data [0 ] 0 |
| M Memory_Ack [0 ] 0 |
| M DMA_READ [0 ] 0 |
| M DMA_WRITE [0 ] 0 |
| |
| IS GETX [0 ] 0 |
| IS GETS [0 ] 0 |
| IS PUTX [0 ] 0 |
| IS PUTO [0 ] 0 |
| IS PUTO_SHARERS [0 ] 0 |
| IS Unblock [0 ] 0 |
| IS Exclusive_Unblock [979 ] 979 |
| IS Memory_Data [979 ] 979 |
| IS Memory_Ack [1 ] 1 |
| IS DMA_READ [0 ] 0 |
| IS DMA_WRITE [0 ] 0 |
| |
| SS GETX [0 ] 0 |
| SS GETS [0 ] 0 |
| SS PUTX [0 ] 0 |
| SS PUTO [0 ] 0 |
| SS PUTO_SHARERS [0 ] 0 |
| SS Unblock [0 ] 0 |
| SS Last_Unblock [0 ] 0 |
| SS Memory_Data [0 ] 0 |
| SS Memory_Ack [0 ] 0 |
| SS DMA_READ [0 ] 0 |
| SS DMA_WRITE [0 ] 0 |
| |
| OO GETX [0 ] 0 |
| OO GETS [0 ] 0 |
| OO PUTX [0 ] 0 |
| OO PUTO [0 ] 0 |
| OO PUTO_SHARERS [0 ] 0 |
| OO Unblock [0 ] 0 |
| OO Last_Unblock [0 ] 0 |
| OO Memory_Data [0 ] 0 |
| OO Memory_Ack [0 ] 0 |
| OO DMA_READ [0 ] 0 |
| OO DMA_WRITE [0 ] 0 |
| |
| MO GETX [0 ] 0 |
| MO GETS [0 ] 0 |
| MO PUTX [0 ] 0 |
| MO PUTO [0 ] 0 |
| MO PUTO_SHARERS [0 ] 0 |
| MO Unblock [0 ] 0 |
| MO Exclusive_Unblock [0 ] 0 |
| MO Memory_Data [0 ] 0 |
| MO Memory_Ack [0 ] 0 |
| MO DMA_READ [0 ] 0 |
| MO DMA_WRITE [0 ] 0 |
| |
| MM GETX [0 ] 0 |
| MM GETS [0 ] 0 |
| MM PUTX [0 ] 0 |
| MM PUTO [0 ] 0 |
| MM PUTO_SHARERS [0 ] 0 |
| MM Exclusive_Unblock [130 ] 130 |
| MM Memory_Data [130 ] 130 |
| MM Memory_Ack [0 ] 0 |
| MM DMA_READ [0 ] 0 |
| MM DMA_WRITE [0 ] 0 |
| |
| |
| MI GETX [0 ] 0 |
| MI GETS [0 ] 0 |
| MI PUTX [0 ] 0 |
| MI PUTO [0 ] 0 |
| MI PUTO_SHARERS [0 ] 0 |
| MI Unblock [0 ] 0 |
| MI Clean_Writeback [899 ] 899 |
| MI Dirty_Writeback [194 ] 194 |
| MI Memory_Data [0 ] 0 |
| MI Memory_Ack [0 ] 0 |
| MI DMA_READ [0 ] 0 |
| MI DMA_WRITE [0 ] 0 |
| |
| MIS GETX [0 ] 0 |
| MIS GETS [0 ] 0 |
| MIS PUTX [0 ] 0 |
| MIS PUTO [0 ] 0 |
| MIS PUTO_SHARERS [0 ] 0 |
| MIS Unblock [0 ] 0 |
| MIS Clean_Writeback [0 ] 0 |
| MIS Dirty_Writeback [0 ] 0 |
| MIS Memory_Data [0 ] 0 |
| MIS Memory_Ack [0 ] 0 |
| MIS DMA_READ [0 ] 0 |
| MIS DMA_WRITE [0 ] 0 |
| |
| OS GETX [0 ] 0 |
| OS GETS [0 ] 0 |
| OS PUTX [0 ] 0 |
| OS PUTO [0 ] 0 |
| OS PUTO_SHARERS [0 ] 0 |
| OS Unblock [0 ] 0 |
| OS Clean_Writeback [0 ] 0 |
| OS Dirty_Writeback [0 ] 0 |
| OS Memory_Data [0 ] 0 |
| OS Memory_Ack [0 ] 0 |
| OS DMA_READ [0 ] 0 |
| OS DMA_WRITE [0 ] 0 |
| |
| OSS GETX [0 ] 0 |
| OSS GETS [0 ] 0 |
| OSS PUTX [0 ] 0 |
| OSS PUTO [0 ] 0 |
| OSS PUTO_SHARERS [0 ] 0 |
| OSS Unblock [0 ] 0 |
| OSS Clean_Writeback [0 ] 0 |
| OSS Dirty_Writeback [0 ] 0 |
| OSS Memory_Data [0 ] 0 |
| OSS Memory_Ack [0 ] 0 |
| OSS DMA_READ [0 ] 0 |
| OSS DMA_WRITE [0 ] 0 |
| |
| XI_M GETX [0 ] 0 |
| XI_M GETS [0 ] 0 |
| XI_M PUTX [0 ] 0 |
| XI_M PUTO [0 ] 0 |
| XI_M PUTO_SHARERS [0 ] 0 |
| XI_M Memory_Data [0 ] 0 |
| XI_M Memory_Ack [0 ] 0 |
| XI_M DMA_READ [0 ] 0 |
| XI_M DMA_WRITE [0 ] 0 |
| |
| XI_U GETX [0 ] 0 |
| XI_U GETS [0 ] 0 |
| XI_U PUTX [0 ] 0 |
| XI_U PUTO [0 ] 0 |
| XI_U PUTO_SHARERS [0 ] 0 |
| XI_U Exclusive_Unblock [0 ] 0 |
| XI_U Memory_Ack [0 ] 0 |
| XI_U DMA_READ [0 ] 0 |
| XI_U DMA_WRITE [0 ] 0 |
| |
| OI_D GETX [0 ] 0 |
| OI_D GETS [0 ] 0 |
| OI_D PUTX [0 ] 0 |
| OI_D PUTO [0 ] 0 |
| OI_D PUTO_SHARERS [0 ] 0 |
| OI_D DMA_READ [0 ] 0 |
| OI_D DMA_WRITE [0 ] 0 |
| OI_D Data [0 ] 0 |
| |
| OD GETX [0 ] 0 |
| OD GETS [0 ] 0 |
| OD PUTX [0 ] 0 |
| OD PUTO [0 ] 0 |
| OD PUTO_SHARERS [0 ] 0 |
| OD DMA_READ [0 ] 0 |
| OD DMA_WRITE [0 ] 0 |
| OD DMA_ACK [0 ] 0 |
| |
| MD GETX [0 ] 0 |
| MD GETS [0 ] 0 |
| MD PUTX [0 ] 0 |
| MD PUTO [0 ] 0 |
| MD PUTO_SHARERS [0 ] 0 |
| MD DMA_READ [0 ] 0 |
| MD DMA_WRITE [0 ] 0 |
| MD DMA_ACK [0 ] 0 |
| |