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gem5 / arm / gem5 / 6f4bd2c1da0dc7783da87c4877a41332901199b2 / src / cpu / o3 / fetch_impl.hh
  1. 6f4bd2c ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. by Gabe Black · 14 years ago
  2. d8d6b86 O3: Skipping mem-order violation check for uncachable loads. by Min Kyu Jeong · 15 years ago
  3. e6a0be6 ARM: Improve printing of uop disassembly. by Min Kyu Jeong · 15 years ago
  4. f28ea7a O3: Mark fetch stage as active if it faults. by Steve Reinhardt · 15 years ago
  5. d9f39c8 arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh by Nathan Binkert · 15 years ago
  6. a13a706 Fix setting of INST_FETCH flag for O3 CPU. by Steve Reinhardt · 16 years ago
  7. 47877cf types: add a type for thread IDs and try to use it everywhere by Nathan Binkert · 16 years ago
  8. 8d2e51c includes: sort includes again by Nathan Binkert · 16 years ago
  9. eef3a2e types: Move stuff for global types into src/base/types.hh by Nathan Binkert · 16 years ago
  10. 5c1742b o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode stage was not setting the predicted PC correctly or passing that information back to fetch correctly by Korey Sewell · 16 years ago
  11. b146131 o3: handle fetch with no active threads correctly. by Steve Reinhardt · 16 years ago
  12. e0de2c3 tlb: More fixing of unified TLB by Nathan Binkert · 16 years ago
  13. 7b5a96f tlb: Don't separate the TLB classes into an instruction TLB and a data TLB by Gabe Black · 16 years ago
  14. 9ee8e68 O3: Make numThreads error message more helpful. by Steve Reinhardt · 16 years ago
  15. 5605079 ISA: Replace the translate functions in the TLBs with translateAtomic. by Gabe Black · 16 years ago
  16. a1aba01 CPU: Get rid of translate... functions from various interface classes. by Gabe Black · 16 years ago
  17. d857faf Add in Context IDs to the simulator. From now on, cpuId is almost never used, by Lisa Hsu · 16 years ago
  18. c55a467 make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered by Lisa Hsu · 16 years ago
  19. ee62a0f params: Convert the CPU objects to use the auto generated param structs. by Nathan Binkert · 17 years ago
  20. caaac16 Backed out changeset 94a7bb476fca: caused memory leak. by Steve Reinhardt · 17 years ago
  21. 6b45238 Generate more useful error messages for unconnected ports. by Steve Reinhardt · 17 years ago
  22. 7227ab5 Merge with head by Gabe Black · 18 years ago
  23. 537239b Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. by Gabe Black · 18 years ago
  24. 92a57ed O3: Set up the predicted npc and nnpc for a fault carrying noop so that it doesn't cause a false branch mispredict. by Gabe Black · 18 years ago
  25. 08474cc Merge Gabe's changes from head. by Steve Reinhardt · 18 years ago
  26. 8dd7700 Turn the instruction tracing code into pluggable sim objects. by Gabe Black · 18 years ago
  27. 6ab5341 Get rid of Packet result field. Error responses are now encoded in cmd field. by Steve Reinhardt · 18 years ago
  28. 49490b3 Merge zizzer.eecs.umich.edu:/bk/newmem by Gabe Black · 18 years ago
  29. df7730b Fix compiler errors. by Gabe Black · 18 years ago
  30. 5c48a05 Merge zizzer.eecs.umich.edu:/bk/newmem by Gabe Black · 18 years ago
  31. ea70e6d Make branches work by repopulating the predecoder every time through. This is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though. by Gabe Black · 18 years ago
  32. cd8f604 Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst. by Gabe Black · 18 years ago
  33. 11f1c8d Use the right type by Nathan Binkert · 18 years ago
  34. aba2eea Fix typo so m5.fast will compile by Nathan Binkert · 18 years ago
  35. d8c487c don't generate trace data unless tracing is on by Ali Saidi · 18 years ago
  36. 8248af5 Make an inner loop which pulls microops out of macroops. These aren't checked for control flow because we can pull out microops until we run out of buffer. This prevents microops from being interpretted as branches because the pc doesn't become npc. by Gabe Black · 18 years ago
  37. c3081d9 Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect. by Gabe Black · 18 years ago
  38. c7f1cf1 Remove most of the special handling for delay slots since they have to be squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect. by Gabe Black · 18 years ago
  39. 6ff6621 Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions. by Kevin Lim · 18 years ago
  40. ec09e5a Remove/comment out DPRINTFs that were causing a segfault. by Kevin Lim · 18 years ago
  41. 80af653 Update code so that the O3 CPU can handle not initially having anything hooked up to its ports. This fixes the segfault Ali recently found when using sampling. by Kevin Lim · 18 years ago
  42. 047f771 Merge ktlim@zizzer:/bk/newmem by Kevin Lim · 18 years ago
  43. 31e78b0 Two fixes: by Kevin Lim · 18 years ago
  44. a2b5608 Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86. by Gabe Black · 18 years ago
  45. ce18d90 Replaced makeExtMI with predecode. by Gabe Black · 18 years ago
  46. d55b25c Move all of the parameters of the Root SimObject so they are by Nathan Binkert · 18 years ago
  47. 997fc50 Make memory commands dense again to avoid cache stat table explosion. by Steve Reinhardt · 18 years ago
  48. e176c7d A minor hack to get branch prediction to behave like before on Alpha. by Gabe Black · 18 years ago
  49. 8840ebc Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem by Gabe Black · 18 years ago
  50. 3f2b25d Phased out DelaySlotInfo. by Gabe Black · 18 years ago
  51. 9aecfb3 don't use (*activeThreads).begin(), use activeThreads->blah(). by Nathan Binkert · 18 years ago
  52. 327f451 Fixes to get ALPHA_FS and ALPHA_SE to compile again. by Gabe Black · 18 years ago
  53. 96e5086 Make fetch detect when a branch is happening, rather than trying to compute when. by Gabe Black · 18 years ago
  54. 37b9966 Made branch delay slots get squashed, and passed back an NPC and NNPC to start fetching from. by Gabe Black · 18 years ago
  55. 90907f6 Merge zizzer:/bk/newmem/ into zower.eecs.umich.edu:/eecshome/m5/newmem by Gabe Black · 18 years ago
  56. 1868c9f Fix for fetch to use the icache's block size to generate proper access size. by Kevin Lim · 18 years ago
  57. 2dcf00b Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem by Gabe Black · 18 years ago
  58. be29adf Added a DPRINTF to print out the actual value pulled from memory. by Gabe Black · 18 years ago
  59. c0f21b0 Fixes for MIPS_SE compiling. Regressions seem to work, but Korey should make sure these changes (commit especially) work okay. by Kevin Lim · 18 years ago
  60. a962fc4 Make CPU models signal to update the snoop ranges by Ron Dreslinski · 18 years ago
  61. 8a0cbbe Fix for regression failure. by Kevin Lim · 18 years ago
  62. 3052632 Merge ktlim@zamp:./local/clean/tmp/test-regress by Kevin Lim · 18 years ago
  63. 12e26c6 Updates to support new interrupt processing and removal of PcPAL. by Kevin Lim · 18 years ago
  64. b5e68fb Merge ktlim@zizzer:/bk/newmem by Kevin Lim · 18 years ago
  65. f593c8a Change up some warnings to DPRINTFs. by Kevin Lim · 18 years ago
  66. 85a6079 Remote GDB support has been changed to use inheritance. Alpha should work, but isn't tested. Other architectures will not. by Gabe Black · 18 years ago
  67. 118b9dc Got rid of "inPalMode". Some places are still effectively checking if they are in PAL mode, however. by Gabe Black · 18 years ago
  68. ccaf80c Use ISA specific makeExtMI. by Kevin Lim · 18 years ago
  69. bfd5eb2 Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject. by Kevin Lim · 18 years ago
  70. ce4531c Merge ktlim@zizzer:/bk/newmem by Kevin Lim · 18 years ago
  71. 4ccccfe Fix fetch to stop fetching upon encountering a fault in SE mode. Also change warning to a DPRINTF. by Kevin Lim · 18 years ago
  72. 0b5cf4b Merge zizzer.eecs.umich.edu:/bk/newmem by Gabe Black · 18 years ago
  73. a4c6f0d Use PacketPtr everywhere by Nathan Binkert · 18 years ago
  74. 9c582c7 Fixes for uni-coherence in timing mode for FS. by Ron Dreslinski · 18 years ago
  75. 519d11b Merge zizzer.eecs.umich.edu:/bk/newmem by Gabe Black · 18 years ago
  76. a50e83c Fix assertion. I haven't tested it fully (I can't reproduce Lisa's error) but I believe it should fix what she's running into (which was definitely a bug). by Kevin Lim · 18 years ago
  77. 866cfaf Merge zizzer.eecs.umich.edu:/bk/newmem by Gabe Black · 18 years ago
  78. bdde892 Merge ktlim@zizzer:/bk/newmem by Kevin Lim · 18 years ago
  79. 5cb1840 Fixes for functional path. by Ron Dreslinski · 18 years ago
  80. 5df93cc Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable(). by Steve Reinhardt · 18 years ago
  81. d48ea81 Updates to O3 CPU. It should now work in FS mode, although sampling still has a bug. by Kevin Lim · 18 years ago
  82. e8ced44 Merge zizzer.eecs.umich.edu:/bk/newmem by Gabe Black · 18 years ago
  83. 4ed184e Merge ktlim@zamp:./local/clean/o3-merge/m5 by Kevin Lim · 18 years ago
  84. 76708a9 Changed makeExtMI to take a ThreadContext instead of a pc. by Gabe Black · 18 years ago
  85. 8abab05 Merge zizzer.eecs.umich.edu:/bk/newmem into ewok.(none):/home/gblack/m5/newmem by Gabe Black · 18 years ago
  86. c32ef32 Fix up the parameters to getInstRecord by Gabe Black · 19 years ago
  87. 82862e0 add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throughout CPU models by Korey Sewell · 19 years ago
  88. ec0a18f Fixes for Kevins O3 model to work with the blocking caches. by Ron Dreslinski · 19 years ago
  89. 74e80fc Some touchup to the reorganized includes and "using" directives. by Gabe Black · 19 years ago
  90. 74546aa Cleaned up include files and got rid of many using directives in header files. by Gabe Black · 19 years ago
  91. 95561dc MIPS ISA runs 'hello world' in O3CPU ... by Korey Sewell · 19 years ago
  92. 19ca97a This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds, runs, and gets very very close to completing the hello world by Korey Sewell · 19 years ago
  93. 2af2130 Fix for bug when squashing and the fetching. Now fetch checks if the cache data is valid. by Kevin Lim · 19 years ago
  94. bbfe1db Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem by Kevin Lim · 19 years ago
  95. 6d120b7 Track the PC of the cache data stored in fetch so it doesn't access memory multiple times if information is already in fetch. by Kevin Lim · 19 years ago
  96. 6bcc65c Fix ordering issue with squashed Icache Fetches and Static data in packet. by Ron Dreslinski · 19 years ago
  97. 8ade33d Support Ron's changes for hooking up ports. by Kevin Lim · 19 years ago
  98. 744e005 Fix for bug when draining and a memory access is outstanding. by Kevin Lim · 19 years ago
  99. fbe3e22 Fix the O3CPU to support the multi-pass method for checking if the system has fully drained. by Kevin Lim · 19 years ago
  100. 30c516d Support for draining, and the new method of switching out. Now switching out happens after the pipeline has been drained, deferring the three way handshake to the normal drain mechanism. The calls of switchOut() and takeOverFrom() both take action immediately. by Kevin Lim · 19 years ago