ARM: Fix broken coherency for DMA ops

This fixes a problem with dc zva/WriteInvalidate testing on v7. The
The system has coherent I/O and the kernel needs to know this.

What would happen is the IO cache would hold DMA descriptor information
in Exclusive state and the core would send uncacheable requests that
effectively bypassed the coherence.  The IO device would then act on
incoherent data.
2 files changed