| /dts-v1/; |
| |
| / { |
| #address-cells = <0x2>; |
| #size-cells = <0x2>; |
| compatible = "riscv-virtio"; |
| model = "riscv-virtio,qemu"; |
| |
| chosen { |
| bootargs = "root=/dev/vda ro console=ttyS0"; |
| stdout-path = "/soc/uart@10000000"; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x0 0x80000000 0x0 0x8000000>; |
| }; |
| |
| cpus { |
| #address-cells = <0x1>; |
| #size-cells = <0x0>; |
| timebase-frequency = <0x989680>; |
| |
| cpu@0 { |
| phandle = <0x1>; |
| device_type = "cpu"; |
| reg = <0x0>; |
| status = "okay"; |
| compatible = "riscv"; |
| riscv,isa = "rv64imafdcsu"; |
| mmu-type = "riscv,sv48"; |
| |
| interrupt-controller { |
| #interrupt-cells = <0x1>; |
| interrupt-controller; |
| compatible = "riscv,cpu-intc"; |
| phandle = <0x2>; |
| }; |
| }; |
| }; |
| |
| soc { |
| #address-cells = <0x2>; |
| #size-cells = <0x2>; |
| compatible = "simple-bus"; |
| ranges; |
| |
| uart@10000000 { |
| interrupts = <0xa>; |
| interrupt-parent = <0x3>; |
| clock-frequency = <0x384000>; |
| reg = <0x0 0x10000000 0x0 0x008>; |
| compatible = "ns8250"; |
| }; |
| |
| plic@c000000 { |
| phandle = <0x3>; |
| riscv,ndev = <0xa>; |
| reg = <0x0 0xc000000 0x0 0x210000>; |
| interrupts-extended = <0x2 0xb 0x2 0x9>; |
| interrupt-controller; |
| compatible = "riscv,plic0"; |
| #interrupt-cells = <0x1>; |
| #address-cells = <0x0>; |
| }; |
| |
| virtio_mmio@10008000 { |
| interrupts = <0x8>; |
| interrupt-parent = <0x3>; |
| reg = <0x0 0x10008000 0x0 0x1000>; |
| compatible = "virtio,mmio"; |
| }; |
| |
| clint@2000000 { |
| interrupts-extended = <0x2 0x3 0x2 0x7>; |
| reg = <0x0 0x2000000 0x0 0x10000>; |
| compatible = "riscv,clint0"; |
| }; |
| }; |
| }; |