commit 52e798973b0b7f07fa252b8f338671b9fba5dbc0
author Hoa Nguyen <hoanguyen@ucdavis.edu> Mon Dec 07 22:23:12 2020 -0800
committer Hoa Nguyen <hoanguyen@ucdavis.edu> Tue Dec 08 23:03:34 2020 +0000
tree 51c8f0395123f45fd88ed6d0007d8e55a3c2b501
parent bc298e9e9be0398067057370b8de28b665d2d27b

resources: Remove icache from Sequencer constructor for boot_exit

Update gem5 configs of boot_exit to accommodate this change,
https://gem5-review.googlesource.com/c/public/gem5/+/31267

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I204942e20c723d1766c8d920c49ab33837db4403
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/38378
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>

src/boot-exit/configs/system/MESI_Two_Level.py

diff --git a/src/boot-exit/configs/system/MESI_Two_Level.py b/src/boot-exit/configs/system/MESI_Two_Level.py
index 52f0ae5..629e288 100755
--- a/src/boot-exit/configs/system/MESI_Two_Level.py
+++ b/src/boot-exit/configs/system/MESI_Two_Level.py
@@ -82,8 +82,7 @@
         # Create one sequencer per CPU and dma controller.
         # Sequencers for other controllers can be here here.
         self.sequencers = [RubySequencer(version = i,
-                                # I/D cache is combined and grab from ctrl
-                                icache = self.controllers[i].L1Icache,
+                                # Grab dcache from ctrl
                                 dcache = self.controllers[i].L1Dcache,
                                 clk_domain = self.controllers[i].clk_domain,
                                 pio_request_port = iobus.cpu_side_ports,

src/boot-exit/configs/system/MI_example_caches.py

diff --git a/src/boot-exit/configs/system/MI_example_caches.py b/src/boot-exit/configs/system/MI_example_caches.py
index 0f532ee..84bcab5 100755
--- a/src/boot-exit/configs/system/MI_example_caches.py
+++ b/src/boot-exit/configs/system/MI_example_caches.py
@@ -83,8 +83,7 @@
         # complicated since you have to create sequencers for DMA controllers
         # and other controllers, too.
         self.sequencers = [RubySequencer(version = i,
-                                # I/D cache is combined and grab from ctrl
-                                icache = self.controllers[i].cacheMemory,
+                                # Grab dcache from ctrl
                                 dcache = self.controllers[i].cacheMemory,
                                 clk_domain = self.controllers[i].clk_domain,
                                 pio_request_port = iobus.cpu_side_ports,

src/boot-exit/configs/system/MOESI_CMP_directory.py

diff --git a/src/boot-exit/configs/system/MOESI_CMP_directory.py b/src/boot-exit/configs/system/MOESI_CMP_directory.py
index e23b8f6..7dc034a 100755
--- a/src/boot-exit/configs/system/MOESI_CMP_directory.py
+++ b/src/boot-exit/configs/system/MOESI_CMP_directory.py
@@ -83,8 +83,7 @@
         # Create one sequencer per CPU and dma controller.
         # Sequencers for other controllers can be here here.
         self.sequencers = [RubySequencer(version = i,
-                                # I/D cache is combined and grab from ctrl
-                                icache = self.controllers[i].L1Icache,
+                                # Grab dcache from ctrl
                                 dcache = self.controllers[i].L1Dcache,
                                 clk_domain = self.controllers[i].clk_domain,
                                 pio_request_port = iobus.cpu_side_ports,