commit 73dc22eda2fc149ba7d82c138008ae5eca153cbb
author Hoa Nguyen <hoanguyen@ucdavis.edu> Tue Dec 08 00:50:11 2020 -0800
committer Hoa Nguyen <hoanguyen@ucdavis.edu> Tue Dec 08 23:05:50 2020 +0000
tree 473af5bde0fb9cae6af01c7e3f3a1a535ab48230
parent 22cc0352ee887a87201c04f852d2809232fe6216

resources: Update gem5 configs of spec-2006 to python3

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I67ef72e2f8ef52c812dd9da9b3c6e30703c1ab4e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/38396
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>

src/spec-2006/configs/system/ruby_system.py

diff --git a/src/spec-2006/configs/system/ruby_system.py b/src/spec-2006/configs/system/ruby_system.py
index e41d16b..1a15eeb 100755
--- a/src/spec-2006/configs/system/ruby_system.py
+++ b/src/spec-2006/configs/system/ruby_system.py
@@ -72,13 +72,13 @@
 
         # Create the cache hierarchy for the system.
         if mem_sys == 'MI_example':
-            from MI_example_caches import MIExampleSystem
+            from .MI_example_caches import MIExampleSystem
             self.caches = MIExampleSystem()
         elif mem_sys == 'MESI_Two_Level':
-            from MESI_Two_Level import MESITwoLevelCache
+            from .MESI_Two_Level import MESITwoLevelCache
             self.caches = MESITwoLevelCache()
         elif mem_sys == 'MOESI_CMP_directory':
-            from MOESI_CMP_directory import MOESICMPDirCache
+            from .MOESI_CMP_directory import MOESICMPDirCache
             self.caches = MOESICMPDirCache()
         self.caches.setup(self, self.cpu, self.mem_cntrls,
                           [self.pc.south_bridge.ide.dma, self.iobus.mem_side_ports],
@@ -102,31 +102,35 @@
             if self._no_kvm:
                 self.cpu = [AtomicSimpleCPU(cpu_id = i, switched_out = False)
                                 for i in range(num_cpus)]
-                map(lambda c: c.createThreads(), self.cpu)
+                for c in self.cpu:
+                    c.createThreads()
                 self.mem_mode = 'timing'
 
             else:
                 # Note KVM needs a VM and atomic_noncaching
                 self.cpu = [X86KvmCPU(cpu_id = i)
                             for i in range(num_cpus)]
-                map(lambda c: c.createThreads(), self.cpu)
+                for c in self.cpu:
+                    c.createThreads()
                 self.kvm_vm = KvmVM()
                 self.mem_mode = 'atomic_noncaching'
 
                 self.atomicCpu = [AtomicSimpleCPU(cpu_id = i,
                                                 switched_out = True)
                                 for i in range(num_cpus)]
-                map(lambda c: c.createThreads(), self.atomicCpu)
+                for c in self.atomicCpu:
+                    c.createThreads()
 
             self.detailed_cpu = [TimingCPUModel(cpu_id = i,
                                         switched_out = True)
                     for i in range(num_cpus)]
-
-            map(lambda c: c.createThreads(), self.detailed_cpu)
+            
+            for c in self.detailed_cpu:
+                c.createThreads()
 
     def switchCpus(self, old, new):
         assert(new[0].switchedOut())
-        m5.switchCpus(self, zip(old, new))
+        m5.switchCpus(self, list(zip(old, new)))
 
     def setDiskImages(self, img_path_1, img_path_2):
         disk0 = CowDisk(img_path_1)