commit 8044978875dd66aa5b4a0152fdbeec4bd2411858
author Hoa Nguyen <hoanguyen@ucdavis.edu> Wed Dec 09 02:52:36 2020 -0800
committer Hoa Nguyen <hoanguyen@ucdavis.edu> Tue Dec 22 02:42:59 2020 +0000
tree c9c406f962a31106dc20c4119e4190fa2dccf04a
parent e41c71a1354e43cfccd7fb0fa165b78b8ae535b4

resources: Remove icache from Sequencer constructor in gapbs configs

Update gem5 configs of gapbs to accommodate this
change: https://gem5-review.googlesource.com/c/public/gem5/+/31267

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I303b9928bdbefc5c65a7de2b092f49bb5236c665
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/38439
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Jason Lowe-Power <power.jg@gmail.com>

src/gapbs/configs/system/MESI_Two_Level.py

diff --git a/src/gapbs/configs/system/MESI_Two_Level.py b/src/gapbs/configs/system/MESI_Two_Level.py
index dec9e10..edde9ed 100644
--- a/src/gapbs/configs/system/MESI_Two_Level.py
+++ b/src/gapbs/configs/system/MESI_Two_Level.py
@@ -79,8 +79,7 @@
         # Create one sequencer per CPU and dma controller.
         # Sequencers for other controllers can be here here.
         self.sequencers = [RubySequencer(version = i,
-                                # I/D cache is combined and grab from ctrl
-                                icache = self.controllers[i].L1Icache,
+                                # Grab dcache from ctrl
                                 dcache = self.controllers[i].L1Dcache,
                                 clk_domain = self.controllers[i].clk_domain,
                                 pio_request_port = iobus.cpu_side_ports,

src/gapbs/configs/system/MI_example_caches.py

diff --git a/src/gapbs/configs/system/MI_example_caches.py b/src/gapbs/configs/system/MI_example_caches.py
index 8f16590..3d71ee4 100644
--- a/src/gapbs/configs/system/MI_example_caches.py
+++ b/src/gapbs/configs/system/MI_example_caches.py
@@ -83,8 +83,7 @@
         # complicated since you have to create sequencers for DMA controllers
         # and other controllers, too.
         self.sequencers = [RubySequencer(version = i,
-                                # I/D cache is combined and grab from ctrl
-                                icache = self.controllers[i].cacheMemory,
+                                # Grab dcache from ctrl
                                 dcache = self.controllers[i].cacheMemory,
                                 clk_domain = self.controllers[i].clk_domain,
                                 pio_request_port = iobus.cpu_side_ports,