resources: Fix errors in gapbs configs
This commit addresses the following errors,
- Update the way of creating MemCtrl
- Fix memory terminology typos (in_port -> in_ports)
- Revert mmu walker port change that is not compatible w/ gem5 20.1
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: Ib91338d2f71a518692c45c7e16957221767a51b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/38436
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Jason Lowe-Power <power.jg@gmail.com>
diff --git a/src/gapbs/configs/system/MESI_Two_Level.py b/src/gapbs/configs/system/MESI_Two_Level.py
index ca542cb..dc868ab 100644
--- a/src/gapbs/configs/system/MESI_Two_Level.py
+++ b/src/gapbs/configs/system/MESI_Two_Level.py
@@ -88,7 +88,7 @@
pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
- in_port = port)
+ in_ports = port)
for i,port in enumerate(dma_ports)
]
@@ -110,22 +110,22 @@
# Set up a proxy port for the system_port. Used for load binaries and
# other functional-only things.
self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_port
+ system.system_port = self.sys_port_proxy.in_ports
self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
# Connect the cpu's cache, interrupt, and TLB ports to Ruby
for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_port
- cpu.dcache_port = self.sequencers[i].in_port
+ cpu.icache_port = self.sequencers[i].in_ports
+ cpu.dcache_port = self.sequencers[i].in_ports
isa = buildEnv['TARGET_ISA']
if isa == 'x86':
cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_port
+ cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
cpu.interrupts[0].int_responder = \
self.sequencers[i].interrupt_out_port
if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].in_port
- cpu.dtb.walker.port = self.sequencers[i].in_port
+ cpu.itb.walker.port = self.sequencers[i].in_ports
+ cpu.dtb.walker.port = self.sequencers[i].in_ports
class L1Cache(L1Cache_Controller):
diff --git a/src/gapbs/configs/system/MI_example_caches.py b/src/gapbs/configs/system/MI_example_caches.py
index 4ea5938..79ca7a6 100644
--- a/src/gapbs/configs/system/MI_example_caches.py
+++ b/src/gapbs/configs/system/MI_example_caches.py
@@ -92,7 +92,7 @@
pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
- in_port = port)
+ in_ports = port)
for i,port in enumerate(dma_ports)
]
@@ -113,22 +113,22 @@
# Set up a proxy port for the system_port. Used for load binaries and
# other functional-only things.
self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.in_port
+ system.system_port = self.sys_port_proxy.in_ports
self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
# Connect the cpu's cache, interrupt, and TLB ports to Ruby
for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].in_port
- cpu.dcache_port = self.sequencers[i].in_port
+ cpu.icache_port = self.sequencers[i].in_ports
+ cpu.dcache_port = self.sequencers[i].in_ports
isa = buildEnv['TARGET_ISA']
if isa == 'x86':
cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
- cpu.interrupts[0].int_requestor = self.sequencers[i].in_port
+ cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
cpu.interrupts[0].int_responder = \
self.sequencers[i].interrupt_out_port
if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].in_port
- cpu.dtb.walker.port = self.sequencers[i].in_port
+ cpu.itb.walker.port = self.sequencers[i].in_ports
+ cpu.dtb.walker.port = self.sequencers[i].in_ports
class L1Cache(L1Cache_Controller):
diff --git a/src/gapbs/configs/system/caches.py b/src/gapbs/configs/system/caches.py
index ddc578d..c13f099 100755
--- a/src/gapbs/configs/system/caches.py
+++ b/src/gapbs/configs/system/caches.py
@@ -130,8 +130,8 @@
"""
self.mmubus = L2XBar()
self.cpu_side = self.mmubus.mem_side_ports
- cpu.mmu.connectWalkerPorts(
- self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
+ for tlb in [cpu.itb, cpu.dtb]:
+ self.mmubus.cpu_side_ports = tlb.walker.port
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
diff --git a/src/gapbs/configs/system/ruby_system.py b/src/gapbs/configs/system/ruby_system.py
index d0afeae..e5c602a 100755
--- a/src/gapbs/configs/system/ruby_system.py
+++ b/src/gapbs/configs/system/ruby_system.py
@@ -143,7 +143,7 @@
def _createMemoryControllers(self, num, cls):
self.mem_cntrls = [
- cls(range = self.mem_ranges[0])
+ MemCtrl(dram = cls(range = self.mem_ranges[0]))
for i in range(num)
]
diff --git a/src/gapbs/configs/system/system.py b/src/gapbs/configs/system/system.py
index 1e82b12..9a4cb4d 100755
--- a/src/gapbs/configs/system/system.py
+++ b/src/gapbs/configs/system/system.py
@@ -203,14 +203,14 @@
ranges = self._getInterleaveRanges(self.mem_ranges[-1], num, 7, 20)
self.mem_cntrls = [
- cls(range = ranges[i],
- port = self.membus.mem_side_ports)
+ MemCtrl(dram = cls(range = ranges[i]),
+ port = self.membus.mem_side_ports)
for i in range(num)
] + [kernel_controller]
def _createKernelMemoryController(self, cls):
- return cls(range = self.mem_ranges[0],
- port = self.membus.mem_side_ports)
+ return MemCtrl(dram = cls(range = self.mem_ranges[0]),
+ port = self.membus.mem_side_ports)
def _getInterleaveRanges(self, rng, num, intlv_low_bit, xor_low_bit):
from math import log
