commit a282086cc4f51a4bb714493ea410da5c574d63fb
author Hoa Nguyen <hoanguyen@ucdavis.edu> Tue Mar 23 06:00:08 2021 -0700
committer Bobby R. Bruce <bbruce@ucdavis.edu> Wed Mar 24 00:22:05 2021 +0000
tree c51445adf25d95ed2c755ebf3e519c57f0b51926
parent d6c71751136752bf90c44432c3d32efaab5d99cd

resources: Fix spec-2006 system configs

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I74f913132e0fdcdf27a6a625b945402e26624960
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/43466
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>

src/spec-2006/configs/system/MESI_Two_Level.py

diff --git a/src/spec-2006/configs/system/MESI_Two_Level.py b/src/spec-2006/configs/system/MESI_Two_Level.py
index 8a300e2..17df7c0 100644
--- a/src/spec-2006/configs/system/MESI_Two_Level.py
+++ b/src/spec-2006/configs/system/MESI_Two_Level.py
@@ -90,7 +90,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]
 

src/spec-2006/configs/system/MI_example_caches.py

diff --git a/src/spec-2006/configs/system/MI_example_caches.py b/src/spec-2006/configs/system/MI_example_caches.py
index ddad234..0d028df 100644
--- a/src/spec-2006/configs/system/MI_example_caches.py
+++ b/src/spec-2006/configs/system/MI_example_caches.py
@@ -91,7 +91,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]
 

src/spec-2006/configs/system/MOESI_CMP_directory.py

diff --git a/src/spec-2006/configs/system/MOESI_CMP_directory.py b/src/spec-2006/configs/system/MOESI_CMP_directory.py
index 52cc9b7..15b215d 100644
--- a/src/spec-2006/configs/system/MOESI_CMP_directory.py
+++ b/src/spec-2006/configs/system/MOESI_CMP_directory.py
@@ -91,7 +91,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]
 
@@ -288,6 +288,7 @@
         self.forwardFromDir.out_port = ruby_system.network.in_port
         self.requestToMemory = MessageBuffer()
         self.responseFromMemory = MessageBuffer()
+        self.triggerQueue = MessageBuffer(ordered = True)
 
 class DMAController(DMA_Controller):
 

src/spec-2006/configs/system/ruby_system.py

diff --git a/src/spec-2006/configs/system/ruby_system.py b/src/spec-2006/configs/system/ruby_system.py
index e41d16b..4860504 100755
--- a/src/spec-2006/configs/system/ruby_system.py
+++ b/src/spec-2006/configs/system/ruby_system.py
@@ -72,13 +72,13 @@
 
         # Create the cache hierarchy for the system.
         if mem_sys == 'MI_example':
-            from MI_example_caches import MIExampleSystem
+            from .MI_example_caches import MIExampleSystem
             self.caches = MIExampleSystem()
         elif mem_sys == 'MESI_Two_Level':
-            from MESI_Two_Level import MESITwoLevelCache
+            from .MESI_Two_Level import MESITwoLevelCache
             self.caches = MESITwoLevelCache()
         elif mem_sys == 'MOESI_CMP_directory':
-            from MOESI_CMP_directory import MOESICMPDirCache
+            from .MOESI_CMP_directory import MOESICMPDirCache
             self.caches = MOESICMPDirCache()
         self.caches.setup(self, self.cpu, self.mem_cntrls,
                           [self.pc.south_bridge.ide.dma, self.iobus.mem_side_ports],
@@ -98,35 +98,39 @@
     def totalInsts(self):
         return sum([cpu.totalInsts() for cpu in self.cpu])
 
+    def createCPUThreads(self, cpu):
+        for c in cpu:
+            c.createThreads()
+
     def createCPU(self, num_cpus, TimingCPUModel):
             if self._no_kvm:
                 self.cpu = [AtomicSimpleCPU(cpu_id = i, switched_out = False)
                                 for i in range(num_cpus)]
-                map(lambda c: c.createThreads(), self.cpu)
+                self.createCPUThreads(self.cpu)
                 self.mem_mode = 'timing'
 
             else:
                 # Note KVM needs a VM and atomic_noncaching
                 self.cpu = [X86KvmCPU(cpu_id = i)
                             for i in range(num_cpus)]
-                map(lambda c: c.createThreads(), self.cpu)
+                self.createCPUThreads(self.cpu)
                 self.kvm_vm = KvmVM()
                 self.mem_mode = 'atomic_noncaching'
 
                 self.atomicCpu = [AtomicSimpleCPU(cpu_id = i,
                                                 switched_out = True)
                                 for i in range(num_cpus)]
-                map(lambda c: c.createThreads(), self.atomicCpu)
+                self.createCPUThreads(self.atomicCpu)
 
             self.detailed_cpu = [TimingCPUModel(cpu_id = i,
                                         switched_out = True)
                     for i in range(num_cpus)]
 
-            map(lambda c: c.createThreads(), self.detailed_cpu)
+            self.createCPUThreads(self.detailed_cpu)
 
     def switchCpus(self, old, new):
         assert(new[0].switchedOut())
-        m5.switchCpus(self, zip(old, new))
+        m5.switchCpus(self, list(zip(old, new)))
 
     def setDiskImages(self, img_path_1, img_path_2):
         disk0 = CowDisk(img_path_1)