resources: Update memory terminology
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I8420897147f57ff10c467d1b8c0126f675f897eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/37236
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Jason Lowe-Power <power.jg@gmail.com>
diff --git a/src/boot-exit/configs/system/MESI_Two_Level.py b/src/boot-exit/configs/system/MESI_Two_Level.py
index 4feef12..ec19ce2 100755
--- a/src/boot-exit/configs/system/MESI_Two_Level.py
+++ b/src/boot-exit/configs/system/MESI_Two_Level.py
@@ -91,7 +91,7 @@
pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
- slave = port)
+ in_port = port)
for i,port in enumerate(dma_ports)
]
@@ -124,7 +124,8 @@
if isa == 'x86':
cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
+ cpu.interrupts[0].int_responder = \
+ self.sequencers[i].interrupt_out_port
if isa == 'x86' or isa == 'arm':
cpu.itb.walker.port = self.sequencers[i].in_ports
cpu.dtb.walker.port = self.sequencers[i].in_ports
diff --git a/src/boot-exit/configs/system/MI_example_caches.py b/src/boot-exit/configs/system/MI_example_caches.py
index 8aa08ea..d104ebc 100755
--- a/src/boot-exit/configs/system/MI_example_caches.py
+++ b/src/boot-exit/configs/system/MI_example_caches.py
@@ -92,7 +92,7 @@
pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
- slave = port)
+ in_port = port)
for i,port in enumerate(dma_ports)
]
@@ -124,7 +124,8 @@
if isa == 'x86':
cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
- cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
+ cpu.interrupts[0].int_responder = \
+ self.sequencers[i].interrupt_out_port
if isa == 'x86' or isa == 'arm':
cpu.itb.walker.port = self.sequencers[i].in_ports
cpu.dtb.walker.port = self.sequencers[i].in_ports
diff --git a/src/boot-exit/configs/system/MOESI_CMP_directory.py b/src/boot-exit/configs/system/MOESI_CMP_directory.py
index 5aa49ba..c30f72c 100755
--- a/src/boot-exit/configs/system/MOESI_CMP_directory.py
+++ b/src/boot-exit/configs/system/MOESI_CMP_directory.py
@@ -92,7 +92,7 @@
pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
- slave = port)
+ in_port = port)
for i,port in enumerate(dma_ports)
]
diff --git a/src/gapbs/configs/system/MESI_Two_Level.py b/src/gapbs/configs/system/MESI_Two_Level.py
index 102ec57..ca542cb 100644
--- a/src/gapbs/configs/system/MESI_Two_Level.py
+++ b/src/gapbs/configs/system/MESI_Two_Level.py
@@ -83,12 +83,12 @@
icache = self.controllers[i].L1Icache,
dcache = self.controllers[i].L1Dcache,
clk_domain = self.controllers[i].clk_domain,
- pio_master_port = iobus.slave,
- mem_master_port = iobus.slave,
- pio_slave_port = iobus.master
+ pio_request_port = iobus.cpu_side_ports,
+ mem_request_port = iobus.cpu_side_ports,
+ pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
- slave = port)
+ in_port = port)
for i,port in enumerate(dma_ports)
]
@@ -110,21 +110,22 @@
# Set up a proxy port for the system_port. Used for load binaries and
# other functional-only things.
self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.slave
- self.sys_port_proxy.pio_master_port = iobus.slave
+ system.system_port = self.sys_port_proxy.in_port
+ self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
# Connect the cpu's cache, interrupt, and TLB ports to Ruby
for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].slave
- cpu.dcache_port = self.sequencers[i].slave
+ cpu.icache_port = self.sequencers[i].in_port
+ cpu.dcache_port = self.sequencers[i].in_port
isa = buildEnv['TARGET_ISA']
if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].master
- cpu.interrupts[0].int_master = self.sequencers[i].slave
- cpu.interrupts[0].int_slave = self.sequencers[i].master
+ cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
+ cpu.interrupts[0].int_requestor = self.sequencers[i].in_port
+ cpu.interrupts[0].int_responder = \
+ self.sequencers[i].interrupt_out_port
if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].slave
- cpu.dtb.walker.port = self.sequencers[i].slave
+ cpu.itb.walker.port = self.sequencers[i].in_port
+ cpu.dtb.walker.port = self.sequencers[i].in_port
class L1Cache(L1Cache_Controller):
@@ -190,18 +191,18 @@
"""
self.mandatoryQueue = MessageBuffer()
self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.master = ruby_system.network.slave
+ self.requestFromL1Cache.out_port = ruby_system.network.in_port
self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.master = ruby_system.network.slave
+ self.responseFromL1Cache.out_port = ruby_system.network.in_port
self.unblockFromL1Cache = MessageBuffer()
- self.unblockFromL1Cache.master = ruby_system.network.slave
+ self.unblockFromL1Cache.out_port = ruby_system.network.in_port
self.optionalQueue = MessageBuffer()
self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.slave = ruby_system.network.master
+ self.requestToL1Cache.in_port = ruby_system.network.out_port
self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.slave = ruby_system.network.master
+ self.responseToL1Cache.in_port = ruby_system.network.out_port
class L2Cache(L2Cache_Controller):
@@ -235,17 +236,17 @@
"""Connect all of the queues for this controller.
"""
self.DirRequestFromL2Cache = MessageBuffer()
- self.DirRequestFromL2Cache.master = ruby_system.network.slave
+ self.DirRequestFromL2Cache.out_port = ruby_system.network.in_port
self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.master = ruby_system.network.slave
+ self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.master = ruby_system.network.slave
+ self.responseFromL2Cache.out_port = ruby_system.network.in_port
self.unblockToL2Cache = MessageBuffer()
- self.unblockToL2Cache.slave = ruby_system.network.master
+ self.unblockToL2Cache.in_port = ruby_system.network.out_port
self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.slave = ruby_system.network.master
+ self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.slave = ruby_system.network.master
+ self.responseToL2Cache.in_port = ruby_system.network.out_port
@@ -273,11 +274,11 @@
def connectQueues(self, ruby_system):
self.requestToDir = MessageBuffer()
- self.requestToDir.slave = ruby_system.network.master
+ self.requestToDir.in_port = ruby_system.network.out_port
self.responseToDir = MessageBuffer()
- self.responseToDir.slave = ruby_system.network.master
+ self.responseToDir.in_port = ruby_system.network.out_port
self.responseFromDir = MessageBuffer()
- self.responseFromDir.master = ruby_system.network.slave
+ self.responseFromDir.out_port = ruby_system.network.in_port
self.requestToMemory = MessageBuffer()
self.responseFromMemory = MessageBuffer()
@@ -298,9 +299,9 @@
def connectQueues(self, ruby_system):
self.mandatoryQueue = MessageBuffer()
self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.slave = ruby_system.network.master
+ self.responseFromDir.in_port = ruby_system.network.out_port
self.requestToDir = MessageBuffer()
- self.requestToDir.master = ruby_system.network.slave
+ self.requestToDir.out_port = ruby_system.network.in_port
class MyNetwork(SimpleNetwork):
diff --git a/src/gapbs/configs/system/MI_example_caches.py b/src/gapbs/configs/system/MI_example_caches.py
index c588e0d..4ea5938 100644
--- a/src/gapbs/configs/system/MI_example_caches.py
+++ b/src/gapbs/configs/system/MI_example_caches.py
@@ -87,12 +87,12 @@
icache = self.controllers[i].cacheMemory,
dcache = self.controllers[i].cacheMemory,
clk_domain = self.controllers[i].clk_domain,
- pio_master_port = iobus.slave,
- mem_master_port = iobus.slave,
- pio_slave_port = iobus.master
+ pio_request_port = iobus.cpu_side_ports,
+ mem_request_port = iobus.cpu_side_ports,
+ pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
- slave = port)
+ in_port = port)
for i,port in enumerate(dma_ports)
]
@@ -113,21 +113,22 @@
# Set up a proxy port for the system_port. Used for load binaries and
# other functional-only things.
self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.slave
- self.sys_port_proxy.pio_master_port = iobus.slave
+ system.system_port = self.sys_port_proxy.in_port
+ self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
# Connect the cpu's cache, interrupt, and TLB ports to Ruby
for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].slave
- cpu.dcache_port = self.sequencers[i].slave
+ cpu.icache_port = self.sequencers[i].in_port
+ cpu.dcache_port = self.sequencers[i].in_port
isa = buildEnv['TARGET_ISA']
if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].master
- cpu.interrupts[0].int_master = self.sequencers[i].slave
- cpu.interrupts[0].int_slave = self.sequencers[i].master
+ cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
+ cpu.interrupts[0].int_requestor = self.sequencers[i].in_port
+ cpu.interrupts[0].int_responder = \
+ self.sequencers[i].interrupt_out_port
if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].slave
- cpu.dtb.walker.port = self.sequencers[i].slave
+ cpu.itb.walker.port = self.sequencers[i].in_port
+ cpu.dtb.walker.port = self.sequencers[i].in_port
class L1Cache(L1Cache_Controller):
@@ -177,13 +178,13 @@
"""
self.mandatoryQueue = MessageBuffer()
self.requestFromCache = MessageBuffer(ordered = True)
- self.requestFromCache.master = ruby_system.network.slave
+ self.requestFromCache.out_port = ruby_system.network.in_port
self.responseFromCache = MessageBuffer(ordered = True)
- self.responseFromCache.master = ruby_system.network.slave
+ self.responseFromCache.out_port = ruby_system.network.in_port
self.forwardToCache = MessageBuffer(ordered = True)
- self.forwardToCache.slave = ruby_system.network.master
+ self.forwardToCache.in_port = ruby_system.network.out_port
self.responseToCache = MessageBuffer(ordered = True)
- self.responseToCache.slave = ruby_system.network.master
+ self.responseToCache.in_port = ruby_system.network.out_port
class DirController(Directory_Controller):
@@ -209,16 +210,16 @@
def connectQueues(self, ruby_system):
self.requestToDir = MessageBuffer(ordered = True)
- self.requestToDir.slave = ruby_system.network.master
+ self.requestToDir.in_port = ruby_system.network.out_port
self.dmaRequestToDir = MessageBuffer(ordered = True)
- self.dmaRequestToDir.slave = ruby_system.network.master
+ self.dmaRequestToDir.in_port = ruby_system.network.out_port
self.responseFromDir = MessageBuffer()
- self.responseFromDir.master = ruby_system.network.slave
+ self.responseFromDir.out_port = ruby_system.network.in_port
self.dmaResponseFromDir = MessageBuffer(ordered = True)
- self.dmaResponseFromDir.master = ruby_system.network.slave
+ self.dmaResponseFromDir.out_port = ruby_system.network.in_port
self.forwardFromDir = MessageBuffer()
- self.forwardFromDir.master = ruby_system.network.slave
+ self.forwardFromDir.out_port = ruby_system.network.in_port
self.requestToMemory = MessageBuffer()
self.responseFromMemory = MessageBuffer()
@@ -239,9 +240,9 @@
def connectQueues(self, ruby_system):
self.mandatoryQueue = MessageBuffer()
self.requestToDir = MessageBuffer()
- self.requestToDir.master = ruby_system.network.slave
+ self.requestToDir.out_port = ruby_system.network.in_port
self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.slave = ruby_system.network.master
+ self.responseFromDir.in_port = ruby_system.network.out_port
class MyNetwork(SimpleNetwork):
diff --git a/src/gapbs/configs/system/caches.py b/src/gapbs/configs/system/caches.py
index 1b4862a..ddc578d 100755
--- a/src/gapbs/configs/system/caches.py
+++ b/src/gapbs/configs/system/caches.py
@@ -69,7 +69,7 @@
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU-side port
@@ -129,13 +129,13 @@
Note: This creates a new crossbar
"""
self.mmubus = L2XBar()
- self.cpu_side = self.mmubus.master
- for tlb in [cpu.itb, cpu.dtb]:
- self.mmubus.slave = tlb.walker.port
+ self.cpu_side = self.mmubus.mem_side_ports
+ cpu.mmu.connectWalkerPorts(
+ self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
class L2Cache(PrefetchCache):
"""Simple L2 Cache with default values"""
@@ -158,10 +158,10 @@
self.size = opts.l2_size
def connectCPUSideBus(self, bus):
- self.cpu_side = bus.master
+ self.cpu_side = bus.mem_side_ports
def connectMemSideBus(self, bus):
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
class L3Cache(Cache):
"""Simple L3 Cache bank with default values
@@ -185,7 +185,7 @@
self.size = ('4MB')
def connectCPUSideBus(self, bus):
- self.cpu_side = bus.master
+ self.cpu_side = bus.mem_side_ports
def connectMemSideBus(self, bus):
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
diff --git a/src/gapbs/configs/system/fs_tools.py b/src/gapbs/configs/system/fs_tools.py
index 22a43d2..5e5e2df 100755
--- a/src/gapbs/configs/system/fs_tools.py
+++ b/src/gapbs/configs/system/fs_tools.py
@@ -33,7 +33,7 @@
def __init__(self, filename):
super(CowDisk, self).__init__()
- self.driveID = 'master'
+ self.driveID = 'device0'
self.image = CowDiskImage(child=RawDiskImage(read_only=True),
read_only=False)
self.image.child.image_file = filename
diff --git a/src/gapbs/configs/system/ruby_system.py b/src/gapbs/configs/system/ruby_system.py
index b642d97..d0afeae 100755
--- a/src/gapbs/configs/system/ruby_system.py
+++ b/src/gapbs/configs/system/ruby_system.py
@@ -78,7 +78,8 @@
self.caches = MESITwoLevelCache()
self.caches.setup(self, self.cpu, self.mem_cntrls,
- [self.pc.south_bridge.ide.dma, self.iobus.master],
+ [self.pc.south_bridge.ide.dma,
+ self.iobus.mem_side_ports],
self.iobus)
if self._host_parallel:
diff --git a/src/gapbs/configs/system/system.py b/src/gapbs/configs/system/system.py
index ba87399..1e82b12 100755
--- a/src/gapbs/configs/system/system.py
+++ b/src/gapbs/configs/system/system.py
@@ -59,7 +59,7 @@
self.membus.default = Self.badaddr_responder.pio
# Set up the system port for functional access from the simulator
- self.system_port = self.membus.slave
+ self.system_port = self.membus.cpu_side_ports
self.initFS(self.membus,num_cpus)
@@ -189,9 +189,9 @@
# For x86 only, connect interrupts to the memory
# Note: these are directly connected to the memory bus and
# not cached
- cpu.interrupts[0].pio = self.membus.master
- cpu.interrupts[0].int_master = self.membus.slave
- cpu.interrupts[0].int_slave = self.membus.master
+ cpu.interrupts[0].pio = self.membus.mem_side_ports
+ cpu.interrupts[0].int_requestor = self.membus.cpu_side_ports
+ cpu.interrupts[0].int_responder = self.membus.mem_side_ports
def createMemoryControllersDDR3(self):
@@ -204,13 +204,13 @@
self.mem_cntrls = [
cls(range = ranges[i],
- port = self.membus.master)
+ port = self.membus.mem_side_ports)
for i in range(num)
] + [kernel_controller]
def _createKernelMemoryController(self, cls):
return cls(range = self.mem_ranges[0],
- port = self.membus.master)
+ port = self.membus.mem_side_ports)
def _getInterleaveRanges(self, rng, num, intlv_low_bit, xor_low_bit):
from math import log
@@ -240,13 +240,13 @@
IO_address_space_base = 0x8000000000000000
pci_config_address_space_base = 0xc000000000000000
interrupts_address_space_base = 0xa000000000000000
- APIC_range_size = 1 << 12;
+ APIC_range_size = 1 << 12
# North Bridge
self.iobus = IOXBar()
self.bridge = Bridge(delay='50ns')
- self.bridge.master = self.iobus.slave
- self.bridge.slave = membus.master
+ self.bridge.mem_side_port = self.iobus.cpu_side_ports
+ self.bridge.cpu_side_port = membus.mem_side_ports
# Allow the bridge to pass through:
# 1) kernel configured PCI device memory map address: address range
# [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
@@ -266,8 +266,8 @@
# Create a bridge from the IO bus to the memory bus to allow access
# to the local APIC (two pages)
self.apicbridge = Bridge(delay='50ns')
- self.apicbridge.slave = self.iobus.master
- self.apicbridge.master = membus.slave
+ self.apicbridge.cpu_side_port = self.iobus.mem_side_ports
+ self.apicbridge.mem_side_port = membus.cpu_side_ports
self.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
interrupts_address_space_base +
cpus * APIC_range_size
@@ -286,8 +286,8 @@
size = '1kB',
tgts_per_mshr = 12,
addr_ranges = self.mem_ranges)
- self.iocache.cpu_side = self.iobus.master
- self.iocache.mem_side = self.membus.slave
+ self.iocache.cpu_side = self.iobus.mem_side_ports
+ self.iocache.mem_side = self.membus.cpu_side_ports
self.intrctrl = IntrControl()
diff --git a/src/npb/configs/system/MESI_Two_Level.py b/src/npb/configs/system/MESI_Two_Level.py
index 1294445..eac0834 100755
--- a/src/npb/configs/system/MESI_Two_Level.py
+++ b/src/npb/configs/system/MESI_Two_Level.py
@@ -88,7 +88,7 @@
pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
- slave = port)
+ in_port = port)
for i,port in enumerate(dma_ports)
]
diff --git a/src/npb/configs/system/MI_example_caches.py b/src/npb/configs/system/MI_example_caches.py
index ca69eab..907c3f0 100755
--- a/src/npb/configs/system/MI_example_caches.py
+++ b/src/npb/configs/system/MI_example_caches.py
@@ -89,7 +89,7 @@
pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
- slave = port)
+ in_port = port)
for i,port in enumerate(dma_ports)
]
diff --git a/src/npb/configs/system/MOESI_CMP_directory.py b/src/npb/configs/system/MOESI_CMP_directory.py
index 5208e73..bf31ab7 100755
--- a/src/npb/configs/system/MOESI_CMP_directory.py
+++ b/src/npb/configs/system/MOESI_CMP_directory.py
@@ -92,7 +92,7 @@
pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
- slave = port)
+ in_port = port)
for i,port in enumerate(dma_ports)
]
diff --git a/src/parsec/configs/system/caches.py b/src/parsec/configs/system/caches.py
index 5d5ca76..f5d3100 100755
--- a/src/parsec/configs/system/caches.py
+++ b/src/parsec/configs/system/caches.py
@@ -72,7 +72,7 @@
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU-side port
@@ -136,13 +136,13 @@
Note: This creates a new crossbar
"""
self.mmubus = L2XBar()
- self.cpu_side = self.mmubus.master
- for tlb in [cpu.itb, cpu.dtb]:
- self.mmubus.slave = tlb.walker.port
+ self.cpu_side = self.mmubus.mem_side_ports
+ cpu.mmu.connectWalkerPorts(
+ self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
class L2Cache(PrefetchCache):
"""Simple L2 Cache with default values"""
@@ -167,10 +167,10 @@
self.size = opts.l2_size
def connectCPUSideBus(self, bus):
- self.cpu_side = bus.master
+ self.cpu_side = bus.mem_side_ports
def connectMemSideBus(self, bus):
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
class L3Cache(Cache):
"""Simple L3 Cache bank with default values
@@ -195,7 +195,7 @@
self.size = (opts.l3_size)
def connectCPUSideBus(self, bus):
- self.cpu_side = bus.master
+ self.cpu_side = bus.mem_side_ports
def connectMemSideBus(self, bus):
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
diff --git a/src/parsec/configs/system/system.py b/src/parsec/configs/system/system.py
index f2a5b4f..5becf46 100644
--- a/src/parsec/configs/system/system.py
+++ b/src/parsec/configs/system/system.py
@@ -68,7 +68,7 @@
self.membus.default = Self.badaddr_responder.pio
# Set up the system port for functional access from the simulator
- self.system_port = self.membus.slave
+ self.system_port = self.membus.cpu_side_ports
self.initFS(self.membus, num_cpus)
@@ -207,9 +207,9 @@
# For x86 only, connect interrupts to the memory
# Note: these are directly connected to the memory bus and
# not cached
- cpu.interrupts[0].pio = self.membus.master
- cpu.interrupts[0].int_master = self.membus.slave
- cpu.interrupts[0].int_slave = self.membus.master
+ cpu.interrupts[0].pio = self.membus.mem_side_ports
+ cpu.interrupts[0].int_requestor = self.membus.cpu_side_ports
+ cpu.interrupts[0].int_responder = self.membus.mem_side_ports
# Memory latency: Using the smaller number from [3]: 96ns
def createMemoryControllersDDR4(self):
@@ -224,7 +224,7 @@
interface.range = ranges[i]
ctrl = MemCtrl()
ctrl.dram = interface
- ctrl.port = self.membus.master
+ ctrl.port = self.membus.mem_side_ports
mem_ctrls.append(ctrl)
self.mem_cntrls = mem_ctrls + [kernel_controller]
@@ -233,7 +233,7 @@
interface.range = self.mem_ranges[0]
ctrl = MemCtrl()
ctrl.dram = interface
- ctrl.port = self.membus.master
+ ctrl.port = self.membus.mem_side_ports
return ctrl
def _getInterleaveRanges(self, rng, num, intlv_low_bit, xor_low_bit):
@@ -268,8 +268,8 @@
# North Bridge
self.iobus = IOXBar()
self.bridge = Bridge(delay='50ns')
- self.bridge.master = self.iobus.slave
- self.bridge.slave = membus.master
+ self.bridge.mem_side_port = self.iobus.cpu_side_ports
+ self.bridge.cpu_side_port = membus.mem_side_ports
# Allow the bridge to pass through:
# 1) kernel configured PCI device memory map address: address range
# [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
@@ -289,8 +289,8 @@
# Create a bridge from the IO bus to the memory bus to allow access
# to the local APIC (two pages)
self.apicbridge = Bridge(delay='50ns')
- self.apicbridge.slave = self.iobus.master
- self.apicbridge.master = membus.slave
+ self.apicbridge.cpu_side_port = self.iobus.mem_side_ports
+ self.apicbridge.mem_side_port = membus.cpu_side_ports
self.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
interrupts_address_space_base +
cpus * APIC_range_size
@@ -309,8 +309,8 @@
size = '1kB',
tgts_per_mshr = 12,
addr_ranges = self.mem_ranges)
- self.iocache.cpu_side = self.iobus.master
- self.iocache.mem_side = self.membus.slave
+ self.iocache.cpu_side = self.iobus.mem_side_ports
+ self.iocache.mem_side = self.membus.cpu_side_ports
self.intrctrl = IntrControl()
diff --git a/src/spec-2006/configs/system/MESI_Two_Level.py b/src/spec-2006/configs/system/MESI_Two_Level.py
index 9b996d1..0513041 100644
--- a/src/spec-2006/configs/system/MESI_Two_Level.py
+++ b/src/spec-2006/configs/system/MESI_Two_Level.py
@@ -91,7 +91,7 @@
pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
- slave = port)
+ in_port = port)
for i,port in enumerate(dma_ports)
]
diff --git a/src/spec-2006/configs/system/MI_example_caches.py b/src/spec-2006/configs/system/MI_example_caches.py
index 0bf2ab3..b8fd7b4 100644
--- a/src/spec-2006/configs/system/MI_example_caches.py
+++ b/src/spec-2006/configs/system/MI_example_caches.py
@@ -92,7 +92,7 @@
pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
- slave = port)
+ in_port = port)
for i,port in enumerate(dma_ports)
]
diff --git a/src/spec-2006/configs/system/MOESI_CMP_directory.py b/src/spec-2006/configs/system/MOESI_CMP_directory.py
index 44e210d..c657df7 100644
--- a/src/spec-2006/configs/system/MOESI_CMP_directory.py
+++ b/src/spec-2006/configs/system/MOESI_CMP_directory.py
@@ -92,7 +92,7 @@
pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
- slave = port)
+ in_port = port)
for i,port in enumerate(dma_ports)
]
diff --git a/src/spec-2017/configs/system/caches.py b/src/spec-2017/configs/system/caches.py
index b884aef..5b273eb 100644
--- a/src/spec-2017/configs/system/caches.py
+++ b/src/spec-2017/configs/system/caches.py
@@ -63,7 +63,7 @@
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU-side port
@@ -115,13 +115,13 @@
Note: This creates a new crossbar
"""
self.mmubus = L2XBar()
- self.cpu_side = self.mmubus.master
- for tlb in [cpu.itb, cpu.dtb]:
- self.mmubus.slave = tlb.walker.port
+ self.cpu_side = self.mmubus.mem_side_ports
+ cpu.mmu.connectWalkerPorts(
+ self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
class L2Cache(PrefetchCache):
"""Simple L2 Cache with default values"""
@@ -140,10 +140,10 @@
super(L2Cache, self).__init__()
def connectCPUSideBus(self, bus):
- self.cpu_side = bus.master
+ self.cpu_side = bus.mem_side_ports
def connectMemSideBus(self, bus):
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
class L3Cache(Cache):
"""Simple L3 Cache bank with default values
@@ -166,8 +166,8 @@
super(L3Cache, self).__init__()
def connectCPUSideBus(self, bus):
- self.cpu_side = bus.master
+ self.cpu_side = bus.mem_side_ports
def connectMemSideBus(self, bus):
- self.mem_side = bus.slave
+ self.mem_side = bus.cpu_side_ports
diff --git a/src/spec-2017/configs/system/fs_tools.py b/src/spec-2017/configs/system/fs_tools.py
index 99102ad..e6421f8 100644
--- a/src/spec-2017/configs/system/fs_tools.py
+++ b/src/spec-2017/configs/system/fs_tools.py
@@ -33,7 +33,7 @@
def __init__(self, filename):
super(CowDisk, self).__init__()
- self.driveID = 'master'
+ self.driveID = 'device0'
self.image = CowDiskImage(child=RawDiskImage(read_only=True),
read_only=False)
self.image.child.image_file = filename
diff --git a/src/spec-2017/configs/system/system.py b/src/spec-2017/configs/system/system.py
index 6b4e79a..1f4642c 100644
--- a/src/spec-2017/configs/system/system.py
+++ b/src/spec-2017/configs/system/system.py
@@ -52,7 +52,7 @@
self.membus.badaddr_responder = BadAddr()
self.membus.default = Self.badaddr_responder.pio
# Set up the system port for functional access from the simulator
- self.system_port = self.membus.slave
+ self.system_port = self.membus.cpu_side_ports
self.initFS(self.membus, num_cpus)
# Replace these paths with the path to your disk images.
# The first disk is the root disk. The second could be used for swap
@@ -148,9 +148,9 @@
# For x86 only, connect interrupts to the memory
# Note: these are directly connected to the memory bus and
# not cached
- cpu.interrupts[0].pio = self.membus.master
- cpu.interrupts[0].int_master = self.membus.slave
- cpu.interrupts[0].int_slave = self.membus.master
+ cpu.interrupts[0].pio = self.membus.mem_side_ports
+ cpu.interrupts[0].int_requestor = self.membus.cpu_side_ports
+ cpu.interrupts[0].int_responder = self.membus.mem_side_ports
# Memory latency: Using the smaller number from [3]: 96ns
def createMemoryControllersDDR4(self):
self._createMemoryControllers(8, DDR4_2400_16x4)
@@ -159,12 +159,12 @@
ranges = self._getInterleaveRanges(self.mem_ranges[-1], num, 7, 20)
self.mem_cntrls = [
cls(range = ranges[i],
- port = self.membus.master)
+ port = self.membus.mem_side_ports)
for i in range(num)
] + [kernel_controller]
def _createKernelMemoryController(self, cls):
return cls(range = self.mem_ranges[0],
- port = self.membus.master)
+ port = self.membus.mem_side_ports)
def _getInterleaveRanges(self, rng, num, intlv_low_bit, xor_low_bit):
from math import log
bits = int(log(num, 2))
@@ -192,8 +192,8 @@
# North Bridge
self.iobus = IOXBar()
self.bridge = Bridge(delay='50ns')
- self.bridge.master = self.iobus.slave
- self.bridge.slave = membus.master
+ self.bridge.mem_side_port = self.iobus.cpu_side_ports
+ self.bridge.cpu_side_port = membus.mem_side_ports
# Allow the bridge to pass through:
# 1) kernel configured PCI device memory map address: address range
# [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
@@ -212,8 +212,8 @@
# Create a bridge from the IO bus to the memory bus to allow access
# to the local APIC (two pages)
self.apicbridge = Bridge(delay='50ns')
- self.apicbridge.slave = self.iobus.master
- self.apicbridge.master = membus.slave
+ self.apicbridge.cpu_side_port = self.iobus.mem_side_ports
+ self.apicbridge.mem_side_port = membus.cpu_side_ports
self.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
interrupts_address_space_base +
cpus * APIC_range_size
@@ -230,8 +230,8 @@
size = '1kB',
tgts_per_mshr = 12,
addr_ranges = self.mem_ranges)
- self.iocache.cpu_side = self.iobus.master
- self.iocache.mem_side = self.membus.slave
+ self.iocache.cpu_side = self.iobus.mem_side_ports
+ self.iocache.mem_side = self.membus.cpu_side_ports
self.intrctrl = IntrControl()
###############################################
# Add in a Bios information structure.
