resources: Update the way of connecting MMUCache and XBar ports
Update the gem5 configs to accommodate this change,
https://gem5-review.googlesource.com/c/public/gem5/+/34976
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I91df4a815e1f0fa7e6610dec4c8544555c777225
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/37217
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>
diff --git a/src/boot-exit/configs/system/caches.py b/src/boot-exit/configs/system/caches.py
index 813c6b5..9679d9e 100755
--- a/src/boot-exit/configs/system/caches.py
+++ b/src/boot-exit/configs/system/caches.py
@@ -117,8 +117,8 @@
"""
self.mmubus = L2XBar()
self.cpu_side = self.mmubus.mem_side_ports
- for tlb in [cpu.itb, cpu.dtb]:
- self.mmubus.cpu_side_ports = tlb.walker.port
+ cpu.mmu.connectWalkerPorts(
+ self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
diff --git a/src/gapbs/configs/system/caches.py b/src/gapbs/configs/system/caches.py
index 1b4862a..1bb9056 100755
--- a/src/gapbs/configs/system/caches.py
+++ b/src/gapbs/configs/system/caches.py
@@ -130,8 +130,8 @@
"""
self.mmubus = L2XBar()
self.cpu_side = self.mmubus.master
- for tlb in [cpu.itb, cpu.dtb]:
- self.mmubus.slave = tlb.walker.port
+ cpu.mmu.connectWalkerPorts(
+ self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
diff --git a/src/npb/configs/system/caches.py b/src/npb/configs/system/caches.py
index 0f03238..3751926 100755
--- a/src/npb/configs/system/caches.py
+++ b/src/npb/configs/system/caches.py
@@ -138,8 +138,8 @@
"""
self.mmubus = L2XBar()
self.cpu_side = self.mmubus.mem_side_ports
- for tlb in [cpu.itb, cpu.dtb]:
- self.mmubus.cpu_side_ports = tlb.walker.port
+ cpu.mmu.connectWalkerPorts(
+ self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
diff --git a/src/parsec/configs/system/caches.py b/src/parsec/configs/system/caches.py
index 5d5ca76..0a43c81 100755
--- a/src/parsec/configs/system/caches.py
+++ b/src/parsec/configs/system/caches.py
@@ -137,8 +137,8 @@
"""
self.mmubus = L2XBar()
self.cpu_side = self.mmubus.master
- for tlb in [cpu.itb, cpu.dtb]:
- self.mmubus.slave = tlb.walker.port
+ cpu.mmu.connectWalkerPorts(
+ self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
diff --git a/src/spec-2006/configs/system/caches.py b/src/spec-2006/configs/system/caches.py
index b884aef..dd604ac 100644
--- a/src/spec-2006/configs/system/caches.py
+++ b/src/spec-2006/configs/system/caches.py
@@ -115,9 +115,9 @@
Note: This creates a new crossbar
"""
self.mmubus = L2XBar()
- self.cpu_side = self.mmubus.master
- for tlb in [cpu.itb, cpu.dtb]:
- self.mmubus.slave = tlb.walker.port
+ self.cpu_side = self.mmubus.mem_side_ports
+ cpu.mmu.connectWalkerPorts(
+ self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
diff --git a/src/spec-2017/configs/system/caches.py b/src/spec-2017/configs/system/caches.py
index b884aef..5eb3d77 100644
--- a/src/spec-2017/configs/system/caches.py
+++ b/src/spec-2017/configs/system/caches.py
@@ -116,8 +116,8 @@
"""
self.mmubus = L2XBar()
self.cpu_side = self.mmubus.master
- for tlb in [cpu.itb, cpu.dtb]:
- self.mmubus.slave = tlb.walker.port
+ cpu.mmu.connectWalkerPorts(
+ self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
