resources: Update the way of connecting MMUCache and Sequencers for boot-exit
Update the gem5 configs of boot-exit to accommodate this change,
https://gem5-review.googlesource.com/c/public/gem5/+/34976
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I9cfa6e5164478cfe90a773e9bbc4b1c7e509432a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/38377
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Jason Lowe-Power <power.jg@gmail.com>
diff --git a/src/boot-exit/configs/system/MESI_Two_Level.py b/src/boot-exit/configs/system/MESI_Two_Level.py
index ec19ce2..52f0ae5 100755
--- a/src/boot-exit/configs/system/MESI_Two_Level.py
+++ b/src/boot-exit/configs/system/MESI_Two_Level.py
@@ -127,8 +127,8 @@
cpu.interrupts[0].int_responder = \
self.sequencers[i].interrupt_out_port
if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].in_ports
- cpu.dtb.walker.port = self.sequencers[i].in_ports
+ cpu.mmu.connectWalkerPorts(
+ self.sequencers[i].in_ports, self.sequencers[i].in_ports)
class L1Cache(L1Cache_Controller):
diff --git a/src/boot-exit/configs/system/MI_example_caches.py b/src/boot-exit/configs/system/MI_example_caches.py
index d104ebc..0f532ee 100755
--- a/src/boot-exit/configs/system/MI_example_caches.py
+++ b/src/boot-exit/configs/system/MI_example_caches.py
@@ -127,9 +127,8 @@
cpu.interrupts[0].int_responder = \
self.sequencers[i].interrupt_out_port
if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].in_ports
- cpu.dtb.walker.port = self.sequencers[i].in_ports
-
+ cpu.mmu.connectWalkerPorts(
+ self.sequencers[i].in_ports, self.sequencers[i].in_ports)
class L1Cache(L1Cache_Controller):
diff --git a/src/boot-exit/configs/system/MOESI_CMP_directory.py b/src/boot-exit/configs/system/MOESI_CMP_directory.py
index c30f72c..e23b8f6 100755
--- a/src/boot-exit/configs/system/MOESI_CMP_directory.py
+++ b/src/boot-exit/configs/system/MOESI_CMP_directory.py
@@ -127,9 +127,8 @@
cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
cpu.interrupts[0].int_responder = self.sequencers[i].interrupt_out_port
if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].in_ports
- cpu.dtb.walker.port = self.sequencers[i].in_ports
-
+ cpu.mmu.connectWalkerPorts(
+ self.sequencers[i].in_ports, self.sequencers[i].in_ports)
class L1Cache(L1Cache_Controller):
