commit d6234513a3a3a94b72d68311858d7b89a22ef0af
author Hoa Nguyen <hoanguyen@ucdavis.edu> Fri Mar 12 00:02:47 2021 -0800
committer Hoa Nguyen <hoanguyen@ucdavis.edu> Sun Mar 14 07:56:17 2021 +0000
tree 1e2dc115c45c5cd5e352d3a848f6199f315297e8
parent 9c86c417c7cc3575895c4dd8010964ce97b026f3

resources: Fix boot-exit configs

This change is a collection of bug fixes patching the following bugs,
- `in_port` typos while calling DMASequencer constructor, should be
`in_ports`
- Missing `triggerQueue` initialization for DirController of
MOESI_CMP_directory config.

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: Icc252fad7c6699ed0e3e5511f203de93d09300e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/42843
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Jason Lowe-Power <power.jg@gmail.com>

src/boot-exit/configs/system/MESI_Two_Level.py

diff --git a/src/boot-exit/configs/system/MESI_Two_Level.py b/src/boot-exit/configs/system/MESI_Two_Level.py
index 629e288..136ad31 100755
--- a/src/boot-exit/configs/system/MESI_Two_Level.py
+++ b/src/boot-exit/configs/system/MESI_Two_Level.py
@@ -90,7 +90,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]
 

src/boot-exit/configs/system/MI_example_caches.py

diff --git a/src/boot-exit/configs/system/MI_example_caches.py b/src/boot-exit/configs/system/MI_example_caches.py
index 84bcab5..758c291 100755
--- a/src/boot-exit/configs/system/MI_example_caches.py
+++ b/src/boot-exit/configs/system/MI_example_caches.py
@@ -91,7 +91,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]
 

src/boot-exit/configs/system/MOESI_CMP_directory.py

diff --git a/src/boot-exit/configs/system/MOESI_CMP_directory.py b/src/boot-exit/configs/system/MOESI_CMP_directory.py
index 7dc034a..60ce7c2 100755
--- a/src/boot-exit/configs/system/MOESI_CMP_directory.py
+++ b/src/boot-exit/configs/system/MOESI_CMP_directory.py
@@ -91,7 +91,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]
 
@@ -287,6 +287,7 @@
         self.forwardFromDir.out_port = ruby_system.network.in_port
         self.requestToMemory = MessageBuffer()
         self.responseFromMemory = MessageBuffer()
+        self.triggerQueue = MessageBuffer(ordered = True)
 
 class DMAController(DMA_Controller):