resources: Update memory terminology of gem5 configs of parsec
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: Ia95d8a493efbfe2f83920d0c4de47a7a1ebb435a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/38395
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>
diff --git a/src/parsec/configs-mesi-two-level/system/MESI_Two_Level.py b/src/parsec/configs-mesi-two-level/system/MESI_Two_Level.py
index f763727..14b46b2 100644
--- a/src/parsec/configs-mesi-two-level/system/MESI_Two_Level.py
+++ b/src/parsec/configs-mesi-two-level/system/MESI_Two_Level.py
@@ -83,12 +83,12 @@
icache = self.controllers[i].L1Icache,
dcache = self.controllers[i].L1Dcache,
clk_domain = self.controllers[i].clk_domain,
- pio_master_port = iobus.slave,
- mem_master_port = iobus.slave,
- pio_slave_port = iobus.master
+ pio_request_port = iobus.cpu_side_ports,
+ mem_request_port = iobus.cpu_side_ports,
+ pio_response_port = iobus.mem_side_ports
) for i in range(len(cpus))] + \
[DMASequencer(version = i,
- slave = port)
+ in_ports = port)
for i,port in enumerate(dma_ports)
]
@@ -110,22 +110,23 @@
# Set up a proxy port for the system_port. Used for load binaries and
# other functional-only things.
self.sys_port_proxy = RubyPortProxy()
- system.system_port = self.sys_port_proxy.slave
- self.sys_port_proxy.pio_master_port = iobus.slave
+ system.system_port = self.sys_port_proxy.in_ports
+ self.sys_port_proxy.pio_request_port = iobus.cpu_side_ports
# Connect the cpu's cache, interrupt, and TLB ports to Ruby
for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].slave
- cpu.dcache_port = self.sequencers[i].slave
+ cpu.icache_port = self.sequencers[i].in_ports
+ cpu.dcache_port = self.sequencers[i].in_ports
cpu.createInterruptController()
isa = buildEnv['TARGET_ISA']
if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].master
- cpu.interrupts[0].int_master = self.sequencers[i].slave
- cpu.interrupts[0].int_slave = self.sequencers[i].master
+ cpu.interrupts[0].pio = self.sequencers[i].interrupt_out_port
+ cpu.interrupts[0].int_requestor = self.sequencers[i].in_ports
+ cpu.interrupts[0].int_responder = \
+ self.sequencers[i].interrupt_out_port
if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].slave
- cpu.dtb.walker.port = self.sequencers[i].slave
+ cpu.itb.walker.port = self.sequencers[i].in_ports
+ cpu.dtb.walker.port = self.sequencers[i].in_ports
class L1Cache(L1Cache_Controller):
@@ -191,18 +192,18 @@
"""
self.mandatoryQueue = MessageBuffer()
self.requestFromL1Cache = MessageBuffer()
- self.requestFromL1Cache.master = ruby_system.network.slave
+ self.requestFromL1Cache.out_port = ruby_system.network.in_port
self.responseFromL1Cache = MessageBuffer()
- self.responseFromL1Cache.master = ruby_system.network.slave
+ self.responseFromL1Cache.out_port = ruby_system.network.in_port
self.unblockFromL1Cache = MessageBuffer()
- self.unblockFromL1Cache.master = ruby_system.network.slave
+ self.unblockFromL1Cache.out_port = ruby_system.network.in_port
self.optionalQueue = MessageBuffer()
self.requestToL1Cache = MessageBuffer()
- self.requestToL1Cache.slave = ruby_system.network.master
+ self.requestToL1Cache.in_port = ruby_system.network.out_port
self.responseToL1Cache = MessageBuffer()
- self.responseToL1Cache.slave = ruby_system.network.master
+ self.responseToL1Cache.in_port = ruby_system.network.out_port
class L2Cache(L2Cache_Controller):
@@ -236,17 +237,17 @@
"""Connect all of the queues for this controller.
"""
self.DirRequestFromL2Cache = MessageBuffer()
- self.DirRequestFromL2Cache.master = ruby_system.network.slave
+ self.DirRequestFromL2Cache.out_port = ruby_system.network.in_port
self.L1RequestFromL2Cache = MessageBuffer()
- self.L1RequestFromL2Cache.master = ruby_system.network.slave
+ self.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
self.responseFromL2Cache = MessageBuffer()
- self.responseFromL2Cache.master = ruby_system.network.slave
+ self.responseFromL2Cache.out_port = ruby_system.network.in_port
self.unblockToL2Cache = MessageBuffer()
- self.unblockToL2Cache.slave = ruby_system.network.master
+ self.unblockToL2Cache.in_port = ruby_system.network.out_port
self.L1RequestToL2Cache = MessageBuffer()
- self.L1RequestToL2Cache.slave = ruby_system.network.master
+ self.L1RequestToL2Cache.in_port = ruby_system.network.out_port
self.responseToL2Cache = MessageBuffer()
- self.responseToL2Cache.slave = ruby_system.network.master
+ self.responseToL2Cache.in_port = ruby_system.network.out_port
@@ -274,11 +275,11 @@
def connectQueues(self, ruby_system):
self.requestToDir = MessageBuffer()
- self.requestToDir.slave = ruby_system.network.master
+ self.requestToDir.in_port = ruby_system.network.out_port
self.responseToDir = MessageBuffer()
- self.responseToDir.slave = ruby_system.network.master
+ self.responseToDir.in_port = ruby_system.network.out_port
self.responseFromDir = MessageBuffer()
- self.responseFromDir.master = ruby_system.network.slave
+ self.responseFromDir.out_port = ruby_system.network.in_port
self.requestToMemory = MessageBuffer()
self.responseFromMemory = MessageBuffer()
@@ -299,9 +300,9 @@
def connectQueues(self, ruby_system):
self.mandatoryQueue = MessageBuffer()
self.responseFromDir = MessageBuffer(ordered = True)
- self.responseFromDir.slave = ruby_system.network.master
+ self.responseFromDir.in_port = ruby_system.network.out_port
self.requestToDir = MessageBuffer()
- self.requestToDir.master = ruby_system.network.slave
+ self.requestToDir.out_port = ruby_system.network.in_port
class MyNetwork(SimpleNetwork):
diff --git a/src/parsec/configs-mesi-two-level/system/ruby_system.py b/src/parsec/configs-mesi-two-level/system/ruby_system.py
index cea2c2a..d0adcc7 100755
--- a/src/parsec/configs-mesi-two-level/system/ruby_system.py
+++ b/src/parsec/configs-mesi-two-level/system/ruby_system.py
@@ -75,7 +75,8 @@
self.caches = MESITwoLevelCache()
self.caches.setup(self, self.cpu, self.mem_cntrls,
- [self.pc.south_bridge.ide.dma, self.iobus.master],
+ [self.pc.south_bridge.ide.dma,
+ self.iobus.mem_side_ports],
self.iobus)
if self._host_parallel:
