| commit | e41c71a1354e43cfccd7fb0fa165b78b8ae535b4 | [log] [tgz] |
|---|---|---|
| author | Hoa Nguyen <hoanguyen@ucdavis.edu> | Wed Dec 09 02:48:12 2020 -0800 |
| committer | Hoa Nguyen <hoanguyen@ucdavis.edu> | Tue Dec 22 02:42:59 2020 +0000 |
| tree | 613563509a9855f6b61aaa86fab555d24457f665 | |
| parent | ab191ce0efb2884512f90959bd13d28cd7023282 [diff] |
resources: Update the way of connecting MMUCache and Sequencers for gapbs Update the gem5 configs of gapbs to accommodate this change, https://gem5-review.googlesource.com/c/public/gem5/+/34976 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Change-Id: Ibfa91d3298b2bad57fad7eb7931dba8621f6d6eb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/38438 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: Jason Lowe-Power <power.jg@gmail.com>
diff --git a/src/gapbs/configs/system/MESI_Two_Level.py b/src/gapbs/configs/system/MESI_Two_Level.py index ca542cb..dec9e10 100644 --- a/src/gapbs/configs/system/MESI_Two_Level.py +++ b/src/gapbs/configs/system/MESI_Two_Level.py
@@ -124,9 +124,8 @@ cpu.interrupts[0].int_responder = \ self.sequencers[i].interrupt_out_port if isa == 'x86' or isa == 'arm': - cpu.itb.walker.port = self.sequencers[i].in_port - cpu.dtb.walker.port = self.sequencers[i].in_port - + cpu.mmu.connectWalkerPorts( + self.sequencers[i].in_ports, self.sequencers[i].in_ports) class L1Cache(L1Cache_Controller):
diff --git a/src/gapbs/configs/system/MI_example_caches.py b/src/gapbs/configs/system/MI_example_caches.py index 4ea5938..8f16590 100644 --- a/src/gapbs/configs/system/MI_example_caches.py +++ b/src/gapbs/configs/system/MI_example_caches.py
@@ -127,9 +127,8 @@ cpu.interrupts[0].int_responder = \ self.sequencers[i].interrupt_out_port if isa == 'x86' or isa == 'arm': - cpu.itb.walker.port = self.sequencers[i].in_port - cpu.dtb.walker.port = self.sequencers[i].in_port - + cpu.mmu.connectWalkerPorts( + self.sequencers[i].in_ports, self.sequencers[i].in_ports) class L1Cache(L1Cache_Controller):