resources: Revert mmuCache change in parsec configs
The MMU change of gem5 won't be merged to stable until the next
version of gem5.
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I0f1a2ab585dc09ca1b375d566058f906861fe2f1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/39595
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Jason Lowe-Power <power.jg@gmail.com>
diff --git a/src/parsec/configs/system/caches.py b/src/parsec/configs/system/caches.py
index f5d3100..15c9b14 100755
--- a/src/parsec/configs/system/caches.py
+++ b/src/parsec/configs/system/caches.py
@@ -137,8 +137,8 @@
"""
self.mmubus = L2XBar()
self.cpu_side = self.mmubus.mem_side_ports
- cpu.mmu.connectWalkerPorts(
- self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
+ for tlb in [cpu.itb, cpu.dtb]:
+ self.mmubus.cpu_side_ports = tlb.walker.port
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
