arch-riscv: Fix Clint and SATP write side effects

Previously, RISC-V FS support was unable to support O3CPU.
It was due to two issues:

1. CLINT was calling tc->setMiscRegNoEffect which triggers
a conditionalSquash on O3CPU. These frequent squashes led
to assertion error in src/cpu/o3/inst_queue_impl.hh line
1293 (we still suspect that the assertion might contain
some assumptions).

2. A CSR write to SATP needs to trigger a squash (since
MMU can be activated). This is done by conditionally
adding the IsSquashAfter flag to CSR operations if the
target is SATP. This is a simple fix. (Else, an auipc
right after a CSR write to SATP might compute the wrong
value). In the future, a better implementation should
only set the flag for writes to the relevant bit(s).

Change-Id: Ieb9fd0b9aa09e4d2f270b28c2297ea821a81bf65
Maintainer: Bobby R. Bruce <>
Tested-by: kokoro <>
Reviewed-by: Ayaz Akram <>
Reviewed-by: Peter Yuen <>
3 files changed