commit 451cb4cb7a94d1bd20a082d0cdfbb2460ac7990c
author Peter <petery.hin@huawei.com> Thu Mar 18 16:43:15 2021 +0800
committer Peter Yuen <petery.hin@huawei.com> Wed Mar 24 02:48:14 2021 +0000
tree 3d3676874e142a53d4e18dea4b3f17b080cc8a1d
parent 39108150ab041033b3317acc8fbb8bdfabfe3254

arch-riscv: Fix Clint and SATP write side effects

Previously, RISC-V FS support was unable to support O3CPU.
It was due to two issues:

1. CLINT was calling tc->setMiscRegNoEffect which triggers
a conditionalSquash on O3CPU. These frequent squashes led
to assertion error in src/cpu/o3/inst_queue_impl.hh line
1293 (we still suspect that the assertion might contain
some assumptions).

2. A CSR write to SATP needs to trigger a squash (since
MMU can be activated). This is done by conditionally
adding the IsSquashAfter flag to CSR operations if the
target is SATP. This is a simple fix. (Else, an auipc
right after a CSR write to SATP might compute the wrong
value). In the future, a better implementation should
only set the flag for writes to the relevant bit(s).

Change-Id: Ieb9fd0b9aa09e4d2f270b28c2297ea821a81bf65
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43244
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Peter Yuen <petery.hin@huawei.com>

src/arch/riscv/insts/standard.hh

diff --git a/src/arch/riscv/insts/standard.hh b/src/arch/riscv/insts/standard.hh
index aa94942..709c944 100644
--- a/src/arch/riscv/insts/standard.hh
+++ b/src/arch/riscv/insts/standard.hh
@@ -92,7 +92,11 @@
     CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
         : RiscvStaticInst(mnem, _machInst, __opClass),
             csr(FUNCT12), uimm(CSRIMM)
-    {}
+    {
+        if (csr == CSR_SATP) {
+            flags[IsSquashAfter] = true;
+        }
+    }
 
     std::string generateDisassembly(
         Addr pc, const Loader::SymbolTable *symtab) const override;

src/arch/riscv/pma_checker.cc

diff --git a/src/arch/riscv/pma_checker.cc b/src/arch/riscv/pma_checker.cc
index d36dc1d..15c5cf9 100644
--- a/src/arch/riscv/pma_checker.cc
+++ b/src/arch/riscv/pma_checker.cc
@@ -54,7 +54,7 @@
 PMAChecker::check(const RequestPtr &req)
 {
     if (isUncacheable(req->getPaddr(), req->getSize())) {
-        req->setFlags(Request::UNCACHEABLE);
+        req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
     }
 }
 

src/dev/riscv/clint.cc

diff --git a/src/dev/riscv/clint.cc b/src/dev/riscv/clint.cc
index 641ba6f..ced9122 100644
--- a/src/dev/riscv/clint.cc
+++ b/src/dev/riscv/clint.cc
@@ -64,7 +64,9 @@
     for (int context_id = 0; context_id < nThread; context_id++) {
 
         // Update misc reg file
-        system->threads[context_id]->setMiscRegNoEffect(MISCREG_TIME, mtime);
+        ISA* isa = dynamic_cast<ISA*>(
+            system->threads[context_id]->getIsaPtr());
+        isa->setMiscRegNoEffect(MISCREG_TIME, mtime);
 
         // Post timer interrupt
         uint64_t mtimecmp = registers.mtimecmp[context_id].get();