src/dev/amdgpu/hwreg_defines.hh

/*
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#ifndef __DEV_GPU_HWREG_DEFINES_H__
#define __DEV_GPU_HWREG_DEFINES_H__
/*
 * This enum is adapted from the offsets seen by LLVM:
 *
 * https://github.com/llvm/llvm-project/blob/release/14.x/llvm/lib/
 *         Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp#L58
 */

namespace gem5
{

/*
 * Further descriptions can be found in the "Hardware Register Values" table
 * in any of the GCN3, Vega, CDNA1, CNDA2, or RDNA ISA manuals.
 */
enum amdgpu_hwreg
{
    HW_REG_MODE = 0x1,
    HW_REG_STATUS = 0x2,
    HW_REG_TRAPSTS = 0x3,
    HW_REG_HW_ID = 0x4,
    HW_REG_GPR_ALLOC = 0x5,
    HW_REG_LDS_ALLOC = 0x6,
    HW_REG_IB_STS = 0x7,
    HW_REG_SH_MEM_BASES = 0xf,
    HW_REG_TBA_LO = 0x10,
    HW_REG_TBA_HI = 0x11,
    HW_REG_TMA_LO = 0x12,
    HW_REG_TMA_HI = 0x13,
    HW_REG_FLAT_SCR_LO = 0x14,
    HW_REG_FLAT_SCR_HI = 0x15,
    HW_REG_XNACK_MASK = 0x16,
    HW_REG_HW_ID1 = 0x17,
    HW_REG_HW_ID2 = 0x18,
    HW_REG_POPS_PACKER = 0x19,
    HW_REG_SHADER_CYCLES = 0x1d,
};

} // namespace gem5

#endif // __DEV_GPU_HWREG_DEFINES_H__