misc: Merge branch 'release-staging-v20.1.0.0' into develop
Change-Id: I8c3277af7903f0b055b26e497139455a03678524
diff --git a/MAINTAINERS b/MAINTAINERS
index 92c4ce8..d248ec1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -68,6 +68,7 @@
gpu-compute:
Tony Gutierrez <anthony.gutierrez@amd.com>
+ Matt Poremba <matthew.poremba@amd.com>
learning-gem5: The code and configs for the Learning gem5 book (see
learning.gem5.com)
diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc
index 0ddda95..a12c330 100644
--- a/src/arch/arm/insts/mem64.cc
+++ b/src/arch/arm/insts/mem64.cc
@@ -79,7 +79,6 @@
else
memAccessFlags |= ArmISA::TLB::AllowUnaligned;
if (acrel) {
- flags[IsMemBarrier] = true;
flags[IsWriteBarrier] = true;
flags[IsReadBarrier] = true;
}
diff --git a/src/arch/arm/insts/tme64.cc b/src/arch/arm/insts/tme64.cc
index 30aff20..3629d34 100644
--- a/src/arch/arm/insts/tme64.cc
+++ b/src/arch/arm/insts/tme64.cc
@@ -83,7 +83,6 @@
_numVecElemDestRegs = 0;
_numIntDestRegs = 0;
_numCCDestRegs = 0;
- flags[IsMemBarrier] = true;
flags[IsMicroop] = true;
flags[IsReadBarrier] = true;
flags[IsWriteBarrier] = true;
@@ -129,7 +128,6 @@
flags[IsHtmStart] = true;
flags[IsInteger] = true;
flags[IsLoad] = true;
- flags[IsMemRef] = true;
flags[IsMicroop] = true;
flags[IsNonSpeculative] = true;
}
@@ -170,7 +168,6 @@
_numIntDestRegs = 0;
_numCCDestRegs = 0;
flags[IsLoad] = true;
- flags[IsMemRef] = true;
flags[IsMicroop] = true;
flags[IsNonSpeculative] = true;
flags[IsHtmCancel] = true;
@@ -213,7 +210,6 @@
_numCCDestRegs = 0;
flags[IsHtmStop] = true;
flags[IsLoad] = true;
- flags[IsMemRef] = true;
flags[IsMicroop] = true;
flags[IsNonSpeculative] = true;
}
diff --git a/src/arch/arm/isa/insts/amo64.isa b/src/arch/arm/isa/insts/amo64.isa
index 1fe9b7a..51e1f38 100644
--- a/src/arch/arm/isa/insts/amo64.isa
+++ b/src/arch/arm/isa/insts/amo64.isa
@@ -91,7 +91,7 @@
self.instFlags.append("IsMicroop")
if self.flavor in ("release", "acquire_release", "acquire"):
- self.instFlags.append("IsMemBarrier")
+ self.instFlags.extend(["IsReadBarrier", "IsWriteBarrier"])
if self.flavor in ("release", "acquire_release"):
self.instFlags.append("IsWriteBarrier")
if self.flavor in ("acquire_release", "acquire"):
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa
index d5a5869..fb89688 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -392,7 +392,7 @@
"use_uops" : 0,
"op_wb" : ";",
"fa_code" : ";"},
- ['IsStore', 'IsMemRef']);
+ ['IsStore']);
header_output += DCStore64Declare.subst(msrDCZVAIop);
decoder_output += DCStore64Constructor.subst(msrDCZVAIop);
exec_output += DCStore64Execute.subst(msrDCZVAIop);
@@ -423,7 +423,7 @@
"use_uops" : 0,
"op_wb" : ";",
"fa_code" : cachem_fa},
- ['IsStore', 'IsMemRef']);
+ ['IsStore']);
header_output += DCStore64Declare.subst(msrDCCVAUIop);
decoder_output += DCStore64Constructor.subst(msrDCCVAUIop);
exec_output += DCStore64Execute.subst(msrDCCVAUIop);
@@ -447,7 +447,7 @@
"use_uops" : 0,
"op_wb" : ";",
"fa_code" : cachem_fa},
- ['IsStore', 'IsMemRef']);
+ ['IsStore']);
header_output += DCStore64Declare.subst(msrDCCVACIop);
decoder_output += DCStore64Constructor.subst(msrDCCVACIop);
exec_output += DCStore64Execute.subst(msrDCCVACIop);
@@ -472,7 +472,7 @@
"use_uops" : 0,
"op_wb" : ";",
"fa_code" : cachem_fa},
- ['IsStore', 'IsMemRef']);
+ ['IsStore']);
header_output += DCStore64Declare.subst(msrDCCIVACIop);
decoder_output += DCStore64Constructor.subst(msrDCCIVACIop);
exec_output += DCStore64Execute.subst(msrDCCIVACIop);
@@ -503,7 +503,7 @@
"use_uops" : 0,
"op_wb" : ";",
"fa_code" : cachem_fa},
- ['IsStore', 'IsMemRef']);
+ ['IsStore']);
header_output += DCStore64Declare.subst(msrDCIVACIop);
decoder_output += DCStore64Constructor.subst(msrDCIVACIop);
exec_output += DCStore64Execute.subst(msrDCIVACIop);
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index d7e27a4..3be0e3e 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -179,9 +179,7 @@
self.memFlags.append("Request::LLSC")
if self.flavor in ("acquire", "acex"):
- self.instFlags.extend(["IsMemBarrier",
- "IsWriteBarrier",
- "IsReadBarrier"])
+ self.instFlags.extend(["IsWriteBarrier", "IsReadBarrier"])
self.memFlags.append("Request::ACQUIRE")
# Disambiguate the class name for different flavors of loads
@@ -260,9 +258,7 @@
self.Name = "%s_%s" % (self.name.upper(), self.Name)
if self.flavor in ("acquire", "acex"):
- self.instFlags.extend(["IsMemBarrier",
- "IsWriteBarrier",
- "IsReadBarrier"])
+ self.instFlags.extend(["IsWriteBarrier", "IsReadBarrier"])
self.memFlags.append("Request::ACQUIRE")
def emit(self):
diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa
index 51f5389..1ce34cd 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -91,9 +91,7 @@
self.memFlags.append("ArmISA::TLB::AllowUnaligned")
if self.flavor in ("acquire", "acex", "acexp"):
- self.instFlags.extend(["IsMemBarrier",
- "IsWriteBarrier",
- "IsReadBarrier"])
+ self.instFlags.extend(["IsWriteBarrier", "IsReadBarrier"])
self.memFlags.append("Request::ACQUIRE")
if self.flavor in ("acex", "exclusive", "exp", "acexp"):
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 1b9cdf7..ad0f677 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -252,7 +252,7 @@
'memacc_code' : loadMemAccCode,
'ea_code' : simdEnabledCheckCode + eaCode,
'predicate_test' : predicateTest },
- [ 'IsMicroop', 'IsMemRef', 'IsLoad' ])
+ [ 'IsMicroop', 'IsLoad' ])
storeIop = InstObjParams('strneon%(size)d_uop' % subst,
'MicroStrNeon%(size)dUop' % subst,
'MicroNeonMemOp',
@@ -261,7 +261,7 @@
'memacc_code' : storeMemAccCode,
'ea_code' : simdEnabledCheckCode + eaCode,
'predicate_test' : predicateTest },
- [ 'IsMicroop', 'IsMemRef', 'IsStore' ])
+ [ 'IsMicroop', 'IsStore' ])
exec_output += NeonLoadExecute.subst(loadIop) + \
NeonLoadInitiateAcc.subst(loadIop) + \
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 6a9b048..17c30ff 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -1149,7 +1149,7 @@
"postacc_code": "",
"ea_code": McrDcimvacCode,
"predicate_test": predicateTest},
- ['IsMemRef', 'IsStore'])
+ ['IsStore'])
header_output += MiscRegRegImmMemOpDeclare.subst(McrDcimvacIop)
decoder_output += MiscRegRegImmOpConstructor.subst(McrDcimvacIop)
exec_output += Mcr15Execute.subst(McrDcimvacIop) + \
@@ -1167,7 +1167,7 @@
"postacc_code": "",
"ea_code": McrDccmvacCode,
"predicate_test": predicateTest},
- ['IsMemRef', 'IsStore'])
+ ['IsStore'])
header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvacIop)
decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvacIop)
exec_output += Mcr15Execute.subst(McrDccmvacIop) + \
@@ -1185,7 +1185,7 @@
"postacc_code": "",
"ea_code": McrDccmvauCode,
"predicate_test": predicateTest},
- ['IsMemRef', 'IsStore'])
+ ['IsStore'])
header_output += MiscRegRegImmMemOpDeclare.subst(McrDccmvauIop)
decoder_output += MiscRegRegImmOpConstructor.subst(McrDccmvauIop)
exec_output += Mcr15Execute.subst(McrDccmvauIop) + \
@@ -1204,7 +1204,7 @@
"postacc_code": "",
"ea_code": McrDccimvacCode,
"predicate_test": predicateTest},
- ['IsMemRef', 'IsStore'])
+ ['IsStore'])
header_output += MiscRegRegImmMemOpDeclare.subst(McrDccimvacIop)
decoder_output += MiscRegRegImmOpConstructor.subst(McrDccimvacIop)
exec_output += Mcr15Execute.subst(McrDccimvacIop) + \
@@ -1238,7 +1238,8 @@
dsbIop = InstObjParams("dsb", "Dsb", "ImmOp",
{"code": dsbCode,
"predicate_test": predicateTest},
- ['IsMemBarrier', 'IsSerializeAfter'])
+ ['IsReadBarrier', 'IsWriteBarrier',
+ 'IsSerializeAfter'])
header_output += ImmOpDeclare.subst(dsbIop)
decoder_output += ImmOpConstructor.subst(dsbIop)
exec_output += PredOpExecute.subst(dsbIop)
@@ -1254,7 +1255,7 @@
dmbIop = InstObjParams("dmb", "Dmb", "ImmOp",
{"code": dmbCode,
"predicate_test": predicateTest},
- ['IsMemBarrier'])
+ ['IsReadBarrier', 'IsWriteBarrier'])
header_output += ImmOpDeclare.subst(dmbIop)
decoder_output += ImmOpConstructor.subst(dmbIop)
exec_output += PredOpExecute.subst(dmbIop)
diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa
index 7911ec9..e8dc41c 100644
--- a/src/arch/arm/isa/insts/misc64.isa
+++ b/src/arch/arm/isa/insts/misc64.isa
@@ -173,13 +173,14 @@
exec_output += BasicExecute.subst(isbIop)
dsbIop = InstObjParams("dsb", "Dsb64", "ArmStaticInst", "",
- ['IsMemBarrier', 'IsSerializeAfter'])
+ ['IsReadBarrier', 'IsWriteBarrier',
+ 'IsSerializeAfter'])
header_output += BasicDeclare.subst(dsbIop)
decoder_output += BasicConstructor64.subst(dsbIop)
exec_output += BasicExecute.subst(dsbIop)
dmbIop = InstObjParams("dmb", "Dmb64", "ArmStaticInst", "",
- ['IsMemBarrier'])
+ ['IsReadBarrier', 'IsWriteBarrier'])
header_output += BasicDeclare.subst(dmbIop)
decoder_output += BasicConstructor64.subst(dmbIop)
exec_output += BasicExecute.subst(dmbIop)
diff --git a/src/arch/arm/isa/insts/neon64_mem.isa b/src/arch/arm/isa/insts/neon64_mem.isa
index e511f61..80741fb 100644
--- a/src/arch/arm/isa/insts/neon64_mem.isa
+++ b/src/arch/arm/isa/insts/neon64_mem.isa
@@ -146,7 +146,7 @@
'memacc_code' : loadMemAccCode,
'ea_code' : simd64EnabledCheckCode + eaCode,
},
- [ 'IsMicroop', 'IsMemRef', 'IsLoad' ])
+ [ 'IsMicroop', 'IsLoad' ])
loadIop.snippets["memacc_code"] += zeroSveVecRegUpperPartCode % \
"AA64FpDest"
storeIop = InstObjParams(name + 'st',
@@ -156,7 +156,7 @@
'memacc_code' : storeMemAccCode,
'ea_code' : simd64EnabledCheckCode + eaCode,
},
- [ 'IsMicroop', 'IsMemRef', 'IsStore' ])
+ [ 'IsMicroop', 'IsStore' ])
exec_output += NeonLoadExecute64.subst(loadIop) + \
NeonLoadInitiateAcc64.subst(loadIop) + \
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index e99f6ad..48bf153 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -187,8 +187,7 @@
self.memFlags.append("ArmISA::TLB::AllowUnaligned")
if self.flavor in ("release", "relex"):
- self.instFlags.extend(["IsMemBarrier",
- "IsWriteBarrier",
+ self.instFlags.extend(["IsWriteBarrier",
"IsReadBarrier"])
self.memFlags.append("Request::RELEASE")
@@ -269,8 +268,7 @@
self.memFlags.append("ArmISA::TLB::AlignWord")
if self.flavor in ("release", "relex"):
- self.instFlags.extend(["IsMemBarrier",
- "IsWriteBarrier",
+ self.instFlags.extend(["IsWriteBarrier",
"IsReadBarrier"])
self.memFlags.append("Request::RELEASE")
diff --git a/src/arch/arm/isa/insts/str64.isa b/src/arch/arm/isa/insts/str64.isa
index ac84533..ed99064 100644
--- a/src/arch/arm/isa/insts/str64.isa
+++ b/src/arch/arm/isa/insts/str64.isa
@@ -79,8 +79,7 @@
self.instFlags.append("IsMicroop")
if self.flavor in ("release", "relex", "relexp"):
- self.instFlags.extend(["IsMemBarrier",
- "IsWriteBarrier",
+ self.instFlags.extend(["IsWriteBarrier",
"IsReadBarrier"])
self.memFlags.append("Request::RELEASE")
diff --git a/src/arch/arm/isa/insts/sve_mem.isa b/src/arch/arm/isa/insts/sve_mem.isa
index 66bfabb..8599900 100644
--- a/src/arch/arm/isa/insts/sve_mem.isa
+++ b/src/arch/arm/isa/insts/sve_mem.isa
@@ -823,7 +823,7 @@
'rden_code' : loadRdEnableCode,
'fault_code' : '',
'fa_code' : ''},
- ['IsMemRef', 'IsLoad'])
+ ['IsLoad'])
storeIop = InstObjParams('str',
'SveStrPred' if isPred else 'SveStrVec',
'SveMemPredFillSpill' if isPred else 'SveMemVecFillSpill',
@@ -833,7 +833,7 @@
'memacc_code': storeMemAccCode,
'ea_code' : sveEnabledCheckCode + eaCode,
'fa_code' : ''},
- ['IsMemRef', 'IsStore'])
+ ['IsStore'])
header_output += SveMemFillSpillOpDeclare.subst(loadIop)
header_output += SveMemFillSpillOpDeclare.subst(storeIop)
exec_output += (
@@ -1007,7 +1007,7 @@
'ea_code' : sveEnabledCheckCode + eaCode,
'fault_code' : '',
'fa_code' : ''},
- ['IsMemRef', 'IsLoad'])
+ ['IsLoad'])
storeIop = InstObjParams('st1',
'SveContigStoreSI' if offsetIsImm else 'SveContigStoreSS',
'SveContigMemSI' if offsetIsImm else 'SveContigMemSS',
@@ -1017,7 +1017,7 @@
'memacc_code': storeMemAccCode,
'ea_code' : sveEnabledCheckCode + eaCode,
'fa_code' : ''},
- ['IsMemRef', 'IsStore'])
+ ['IsStore'])
faultIop = InstObjParams('ldff1' if firstFaulting else 'ldnf1',
'SveContigFFLoadSS' if firstFaulting else 'SveContigNFLoadSI',
'SveContigMemSS' if firstFaulting else 'SveContigMemSI',
@@ -1028,7 +1028,7 @@
'ea_code' : sveEnabledCheckCode + eaCode,
'fault_code' : faultCode,
'fa_code' : ''},
- ['IsMemRef', 'IsLoad'])
+ ['IsLoad'])
faultIop.snippets['memacc_code'] = (ffrReadBackCode +
faultIop.snippets['memacc_code'])
if offsetIsImm:
@@ -1091,7 +1091,7 @@
'memacc_code': memAccCode,
'ea_code' : sveEnabledCheckCode + eaCode,
'fa_code' : ''},
- ['IsMemRef', 'IsLoad'])
+ ['IsLoad'])
header_output += SveContigMemSIOpDeclare.subst(iop)
exec_output += (
SveLoadAndReplExecute.subst(iop) +
@@ -1158,7 +1158,7 @@
'fault_status_reset_code' : faultStatusResetCode,
'pred_check_code' : predCheckCode,
'fa_code' : ''},
- ['IsMicroop', 'IsMemRef', 'IsLoad'])
+ ['IsMicroop', 'IsLoad'])
storeIop = InstObjParams('st1',
('SveScatterStoreVIMicroop'
if indexed_addr_form == IndexedAddrForm.VEC_PLUS_IMM
@@ -1170,7 +1170,7 @@
'ea_code' : sveEnabledCheckCode + eaCode_store,
'pred_check_code' : predCheckCode,
'fa_code' : ''},
- ['IsMicroop', 'IsMemRef', 'IsStore'])
+ ['IsMicroop', 'IsStore'])
if indexed_addr_form == IndexedAddrForm.VEC_PLUS_IMM:
header_output += SveIndexedMemVIMicroopDeclare.subst(loadIop)
header_output += SveIndexedMemVIMicroopDeclare.subst(storeIop)
@@ -1445,7 +1445,7 @@
'memacc_code': loadMemAccCode,
'ea_code' : sveEnabledCheckCode + eaCode,
'fa_code' : ''},
- ['IsMemRef', 'IsLoad', 'IsMicroop'])
+ ['IsLoad', 'IsMicroop'])
storeIop = InstObjParams('stxx',
'SveStoreRegImmMicroop' if offsetIsImm
else 'SveStoreRegRegMicroop',
@@ -1455,7 +1455,7 @@
'memacc_code': storeMemAccCode,
'ea_code' : sveEnabledCheckCode + eaCode,
'fa_code' : ''},
- ['IsMemRef', 'IsStore', 'IsMicroop'])
+ ['IsStore', 'IsMicroop'])
if offsetIsImm:
header_output += SveStructMemSIMicroopDeclare.subst(loadIop)
header_output += SveStructMemSIMicroopDeclare.subst(storeIop)
@@ -1528,7 +1528,7 @@
'ea_code': sveEnabledCheckCode + eaCode,
'fault_code': '',
'fa_code': ''},
- ['IsMemRef', 'IsLoad'])
+ ['IsLoad'])
if offsetIsImm:
header_output += SveContigMemSIOpDeclare.subst(iop)
else:
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index e9ee098..134c51f 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -681,7 +681,7 @@
'XURc' : intRegX64('urc'),
#Memory Operand
- 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
+ 'Mem': ('Mem', 'uw', None, (None, 'IsLoad', 'IsStore'), srtNormal),
#PCState fields
'RawPC': pcStateReg('pc', srtPC),
diff --git a/src/arch/arm/isa/templates/semihost.isa b/src/arch/arm/isa/templates/semihost.isa
index 0ad84c8..c60db17 100644
--- a/src/arch/arm/isa/templates/semihost.isa
+++ b/src/arch/arm/isa/templates/semihost.isa
@@ -38,8 +38,8 @@
// A new class of Semihosting constructor templates has been added.
// Their main purpose is to check if the Exception Generation
// Instructions (HLT, SVC) are actually a semihosting command.
-// If that is the case, the IsMemBarrier flag is raised, so that
-// in the O3 model we perform a coherent memory access during
+// If that is the case, the IsReadBarrier and IsWriteBarrier flags are raised,
+// so that in the O3 model we perform a coherent memory access during
// the semihosting operation.
// Please note: since we don't have a thread context pointer in the
// constructor we cannot check if semihosting is enabled in the
@@ -64,7 +64,8 @@
auto semihost_imm = machInst.thumb? %(thumb_semihost)s :
%(arm_semihost)s;
if (_imm == semihost_imm) {
- flags[IsMemBarrier] = true;
+ flags[IsReadBarrier] = true;
+ flags[IsWriteBarrier] = true;
}
}
}};
@@ -78,7 +79,8 @@
// In AArch64 there is only one instruction for issuing
// semhosting commands: HLT #0xF000
if (_imm == 0xF000) {
- flags[IsMemBarrier] = true;
+ flags[IsReadBarrier] = true;
+ flags[IsWriteBarrier] = true;
}
}
}};
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index f62000e..3b2b015 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -166,7 +166,7 @@
fault = std::make_shared<SystemCallFault>();
}});
}
- 0x7: sync({{ ; }}, IsMemBarrier);
+ 0x7: sync({{ ; }}, IsReadBarrier, IsWriteBarrier);
0x5: break({{fault = std::make_shared<BreakpointFault>();}});
}
@@ -174,10 +174,10 @@
0x2: decode FUNCTION_LO {
0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }},
- IntMultOp, IsIprAccess);
+ IntMultOp, IsSerializeBefore);
0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }});
0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }},
- IntMultOp, IsIprAccess);
+ IntMultOp, IsSerializeBefore);
0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }});
}
@@ -719,7 +719,7 @@
LLFlag = 0;
Status = status;
SRSCtl = srsCtl;
- }}, IsReturn, IsSerializing, IsERET);
+ }}, IsReturn, IsSerializing);
0x1F: deret({{
DebugReg debug = Debug;
@@ -732,7 +732,7 @@
// Undefined;
}
Debug = debug;
- }}, IsReturn, IsSerializing, IsERET);
+ }}, IsReturn, IsSerializing);
}
format CP0TLB {
0x01: tlbr({{
diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index 4975a13..7c2b27c 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -241,7 +241,6 @@
code += 'R31 = NNPC;\n'
elif x == 'Likely':
not_taken_code = 'NNPC = NPC; NPC = PC;'
- inst_flags += ('IsCondDelaySlot', )
else:
inst_flags += (x, )
@@ -280,7 +279,6 @@
code += 'R32 = NNPC;'
elif x == 'Likely':
not_taken_code = 'NNPC = NPC, NPC = PC;'
- inst_flags += ('IsCondDelaySlot', )
else:
inst_flags += (x, )
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
index 9a6d614..12af2d6 100644
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -173,8 +173,6 @@
code = decl_code + code + write_code
- opt_flags += ('IsDspOp',)
-
iop = InstObjParams(name, Name, 'DspIntOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
@@ -204,8 +202,6 @@
code = decl_code + fetch_code + code + write_code
- opt_flags += ('IsDspOp',)
-
iop = InstObjParams(name, Name, 'DspHiLoOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index 491dd0c..c5fd6f8 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -458,7 +458,6 @@
def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
mem_flags = [], inst_flags = []) {{
- inst_flags += ['IsIndexed']
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
decode_template = ImmNopCheckDecode,
@@ -467,7 +466,6 @@
def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
mem_flags = [], inst_flags = []) {{
- inst_flags += ['IsIndexed']
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
exec_template_base = 'Store')
@@ -475,7 +473,7 @@
def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
mem_flags = [], inst_flags = []) {{
- inst_flags += ['IsIndexed', 'IsFloating']
+ inst_flags += ['IsFloating']
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
decode_template = ImmNopCheckDecode,
@@ -484,7 +482,7 @@
def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
mem_flags = [], inst_flags = []) {{
- inst_flags += ['IsIndexed', 'IsFloating']
+ inst_flags += ['IsFloating']
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
exec_template_base = 'Store')
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa
index 26c5a54..3cb2d43 100644
--- a/src/arch/mips/isa/operands.isa
+++ b/src/arch/mips/isa/operands.isa
@@ -144,7 +144,7 @@
'Cause': ('ControlReg','uw', 'MISCREG_CAUSE',None,1),
#Memory Operand
- 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
+ 'Mem': ('Mem', 'uw', None, (None, 'IsLoad', 'IsStore'), 4),
#Program Counter Operands
'PC': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 4),
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 8400ed6..153a991 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -50,6 +50,7 @@
#include "arch/registers.hh"
#include "base/logging.hh"
#include "base/trace.hh"
+#include "cpu/base.hh"
#include "debug/LLSC.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
diff --git a/src/arch/null/SConscript b/src/arch/null/SConscript
index 41457e2..3f0b053 100644
--- a/src/arch/null/SConscript
+++ b/src/arch/null/SConscript
@@ -36,6 +36,3 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
-
-if env['TARGET_ISA'] == 'null':
- Source('cpu_dummy.cc')
diff --git a/src/arch/null/cpu_dummy.cc b/src/arch/null/cpu_dummy.cc
deleted file mode 100644
index df30b81..0000000
--- a/src/arch/null/cpu_dummy.cc
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2013 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * Provide the actual storage for maxThreadsPerCPU which is declared
- * extern and normally provided by src/cpu/base.cc
- */
-int maxThreadsPerCPU = 1;
diff --git a/src/arch/null/cpu_dummy.hh b/src/arch/null/cpu_dummy.hh
deleted file mode 100644
index 7e183eb..0000000
--- a/src/arch/null/cpu_dummy.hh
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2013 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_NULL_CPU_DUMMY_HH__
-#define __ARCH_NULL_CPU_DUMMY_HH__
-
-#include "sim/core.hh"
-
-class BaseCPU
-{
- public:
- static int numSimulatedInsts() { return 0; }
- static int numSimulatedOps() { return 0; }
- static void wakeup(ThreadID tid) { ; }
-};
-
-#endif // __ARCH_NULL_CPU_DUMMY_HH__
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index b7b9aff..475ddcc 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -343,8 +343,8 @@
format MiscOp {
278: dcbt({{ }});
246: dcbtst({{ }});
- 598: sync({{ }}, [ IsMemBarrier ]);
- 854: eieio({{ }}, [ IsMemBarrier ]);
+ 598: sync({{ }}, [ IsReadBarrier, IsWriteBarrier ]);
+ 854: eieio({{ }}, [ IsReadBarrier, IsWriteBarrier ]);
}
}
diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa
index 397364f..e77fde2 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -54,7 +54,7 @@
'Ft': ('FloatReg', 'df', 'FRT', 'IsFloating', 5),
# Memory Operand
- 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
+ 'Mem': ('Mem', 'uw', None, (None, 'IsLoad', 'IsStore'), 8),
# Program counter and next
'CIA': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9),
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 7b19464..b39005f 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -421,7 +421,7 @@
0x03: decode FUNCT3 {
format FenceOp {
0x0: fence({{
- }}, uint64_t, IsMemBarrier, No_OpClass);
+ }}, uint64_t, IsReadBarrier, IsWriteBarrier, No_OpClass);
0x1: fence_i({{
}}, uint64_t, IsNonSpeculative, IsSerializeAfter, No_OpClass);
}
diff --git a/src/arch/riscv/isa/formats/amo.isa b/src/arch/riscv/isa/formats/amo.isa
index 8c7a6a5..7d01145 100644
--- a/src/arch/riscv/isa/formats/amo.isa
+++ b/src/arch/riscv/isa/formats/amo.isa
@@ -100,7 +100,8 @@
if (RL) {
rel_fence = new MemFenceMicro(machInst, No_OpClass);
rel_fence->setFlag(IsFirstMicroop);
- rel_fence->setFlag(IsMemBarrier);
+ rel_fence->setFlag(IsReadBarrier);
+ rel_fence->setFlag(IsWriteBarrier);
rel_fence->setFlag(IsDelayedCommit);
}
@@ -121,7 +122,8 @@
if (AQ) {
acq_fence = new MemFenceMicro(machInst, No_OpClass);
acq_fence->setFlag(IsLastMicroop);
- acq_fence->setFlag(IsMemBarrier);
+ acq_fence->setFlag(IsReadBarrier);
+ acq_fence->setFlag(IsWriteBarrier);
}
if (RL && AQ) {
@@ -159,7 +161,8 @@
if (RL) {
rel_fence = new MemFenceMicro(machInst, No_OpClass);
rel_fence->setFlag(IsFirstMicroop);
- rel_fence->setFlag(IsMemBarrier);
+ rel_fence->setFlag(IsReadBarrier);
+ rel_fence->setFlag(IsWriteBarrier);
rel_fence->setFlag(IsDelayedCommit);
}
@@ -180,7 +183,8 @@
if (AQ) {
acq_fence = new MemFenceMicro(machInst, No_OpClass);
acq_fence->setFlag(IsLastMicroop);
- acq_fence->setFlag(IsMemBarrier);
+ acq_fence->setFlag(IsReadBarrier);
+ acq_fence->setFlag(IsWriteBarrier);
}
if (RL && AQ) {
@@ -203,7 +207,6 @@
%(constructor)s;
// overwrite default flags
- flags[IsMemRef] = true;
flags[IsLoad] = false;
flags[IsStore] = false;
flags[IsAtomic] = true;
diff --git a/src/arch/riscv/isa/operands.isa b/src/arch/riscv/isa/operands.isa
index 12f5577..78cd5f9 100644
--- a/src/arch/riscv/isa/operands.isa
+++ b/src/arch/riscv/isa/operands.isa
@@ -72,7 +72,7 @@
'Fp2_bits': ('FloatReg', 'ud', 'FP2 + 8', 'IsFloating', 2),
#Memory Operand
- 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5),
+ 'Mem': ('Mem', 'ud', None, (None, 'IsLoad', 'IsStore'), 5),
#Program Counter Operands
'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7),
diff --git a/src/arch/riscv/locked_mem.hh b/src/arch/riscv/locked_mem.hh
index fd45b3f..10d1839 100644
--- a/src/arch/riscv/locked_mem.hh
+++ b/src/arch/riscv/locked_mem.hh
@@ -52,6 +52,7 @@
#include "arch/registers.hh"
#include "base/logging.hh"
#include "base/trace.hh"
+#include "cpu/base.hh"
#include "debug/LLSC.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 75a4d75..c89a141 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -335,7 +335,8 @@
// 7-14 should cause an illegal instruction exception
0x0F: decode I {
0x0: Nop::stbar(IsWriteBarrier, MemWriteOp);
- 0x1: Nop::membar(IsMemBarrier, MemReadOp);
+ 0x1: Nop::membar(IsReadBarrier, IsWriteBarrier,
+ MemReadOp);
}
0x10: Priv::rdpcr({{Rd = Pcr;}});
0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index 2c1eec6..7a2da13 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -187,6 +187,6 @@
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
# Mem gets a large number so it's always last
- 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
+ 'Mem': ('Mem', 'udw', None, (None, 'IsLoad', 'IsStore'), 100)
}};
diff --git a/src/arch/sparc/linux/linux.hh b/src/arch/sparc/linux/linux.hh
index ed50a30..431ec06 100644
--- a/src/arch/sparc/linux/linux.hh
+++ b/src/arch/sparc/linux/linux.hh
@@ -230,6 +230,11 @@
if (stack)
ctc->setIntReg(SparcISA::StackPointerReg, stack);
+
+ // Set these extra values. Since "clone" doesn't return two values,
+ // we can set these and they won't be clobbered by the syscall ABI.
+ ptc->setIntReg(SparcISA::SyscallPseudoReturnReg, 0);
+ ctc->setIntReg(SparcISA::SyscallPseudoReturnReg, 1);
}
};
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 5d45144..e8b1e3d 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -786,13 +786,12 @@
//0x6: group15();
0x6: decode MODRM_MOD {
0x3: decode MODRM_REG {
- 0x5: BasicOperate::LFENCE(
- {{/*Nothing*/}}, IsReadBarrier,
- IsSerializeAfter);
- 0x6: BasicOperate::MFENCE(
- {{/*Nothing*/}}, IsMemBarrier);
- 0x7: BasicOperate::SFENCE(
- {{/*Nothing*/}}, IsWriteBarrier);
+ 0x5: BasicOperate::LFENCE({{/*Nothing*/}},
+ IsReadBarrier, IsSerializeAfter);
+ 0x6: BasicOperate::MFENCE({{/*Nothing*/}},
+ IsReadBarrier, IsWriteBarrier);
+ 0x7: BasicOperate::SFENCE({{/*Nothing*/}},
+ IsWriteBarrier);
default: Inst::UD2();
}
default: decode MODRM_REG {
diff --git a/src/arch/x86/isa/formats/monitor_mwait.isa b/src/arch/x86/isa/formats/monitor_mwait.isa
index 809623d..b5fe34c 100644
--- a/src/arch/x86/isa/formats/monitor_mwait.isa
+++ b/src/arch/x86/isa/formats/monitor_mwait.isa
@@ -90,7 +90,6 @@
OpClass __opClass) :
X86ISA::X86StaticInst(_mnemonic, _machInst, __opClass)
{
- flags[IsMemRef] = 1;
flags[IsLoad] = 1;
}
diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa
index a7dda10..1d50569 100644
--- a/src/arch/x86/isa/microops/specop.isa
+++ b/src/arch/x86/isa/microops/specop.isa
@@ -233,7 +233,8 @@
def __init__(self):
self.className = "Mfence"
self.mnemonic = "mfence"
- self.instFlags = "| (1ULL << StaticInst::IsMemBarrier)"
+ self.instFlags = "| (1ULL << StaticInst::IsReadBarrier)" + \
+ "| (1ULL << StaticInst::IsWriteBarrier)"
def getAllocator(self, microFlags):
allocString = '''
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 2cd92dd..504deb7 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -64,7 +64,7 @@
def floatReg(idx, id):
return ('FloatReg', 'df', idx, 'IsFloating', id)
def ccReg(idx, id):
- return ('CCReg', 'uqw', idx, 'IsCC', id)
+ return ('CCReg', 'uqw', idx, None, id)
def controlReg(idx, id, ctype = 'uqw'):
return ('ControlReg', ctype, idx,
(None, None, ['IsSerializeAfter',
@@ -147,20 +147,20 @@
# would be retained, the write predicate checks if any of the bits
# are being written.
- 'PredccFlagBits': ('CCReg', 'uqw', '(CCREG_ZAPS)', 'IsCC',
+ 'PredccFlagBits': ('CCReg', 'uqw', '(CCREG_ZAPS)', None,
60, None, None, '''(((ext & (PFBit | AFBit | ZFBit | SFBit
)) != (PFBit | AFBit | ZFBit | SFBit )) &&
((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0))''',
'((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0)'),
- 'PredcfofBits': ('CCReg', 'uqw', '(CCREG_CFOF)', 'IsCC',
+ 'PredcfofBits': ('CCReg', 'uqw', '(CCREG_CFOF)', None,
61, None, None, '''(((ext & CFBit) == 0 ||
(ext & OFBit) == 0) && ((ext & (CFBit | OFBit)) != 0))''',
'((ext & (CFBit | OFBit)) != 0)'),
- 'PreddfBit': ('CCReg', 'uqw', '(CCREG_DF)', 'IsCC',
+ 'PreddfBit': ('CCReg', 'uqw', '(CCREG_DF)', None,
62, None, None, '(false)', '((ext & DFBit) != 0)'),
- 'PredecfBit': ('CCReg', 'uqw', '(CCREG_ECF)', 'IsCC',
+ 'PredecfBit': ('CCReg', 'uqw', '(CCREG_ECF)', None,
63, None, None, '(false)', '((ext & ECFBit) != 0)'),
- 'PredezfBit': ('CCReg', 'uqw', '(CCREG_EZF)', 'IsCC',
+ 'PredezfBit': ('CCReg', 'uqw', '(CCREG_EZF)', None,
64, None, None, '(false)', '((ext & EZFBit) != 0)'),
# These register should needs to be more protected so that later
@@ -207,5 +207,5 @@
'TscOp': controlReg('MISCREG_TSC', 212),
'M5Reg': squashCReg('MISCREG_M5_REG', 213),
'Mem': ('Mem', 'uqw', None, \
- ('IsMemRef', 'IsLoad', 'IsStore'), 300)
+ (None, 'IsLoad', 'IsStore'), 300)
}};
diff --git a/src/base/SConscript b/src/base/SConscript
index bd18429..6514de0 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -74,15 +74,6 @@
Source('types.cc')
GTest('types.test', 'types.test.cc', 'types.cc')
-Source('loader/dtb_file.cc')
-Source('loader/elf_object.cc')
-Source('loader/image_file_data.cc')
-GTest('loader/image_file_data.test', 'loader/image_file_data.test.cc',
-'loader/image_file_data.cc')
-Source('loader/memory_image.cc')
-Source('loader/object_file.cc')
-Source('loader/symtab.cc')
-
Source('stats/group.cc')
Source('stats/text.cc')
if env['USE_HDF5']:
diff --git a/src/base/fiber.cc b/src/base/fiber.cc
index 3d2e2e9..fe1bad0 100644
--- a/src/base/fiber.cc
+++ b/src/base/fiber.cc
@@ -145,10 +145,12 @@
setStarted();
- // Swap back to the parent context which is still considered "current",
- // now that we're ready to go.
- int ret M5_VAR_USED = swapcontext(&ctx, &_currentFiber->ctx);
- panic_if(ret == -1, strerror(errno));
+ if (_setjmp(jmp) == 0) {
+ // Swap back to the parent context which is still considered "current",
+ // now that we're ready to go.
+ int ret = swapcontext(&ctx, &_currentFiber->ctx);
+ panic_if(ret == -1, strerror(errno));
+ }
// Call main() when we're been reactivated for the first time.
main();
@@ -175,7 +177,8 @@
Fiber *prev = _currentFiber;
Fiber *next = this;
_currentFiber = next;
- swapcontext(&prev->ctx, &next->ctx);
+ if (_setjmp(prev->jmp) == 0)
+ _longjmp(next->jmp, 1);
}
Fiber *Fiber::currentFiber() { return _currentFiber; }
diff --git a/src/base/fiber.hh b/src/base/fiber.hh
index dc7ef01..be8937f 100644
--- a/src/base/fiber.hh
+++ b/src/base/fiber.hh
@@ -39,6 +39,12 @@
#include <ucontext.h>
#endif
+// Avoid fortify source for longjmp to work between ucontext stacks.
+#pragma push_macro("__USE_FORTIFY_LEVEL")
+#undef __USE_FORTIFY_LEVEL
+#include <setjmp.h>
+#pragma pop_macro("__USE_FORTIFY_LEVEL")
+
#include <cstddef>
#include <cstdint>
@@ -137,6 +143,10 @@
void start();
ucontext_t ctx;
+ // ucontext is slow in swapcontext. Here we use _setjmp/_longjmp to avoid
+ // the additional signals for speed up.
+ jmp_buf jmp;
+
Fiber *link;
// The stack for this context, or a nullptr if allocated elsewhere.
diff --git a/src/base/loader/SConscript b/src/base/loader/SConscript
new file mode 100644
index 0000000..d17875f
--- /dev/null
+++ b/src/base/loader/SConscript
@@ -0,0 +1,37 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Import('*')
+
+Source('dtb_file.cc')
+Source('elf_object.cc')
+Source('image_file_data.cc')
+GTest('image_file_data.test', 'image_file_data.test.cc', 'image_file_data.cc')
+Source('memory_image.cc')
+Source('object_file.cc')
+Source('symtab.cc')
diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py
index 1c2b63a..4775289 100644
--- a/src/cpu/StaticInstFlags.py
+++ b/src/cpu/StaticInstFlags.py
@@ -36,15 +36,9 @@
# one of these two flags set, it is possible for an instruction to have
# neither (e.g., direct unconditional branches, memory barriers) or both
# (e.g., an FP/int conversion).
-# - If IsMemRef is set, then exactly one of IsLoad or IsStore will be set.
# - If IsControl is set, then exactly one of IsDirectControl or IsIndirect
# Control will be set, and exactly one of IsCondControl or IsUncondControl
# will be set.
-# - IsSerializing, IsMemBarrier, and IsWriteBarrier are implemented as flags
-# since in the current model there's no other way for instructions to inject
-# behavior into the pipeline outside of fetch. Once we go to an exec-in-exec
-# CPU model we should be able to get rid of these flags and implement this
-# behavior via the execute() methods.
class StaticInstFlags(Enum):
wrapper_name = 'StaticInstFlags'
@@ -56,17 +50,13 @@
'IsInteger', # References integer regs.
'IsFloating', # References FP regs.
- 'IsCC', # References CC regs.
'IsVector', # References Vector regs.
'IsVectorElem', # References Vector reg elems.
- 'IsMemRef', # References memory (load, store, or prefetch)
'IsLoad', # Reads from memory (load or prefetch).
'IsStore', # Writes to memory.
'IsAtomic', # Does atomic RMW to memory.
'IsStoreConditional', # Store conditional instruction.
- 'IsIndexed', # Accesses memory with an indexed address
- # computation
'IsInstPrefetch', # Instruction-cache prefetch.
'IsDataPrefetch', # Data-cache prefetch.
@@ -78,23 +68,16 @@
'IsCall', # Subroutine call.
'IsReturn', # Subroutine return.
- 'IsCondDelaySlot', # Conditional Delay-Slot Instruction
-
- 'IsThreadSync', # Thread synchronization operation.
-
'IsSerializing', # Serializes pipeline: won't execute until all
# older instructions have committed.
'IsSerializeBefore',
'IsSerializeAfter',
- 'IsMemBarrier', # Is a memory barrier
'IsWriteBarrier', # Is a write barrier
'IsReadBarrier', # Is a read barrier
- 'IsERET', # <- Causes the IFU to stall (MIPS ISA)
'IsNonSpeculative', # Should not be executed speculatively
'IsQuiesce', # Is a quiesce instruction
- 'IsIprAccess', # Accesses IPRs
'IsUnverifiable', # Can't be verified by a checker
'IsSyscall', # Causes a system call to be emulated in syscall
@@ -106,11 +89,9 @@
'IsDelayedCommit', # This microop doesn't commit right away
'IsLastMicroop', # This microop ends a microop sequence
'IsFirstMicroop', # This microop begins a microop sequence
- # This flag doesn't do anything yet
- 'IsMicroBranch', # This microop branches within the microcode for
- # a macroop
- 'IsDspOp',
+
'IsSquashAfter', # Squash all uncommitted state after executed
+
# hardware transactional memory
'IsHtmStart', # Starts a HTM transaction
'IsHtmStop', # Stops (commits) a HTM transaction
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 9ba1b31..ef843d7 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012,2016-2017, 2019 ARM Limited
+ * Copyright (c) 2011-2012,2016-2017, 2019-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -63,6 +63,7 @@
#include "sim/clocked_object.hh"
#include "sim/full_system.hh"
#include "sim/process.hh"
+#include "sim/root.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"
@@ -72,6 +73,8 @@
using namespace std;
+std::unique_ptr<BaseCPU::GlobalStats> BaseCPU::globalStats;
+
vector<BaseCPU *> BaseCPU::cpuList;
// This variable reflects the max number of threads in any CPU. Be
@@ -370,6 +373,12 @@
{
ClockedObject::regStats();
+ if (!globalStats) {
+ /* We need to construct the global CPU stat structure here
+ * since it needs a pointer to the Root object. */
+ globalStats.reset(new GlobalStats(Root::root()));
+ }
+
using namespace Stats;
numCycles
@@ -754,3 +763,39 @@
{
return params()->wait_for_remote_gdb;
}
+
+
+BaseCPU::GlobalStats::GlobalStats(::Stats::Group *parent)
+ : ::Stats::Group(parent),
+ simInsts(this, "sim_insts", "Number of instructions simulated"),
+ simOps(this, "sim_ops", "Number of ops (including micro ops) simulated"),
+ hostInstRate(this, "host_inst_rate",
+ "Simulator instruction rate (inst/s)"),
+ hostOpRate(this, "host_op_rate",
+ "Simulator op (including micro ops) rate (op/s)")
+{
+ simInsts
+ .functor(BaseCPU::numSimulatedInsts)
+ .precision(0)
+ .prereq(simInsts)
+ ;
+
+ simOps
+ .functor(BaseCPU::numSimulatedOps)
+ .precision(0)
+ .prereq(simOps)
+ ;
+
+ hostInstRate
+ .precision(0)
+ .prereq(simInsts)
+ ;
+
+ hostOpRate
+ .precision(0)
+ .prereq(simOps)
+ ;
+
+ hostInstRate = simInsts / hostSeconds;
+ hostOpRate = simOps / hostSeconds;
+}
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 5320492..9cf4baa 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -48,7 +48,7 @@
// and if so stop here
#include "config/the_isa.hh"
#if THE_ISA == NULL_ISA
-#include "arch/null/cpu_dummy.hh"
+#error Including BaseCPU in a system without CPU support
#else
#include "arch/generic/interrupts.hh"
#include "base/statistics.hh"
@@ -145,6 +145,23 @@
/** Cache the cache line size that we get from the system */
const unsigned int _cacheLineSize;
+ /** Global CPU statistics that are merged into the Root object. */
+ struct GlobalStats : public Stats::Group {
+ GlobalStats(::Stats::Group *parent);
+
+ ::Stats::Value simInsts;
+ ::Stats::Value simOps;
+
+ ::Stats::Formula hostInstRate;
+ ::Stats::Formula hostOpRate;
+ };
+
+ /**
+ * Pointer to the global stat structure. This needs to be
+ * constructed from regStats since we merge it into the root
+ * group. */
+ static std::unique_ptr<GlobalStats> globalStats;
+
public:
/**
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index a6c08cc..fd216b1 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -541,8 +541,6 @@
bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
bool isCondCtrl() const { return staticInst->isCondCtrl(); }
bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
- bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
- bool isThreadSync() const { return staticInst->isThreadSync(); }
bool isSerializing() const { return staticInst->isSerializing(); }
bool
isSerializeBefore() const
@@ -555,11 +553,11 @@
return staticInst->isSerializeAfter() || status[SerializeAfter];
}
bool isSquashAfter() const { return staticInst->isSquashAfter(); }
- bool isMemBarrier() const { return staticInst->isMemBarrier(); }
+ bool isFullMemBarrier() const { return staticInst->isFullMemBarrier(); }
+ bool isReadBarrier() const { return staticInst->isReadBarrier(); }
bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
bool isQuiesce() const { return staticInst->isQuiesce(); }
- bool isIprAccess() const { return staticInst->isIprAccess(); }
bool isUnverifiable() const { return staticInst->isUnverifiable(); }
bool isSyscall() const { return staticInst->isSyscall(); }
bool isMacroop() const { return staticInst->isMacroop(); }
@@ -567,7 +565,6 @@
bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
bool isLastMicroop() const { return staticInst->isLastMicroop(); }
bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
- bool isMicroBranch() const { return staticInst->isMicroBranch(); }
// hardware transactional memory
bool isHtmStart() const { return staticInst->isHtmStart(); }
bool isHtmStop() const { return staticInst->isHtmStop(); }
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index 45ca002..0833224 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -224,8 +224,7 @@
!inst->isFault() &&
inst->isLastOpInInst() &&
(inst->staticInst->isSerializeAfter() ||
- inst->staticInst->isSquashAfter() ||
- inst->staticInst->isIprAccess());
+ inst->staticInst->isSquashAfter());
DPRINTF(Branch, "tryToBranch before: %s after: %s%s\n",
pc_before, target, (force_branch ? " (forcing)" : ""));
@@ -782,7 +781,7 @@
/* Mark up barriers in the LSQ */
if (!discarded && inst->isInst() &&
- inst->staticInst->isMemBarrier())
+ inst->staticInst->isFullMemBarrier())
{
DPRINTF(MinorMem, "Issuing memory barrier inst: %s\n", *inst);
lsq.issuedMemBarrierInst(inst);
@@ -952,7 +951,7 @@
completed_inst = completed_mem_inst;
}
completed_mem_issue = completed_inst;
- } else if (inst->isInst() && inst->staticInst->isMemBarrier() &&
+ } else if (inst->isInst() && inst->staticInst->isFullMemBarrier() &&
!lsq.canPushIntoStoreBuffer())
{
DPRINTF(MinorExecute, "Can't commit data barrier inst: %s yet as"
@@ -1369,7 +1368,7 @@
ex_info.inFlightInsts->pop();
/* Complete barriers in the LSQ/move to store buffer */
- if (inst->isInst() && inst->staticInst->isMemBarrier()) {
+ if (inst->isInst() && inst->staticInst->isFullMemBarrier()) {
DPRINTF(MinorMem, "Completing memory barrier"
" inst: %s committed: %d\n", *inst, committed_inst);
lsq.completeMemBarrierInst(inst, committed_inst);
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index 106b51b..d8c1c7a 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -154,7 +154,7 @@
bool
LSQ::LSQRequest::isBarrier()
{
- return inst->isInst() && inst->staticInst->isMemBarrier();
+ return inst->isInst() && inst->staticInst->isFullMemBarrier();
}
bool
@@ -1711,7 +1711,7 @@
void
LSQ::issuedMemBarrierInst(MinorDynInstPtr inst)
{
- assert(inst->isInst() && inst->staticInst->isMemBarrier());
+ assert(inst->isInst() && inst->staticInst->isFullMemBarrier());
assert(inst->id.execSeqNum > lastMemBarrier[inst->id.threadId]);
/* Remember the barrier. We only have a notion of one
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 75d065f..f6a2e2e 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1196,7 +1196,7 @@
// Make sure we are only trying to commit un-executed instructions we
// think are possible.
assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional()
- || head_inst->isMemBarrier() || head_inst->isWriteBarrier()
+ || head_inst->isReadBarrier() || head_inst->isWriteBarrier()
|| head_inst->isAtomic()
|| (head_inst->isLoad() && head_inst->strictlyOrdered()));
@@ -1233,11 +1233,6 @@
return false;
}
- if (head_inst->isThreadSync()) {
- // Not handled for now.
- panic("Thread sync instructions are not handled yet.\n");
- }
-
// Check if the instruction caused a fault. If so, trap.
Fault inst_fault = head_inst->getFault();
@@ -1467,7 +1462,7 @@
}
}
- if (inst->isMemBarrier()) {
+ if (inst->isFullMemBarrier()) {
stats.membars[tid]++;
}
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 497c532..b39001d 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -1119,7 +1119,7 @@
}
toRename->iewInfo[tid].dispatchedToSQ++;
- } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
+ } else if (inst->isReadBarrier() || inst->isWriteBarrier()) {
// Same as non-speculative stores.
inst->setCanCommit();
instQueue.insertBarrier(inst);
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index ff5b3be..19ed49a 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -1014,7 +1014,7 @@
++freeEntries;
completed_inst->memOpDone(true);
count[tid]--;
- } else if (completed_inst->isMemBarrier() ||
+ } else if (completed_inst->isReadBarrier() ||
completed_inst->isWriteBarrier()) {
// Completes a non mem ref barrier
memDepUnit[tid].completeInst(completed_inst);
@@ -1245,7 +1245,7 @@
DPRINTF(IQ, "[tid:%i] Instruction [sn:%llu] PC %s squashed.\n",
tid, squashed_inst->seqNum, squashed_inst->pcState());
- bool is_acq_rel = squashed_inst->isMemBarrier() &&
+ bool is_acq_rel = squashed_inst->isFullMemBarrier() &&
(squashed_inst->isLoad() ||
(squashed_inst->isStore() &&
!squashed_inst->isStoreConditional()));
@@ -1255,7 +1255,7 @@
(!squashed_inst->isNonSpeculative() &&
!squashed_inst->isStoreConditional() &&
!squashed_inst->isAtomic() &&
- !squashed_inst->isMemBarrier() &&
+ !squashed_inst->isReadBarrier() &&
!squashed_inst->isWriteBarrier())) {
for (int src_reg_idx = 0;
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh b/src/cpu/o3/mem_dep_unit_impl.hh
index 4be98c5..7b83efd 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -44,6 +44,7 @@
#include <map>
#include <vector>
+#include "base/debug.hh"
#include "cpu/o3/inst_queue.hh"
#include "cpu/o3/mem_dep_unit.hh"
#include "debug/MemDepUnit.hh"
@@ -171,24 +172,31 @@
MemDepUnit<MemDepPred, Impl>::insertBarrierSN(const DynInstPtr &barr_inst)
{
InstSeqNum barr_sn = barr_inst->seqNum;
- // Memory barriers block loads and stores, write barriers only stores.
- // Required also for hardware transactional memory commands which
- // can have strict ordering semantics
- if (barr_inst->isMemBarrier() || barr_inst->isHtmCmd()) {
- loadBarrierSNs.insert(barr_sn);
- storeBarrierSNs.insert(barr_sn);
- DPRINTF(MemDepUnit, "Inserted a memory barrier %s SN:%lli\n",
- barr_inst->pcState(), barr_sn);
- } else if (barr_inst->isWriteBarrier()) {
- storeBarrierSNs.insert(barr_sn);
- DPRINTF(MemDepUnit, "Inserted a write barrier %s SN:%lli\n",
- barr_inst->pcState(), barr_sn);
- }
- if (loadBarrierSNs.size() || storeBarrierSNs.size()) {
- DPRINTF(MemDepUnit, "Outstanding load barriers = %d; "
- "store barriers = %d\n",
- loadBarrierSNs.size(), storeBarrierSNs.size());
+ if (barr_inst->isReadBarrier() || barr_inst->isHtmCmd())
+ loadBarrierSNs.insert(barr_sn);
+ if (barr_inst->isWriteBarrier() || barr_inst->isHtmCmd())
+ storeBarrierSNs.insert(barr_sn);
+
+ if (DTRACE(MemDepUnit)) {
+ const char *barrier_type = nullptr;
+ if (barr_inst->isReadBarrier() && barr_inst->isWriteBarrier())
+ barrier_type = "memory";
+ else if (barr_inst->isReadBarrier())
+ barrier_type = "read";
+ else if (barr_inst->isWriteBarrier())
+ barrier_type = "write";
+
+ if (barrier_type) {
+ DPRINTF(MemDepUnit, "Inserted a %s barrier %s SN:%lli\n",
+ barrier_type, barr_inst->pcState(), barr_sn);
+ }
+
+ if (loadBarrierSNs.size() || storeBarrierSNs.size()) {
+ DPRINTF(MemDepUnit, "Outstanding load barriers = %d; "
+ "store barriers = %d\n",
+ loadBarrierSNs.size(), storeBarrierSNs.size());
+ }
}
}
@@ -444,18 +452,27 @@
completed(inst);
InstSeqNum barr_sn = inst->seqNum;
- if (inst->isMemBarrier() || inst->isHtmCmd()) {
+ if (inst->isWriteBarrier() || inst->isHtmCmd()) {
+ assert(hasStoreBarrier());
+ storeBarrierSNs.erase(barr_sn);
+ }
+ if (inst->isReadBarrier() || inst->isHtmCmd()) {
assert(hasLoadBarrier());
- assert(hasStoreBarrier());
loadBarrierSNs.erase(barr_sn);
- storeBarrierSNs.erase(barr_sn);
- DPRINTF(MemDepUnit, "Memory barrier completed: %s SN:%lli\n",
- inst->pcState(), inst->seqNum);
- } else if (inst->isWriteBarrier()) {
- assert(hasStoreBarrier());
- storeBarrierSNs.erase(barr_sn);
- DPRINTF(MemDepUnit, "Write barrier completed: %s SN:%lli\n",
- inst->pcState(), inst->seqNum);
+ }
+ if (DTRACE(MemDepUnit)) {
+ const char *barrier_type = nullptr;
+ if (inst->isWriteBarrier() && inst->isReadBarrier())
+ barrier_type = "Memory";
+ else if (inst->isWriteBarrier())
+ barrier_type = "Write";
+ else if (inst->isReadBarrier())
+ barrier_type = "Read";
+
+ if (barrier_type) {
+ DPRINTF(MemDepUnit, "%s barrier completed: %s SN:%lli\n",
+ barrier_type, inst->pcState(), inst->seqNum);
+ }
}
}
@@ -463,9 +480,8 @@
void
MemDepUnit<MemDepPred, Impl>::wakeDependents(const DynInstPtr &inst)
{
- // Only stores, atomics, barriers and
- // hardware transactional memory commands have dependents.
- if (!inst->isStore() && !inst->isAtomic() && !inst->isMemBarrier() &&
+ // Only stores, atomics and barriers have dependents.
+ if (!inst->isStore() && !inst->isAtomic() && !inst->isReadBarrier() &&
!inst->isWriteBarrier() && !inst->isHtmCmd()) {
return;
}
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 1cbe87a..052012e 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -684,8 +684,7 @@
// instructions. This is mainly due to lack of support for
// out-of-order operations of either of those classes of
// instructions.
- if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
- !inst->isSerializeHandled()) {
+ if (inst->isSerializeBefore() && !inst->isSerializeHandled()) {
DPRINTF(Rename, "Serialize before instruction encountered.\n");
if (!inst->isTempSerializeBefore()) {
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 146be8c..6556170 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -157,7 +157,11 @@
bool isNop() const { return flags[IsNop]; }
- bool isMemRef() const { return flags[IsMemRef]; }
+ bool
+ isMemRef() const
+ {
+ return flags[IsLoad] || flags[IsStore] || flags[IsAtomic];
+ }
bool isLoad() const { return flags[IsLoad]; }
bool isStore() const { return flags[IsStore]; }
bool isAtomic() const { return flags[IsAtomic]; }
@@ -170,7 +174,6 @@
bool isInteger() const { return flags[IsInteger]; }
bool isFloating() const { return flags[IsFloating]; }
bool isVector() const { return flags[IsVector]; }
- bool isCC() const { return flags[IsCC]; }
bool isControl() const { return flags[IsControl]; }
bool isCall() const { return flags[IsCall]; }
@@ -179,20 +182,22 @@
bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
bool isCondCtrl() const { return flags[IsCondControl]; }
bool isUncondCtrl() const { return flags[IsUncondControl]; }
- bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
- bool isThreadSync() const { return flags[IsThreadSync]; }
bool isSerializing() const { return flags[IsSerializing] ||
flags[IsSerializeBefore] ||
flags[IsSerializeAfter]; }
bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
bool isSquashAfter() const { return flags[IsSquashAfter]; }
- bool isMemBarrier() const { return flags[IsMemBarrier]; }
+ bool
+ isFullMemBarrier() const
+ {
+ return flags[IsReadBarrier] && flags[IsWriteBarrier];
+ }
+ bool isReadBarrier() const { return flags[IsReadBarrier]; }
bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
bool isQuiesce() const { return flags[IsQuiesce]; }
- bool isIprAccess() const { return flags[IsIprAccess]; }
bool isUnverifiable() const { return flags[IsUnverifiable]; }
bool isSyscall() const { return flags[IsSyscall]; }
bool isMacroop() const { return flags[IsMacroop]; }
@@ -200,8 +205,6 @@
bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
bool isLastMicroop() const { return flags[IsLastMicroop]; }
bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
- //This flag doesn't do anything yet
- bool isMicroBranch() const { return flags[IsMicroBranch]; }
// hardware transactional memory
// HtmCmds must be identified as such in order
// to provide them with necessary memory ordering semantics.
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index a5730c7..a708c6c 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -45,7 +45,6 @@
#include "arch/locked_mem.hh"
#include "base/loader/memory_image.hh"
#include "base/loader/object_file.hh"
-#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/LLSC.hh"
#include "debug/MemoryAccess.hh"
@@ -346,17 +345,15 @@
tracePacket(System *sys, const char *label, PacketPtr pkt)
{
int size = pkt->getSize();
-#if THE_ISA != NULL_ISA
if (size == 1 || size == 2 || size == 4 || size == 8) {
ByteOrder byte_order = sys->getGuestByteOrder();
- DPRINTF(MemoryAccess,"%s from %s of size %i on address %#x data "
+ DPRINTF(MemoryAccess, "%s from %s of size %i on address %#x data "
"%#x %c\n", label, sys->getRequestorName(pkt->req->
requestorId()), size, pkt->getAddr(),
size, pkt->getAddr(), pkt->getUintX(byte_order),
pkt->req->isUncacheable() ? 'U' : 'C');
return;
}
-#endif
DPRINTF(MemoryAccess, "%s from %s of size %i on address %#x %c\n",
label, sys->getRequestorName(pkt->req->requestorId()),
size, pkt->getAddr(), pkt->req->isUncacheable() ? 'U' : 'C');
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index a35be33..2ff466b 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -48,7 +48,6 @@
#include <cassert>
#include "base/intmath.hh"
-#include "cpu/base.hh"
#include "mem/cache/base.hh"
#include "params/BasePrefetcher.hh"
#include "sim/system.hh"
diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc
index 9464c0d..5b66786 100644
--- a/src/sim/stat_control.cc
+++ b/src/sim/stat_control.cc
@@ -53,7 +53,6 @@
#include "base/hostinfo.hh"
#include "base/statistics.hh"
#include "base/time.hh"
-#include "cpu/base.hh"
#include "sim/global_event.hh"
using namespace std;
@@ -62,6 +61,7 @@
Stats::Value simTicks;
Stats::Value finalTick;
Stats::Value simFreq;
+Stats::Value hostSeconds;
namespace Stats {
@@ -94,36 +94,14 @@
struct Global
{
- Stats::Formula hostInstRate;
- Stats::Formula hostOpRate;
Stats::Formula hostTickRate;
Stats::Value hostMemory;
- Stats::Value hostSeconds;
-
- Stats::Value simInsts;
- Stats::Value simOps;
Global();
};
Global::Global()
{
- simInsts
- .functor(BaseCPU::numSimulatedInsts)
- .name("sim_insts")
- .desc("Number of instructions simulated")
- .precision(0)
- .prereq(simInsts)
- ;
-
- simOps
- .functor(BaseCPU::numSimulatedOps)
- .name("sim_ops")
- .desc("Number of ops (including micro ops) simulated")
- .precision(0)
- .prereq(simOps)
- ;
-
simSeconds
.name("sim_seconds")
.desc("Number of seconds simulated")
@@ -148,20 +126,6 @@
"(restored from checkpoints and never reset)")
;
- hostInstRate
- .name("host_inst_rate")
- .desc("Simulator instruction rate (inst/s)")
- .precision(0)
- .prereq(simInsts)
- ;
-
- hostOpRate
- .name("host_op_rate")
- .desc("Simulator op (including micro ops) rate (op/s)")
- .precision(0)
- .prereq(simOps)
- ;
-
hostMemory
.functor(memUsage)
.name("host_mem_usage")
@@ -183,8 +147,6 @@
;
simSeconds = simTicks / simFreq;
- hostInstRate = simInsts / hostSeconds;
- hostOpRate = simOps / hostSeconds;
hostTickRate = simTicks / hostSeconds;
registerResetCallback([]() {
diff --git a/src/sim/stats.hh b/src/sim/stats.hh
index ed68af6..4e17f64 100644
--- a/src/sim/stats.hh
+++ b/src/sim/stats.hh
@@ -34,5 +34,6 @@
extern Stats::Formula simSeconds;
extern Stats::Value simTicks;
extern Stats::Value simFreq;
+extern Stats::Value hostSeconds;
#endif // __SIM_SIM_STATS_HH__
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 05a29f9..9d1f6e2 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1506,11 +1506,6 @@
desc->returnInto(ctc, 0);
-#if THE_ISA == SPARC_ISA
- tc->setIntReg(TheISA::SyscallPseudoReturnReg, 0);
- ctc->setIntReg(TheISA::SyscallPseudoReturnReg, 1);
-#endif
-
TheISA::PCState cpc = tc->pcState();
if (!p->kvmInSE)
cpc.advance();
diff --git a/src/sim/system.cc b/src/sim/system.cc
index cb412a8..cbc30a9 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -50,12 +50,15 @@
#include "base/loader/symtab.hh"
#include "base/str.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "config/use_kvm.hh"
#if USE_KVM
#include "cpu/kvm/base.hh"
#include "cpu/kvm/vm.hh"
#endif
+#if THE_ISA != NULL_ISA
#include "cpu/base.hh"
+#endif
#include "cpu/thread_context.hh"
#include "debug/Loader.hh"
#include "debug/Quiesce.hh"
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 7d77c48..fc93b85 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -52,7 +52,6 @@
#include "base/loader/symtab.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
-#include "cpu/base.hh"
#include "cpu/pc_event.hh"
#include "enums/MemoryMode.hh"
#include "mem/mem_requestor.hh"
diff --git a/src/systemc/core/list.hh b/src/systemc/core/list.hh
index b1c5f55..6ba2825 100644
--- a/src/systemc/core/list.hh
+++ b/src/systemc/core/list.hh
@@ -102,8 +102,13 @@
prevListNode = t;
}
- T *getNext() { return dynamic_cast<T *>(nextListNode); }
- bool empty() { return getNext() == nullptr; }
+ T *
+ getNext()
+ {
+ return empty() ? nullptr : static_cast<T *>(nextListNode);
+ }
+
+ bool empty() { return nextListNode == this; }
};
} // namespace sc_gem5
