src/mem/mem_delay.cc

/*
 * Copyright (c) 2018 ARM Limited
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 * property including but not limited to intellectual property relating
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 * met: redistributions of source code must retain the above copyright
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 * redistributions in binary form must reproduce the above copyright
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 * this software without specific prior written permission.
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#include "mem/mem_delay.hh"

#include "params/MemDelay.hh"
#include "params/SimpleMemDelay.hh"

MemDelay::MemDelay(const MemDelayParams *p)
    : ClockedObject(p),
      masterPort(name() + "-master", *this),
      slavePort(name() + "-slave", *this),
      reqQueue(*this, masterPort),
      respQueue(*this, slavePort),
      snoopRespQueue(*this, masterPort)
{
}

void
MemDelay::init()
{
    if (!slavePort.isConnected() || !masterPort.isConnected())
        fatal("Memory delay is not connected on both sides.\n");
}


Port &
MemDelay::getPort(const std::string &if_name, PortID idx)
{
    if (if_name == "master") {
        return masterPort;
    } else if (if_name == "slave") {
        return slavePort;
    } else {
        return ClockedObject::getPort(if_name, idx);
    }
}

bool
MemDelay::trySatisfyFunctional(PacketPtr pkt)
{
    return slavePort.trySatisfyFunctional(pkt) ||
        masterPort.trySatisfyFunctional(pkt);
}

MemDelay::MasterPort::MasterPort(const std::string &_name, MemDelay &_parent)
    : QueuedMasterPort(_name, &_parent,
                       _parent.reqQueue, _parent.snoopRespQueue),
      parent(_parent)
{
}

bool
MemDelay::MasterPort::recvTimingResp(PacketPtr pkt)
{
    const Tick when = curTick() + parent.delayResp(pkt);

    parent.slavePort.schedTimingResp(pkt, when);

    return true;
}

void
MemDelay::MasterPort::recvFunctionalSnoop(PacketPtr pkt)
{
    if (parent.trySatisfyFunctional(pkt)) {
        pkt->makeResponse();
    } else {
        parent.slavePort.sendFunctionalSnoop(pkt);
    }
}

Tick
MemDelay::MasterPort::recvAtomicSnoop(PacketPtr pkt)
{
    const Tick delay = parent.delaySnoopResp(pkt);

    return delay + parent.slavePort.sendAtomicSnoop(pkt);
}

void
MemDelay::MasterPort::recvTimingSnoopReq(PacketPtr pkt)
{
    parent.slavePort.sendTimingSnoopReq(pkt);
}


MemDelay::SlavePort::SlavePort(const std::string &_name, MemDelay &_parent)
    : QueuedSlavePort(_name, &_parent, _parent.respQueue),
      parent(_parent)
{
}

Tick
MemDelay::SlavePort::recvAtomic(PacketPtr pkt)
{
    const Tick delay = parent.delayReq(pkt) + parent.delayResp(pkt);

    return delay + parent.masterPort.sendAtomic(pkt);
}

bool
MemDelay::SlavePort::recvTimingReq(PacketPtr pkt)
{
    const Tick when = curTick() + parent.delayReq(pkt);

    parent.masterPort.schedTimingReq(pkt, when);

    return true;
}

void
MemDelay::SlavePort::recvFunctional(PacketPtr pkt)
{
    if (parent.trySatisfyFunctional(pkt)) {
        pkt->makeResponse();
    } else {
        parent.masterPort.sendFunctional(pkt);
    }
}

bool
MemDelay::SlavePort::recvTimingSnoopResp(PacketPtr pkt)
{
    const Tick when = curTick() + parent.delaySnoopResp(pkt);

    parent.masterPort.schedTimingSnoopResp(pkt, when);

    return true;
}



SimpleMemDelay::SimpleMemDelay(const SimpleMemDelayParams *p)
    : MemDelay(p),
      readReqDelay(p->read_req),
      readRespDelay(p->read_resp),
      writeReqDelay(p->write_req),
      writeRespDelay(p->write_resp)
{
}

Tick
SimpleMemDelay::delayReq(PacketPtr pkt)
{
    if (pkt->isRead()) {
        return readReqDelay;
    } else if (pkt->isWrite()) {
        return writeReqDelay;
    } else {
        return 0;
    }
}

Tick
SimpleMemDelay::delayResp(PacketPtr pkt)
{
    if (pkt->isRead()) {
        return readRespDelay;
    } else if (pkt->isWrite()) {
        return writeRespDelay;
    } else {
        return 0;
    }
}


SimpleMemDelay *
SimpleMemDelayParams::create()
{
    return new SimpleMemDelay(this);
}