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# Copyright (c) 2022 Fraunhofer IESE
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import m5
from m5.objects import (
DRAMSys,
AddrRange,
Port,
MemCtrl,
Gem5ToTlmBridge32,
SystemC_Kernel,
)
from m5.util.convert import toMemorySize
from ...utils.override import overrides
from ..boards.abstract_board import AbstractBoard
from .abstract_memory_system import AbstractMemorySystem
from typing import Tuple, Sequence, List
class DRAMSysMem(AbstractMemorySystem):
def __init__(
self,
configuration: str,
size: str,
resource_directory: str,
recordable: bool,
) -> None:
"""
:param configuration: Path to the base configuration JSON for DRAMSys.
:param size: Memory size of DRAMSys. Must match the size specified in JSON configuration.
:param resource_directory: Path to the base resource directory for DRAMSys.
:param recordable: Whether the database recording feature of DRAMSys is enabled.
"""
super().__init__()
self.dramsys = DRAMSys(
configuration=configuration,
resource_directory=resource_directory,
recordable=recordable,
)
self._size = toMemorySize(size)
self.bridge = Gem5ToTlmBridge32()
self.dramsys.tlm = self.bridge.tlm
self.kernel = SystemC_Kernel()
@overrides(AbstractMemorySystem)
def incorporate_memory(self, board: AbstractBoard) -> None:
pass
@overrides(AbstractMemorySystem)
def get_mem_ports(self) -> Sequence[Tuple[AddrRange, Port]]:
return [(self.dramsys.range, self.bridge.gem5)]
@overrides(AbstractMemorySystem)
def get_memory_controllers(self) -> List[MemCtrl]:
return [self.dramsys]
@overrides(AbstractMemorySystem)
def get_size(self) -> int:
return self._size
@overrides(AbstractMemorySystem)
def set_memory_range(self, ranges: List[AddrRange]) -> None:
if len(ranges) != 1 or ranges[0].size() != self._size:
raise Exception(
"DRAMSys memory controller requires a single "
"range which matches the memory's size."
)
self.dramsys.range = ranges[0]
self.bridge.addr_ranges = ranges[0]
class DRAMSysDDR4_1866(DRAMSysMem):
def __init__(self, recordable: bool):
"""
:param recordable: Whether the database recording feature of DRAMSys is enabled.
"""
super().__init__(
configuration="ext/dramsys/DRAMSys/DRAMSys/"
"library/resources/simulations/ddr4-example.json",
size="4GB",
resource_directory="ext/dramsys/DRAMSys/DRAMSys/library/resources",
recordable=recordable,
)
class DRAMSysDDR3_1600(DRAMSysMem):
def __init__(self, recordable: bool):
"""
:param recordable: Whether the database recording feature of DRAMSys is enabled.
"""
super().__init__(
configuration="ext/dramsys/DRAMSys/DRAMSys/"
"library/resources/simulations/ddr3-gem5-se.json",
size="4GB",
resource_directory="ext/dramsys/DRAMSys/DRAMSys/library/resources",
recordable=recordable,
)
class DRAMSysLPDDR4_3200(DRAMSysMem):
def __init__(self, recordable: bool):
"""
:param recordable: Whether the database recording feature of DRAMSys is enabled.
"""
super().__init__(
configuration="ext/dramsys/DRAMSys/DRAMSys/"
"library/resources/simulations/lpddr4-example.json",
size="4GB",
resource_directory="ext/dramsys/DRAMSys/DRAMSys/library/resources",
recordable=recordable,
)
class DRAMSysHBM2(DRAMSysMem):
def __init__(self, recordable: bool):
"""
:param recordable: Whether the database recording feature of DRAMSys is enabled.
"""
super().__init__(
configuration="ext/dramsys/DRAMSys/DRAMSys/"
"library/resources/simulations/hbm2-example.json",
size="4GB",
resource_directory="ext/dramsys/DRAMSys/DRAMSys/library/resources",
recordable=recordable,
)