src/arch/arm/isa_device.cc

/*
 * Copyright (c) 2014,2017 ARM Limited
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 *
 * The license below extends only to copyright in the software and shall
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 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
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 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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#include "arch/arm/isa_device.hh"

#include "arch/arm/regs/misc.hh"
#include "base/logging.hh"

namespace gem5
{

namespace ArmISA
{

BaseISADevice::BaseISADevice()
    : isa(nullptr)
{
}

void
BaseISADevice::setISA(ISA *_isa)
{
    assert(_isa);

    isa = _isa;
}

void
DummyISADevice::setMiscReg(int misc_reg, RegVal val)
{
    warn("Ignoring write of 0x%lx to miscreg %s\n",
          val,
          miscRegName[misc_reg]);
}

RegVal
DummyISADevice::readMiscReg(int misc_reg)
{
    warn("Returning zero for read from miscreg %s\n", miscRegName[misc_reg]);

    return 0;
}

} // namespace ArmISA
} // namespace gem5