src/arch/mips/isa/operands.isa

// -*- mode:c++ -*-

// Copyright (c) 2007 MIPS Technologies, Inc.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

def operand_types {{
    'sb' : 'int8_t',
    'ub' : 'uint8_t',
    'sh' : 'int16_t',
    'uh' : 'uint16_t',
    'sw' : 'int32_t',
    'uw' : 'uint32_t',
    'sd' : 'int64_t',
    'ud' : 'uint64_t',
    'sf' : 'float',
    'df' : 'double'
}};

let {{
    class IntReg(IntRegOp):
        @overrideInOperand
        def regId(self):
            return f'(({self.reg_spec}) == 0) ? RegId() : ' \
                   f'{self.reg_class}[{self.reg_spec}]'
}};

def operands {{
    #General Purpose Integer Reg Operands
    'Rd': IntReg('uw', 'RD', 'IsInteger', 1),
    'Rs': IntReg('uw', 'RS', 'IsInteger', 2),
    'Rt': IntReg('uw', 'RT', 'IsInteger', 3),

    #Immediate Value operand
    'IntImm': IntReg('uw', 'INTIMM', 'IsInteger', 3),

    #Operands used for Link Insts
    'R31': IntReg('uw', '31', 'IsInteger', 4),

    #Special Integer Reg operands
    'LO0':  IntReg('uw', 'int_reg::Lo', 'IsInteger', 6),
    'HI0':  IntReg('uw', 'int_reg::Hi', 'IsInteger', 7),

    #Bitfield-dependent HI/LO Register Access
    'LO_RD_SEL': IntReg('uw', 'int_reg::DspLo0 + ACDST*3', None, 6),
    'HI_RD_SEL': IntReg('uw', 'int_reg::DspHi0 + ACDST*3', None, 7),
    'LO_RS_SEL': IntReg('uw', 'int_reg::DspLo0 + ACSRC*3', None, 6),
    'HI_RS_SEL': IntReg('uw', 'int_reg::DspHi0 + ACSRC*3', None, 7),

    #DSP Special Purpose Integer Operands
    'DSPControl': IntReg('uw', 'int_reg::DspControl', None, 8),
    'DSPLo0': IntReg('uw', 'int_reg::Lo', None, 1),
    'DSPHi0': IntReg('uw', 'int_reg::Hi', None, 1),
    'DSPACX0': IntReg('uw', 'int_reg::DspAcx0', None, 1),
    'DSPLo1': IntReg('uw', 'int_reg::DspLo1', None, 1),
    'DSPHi1': IntReg('uw', 'int_reg::DspHi1', None, 1),
    'DSPACX1': IntReg('uw', 'int_reg::DspAcx1', None, 1),
    'DSPLo2': IntReg('uw', 'int_reg::DspLo2', None, 1),
    'DSPHi2': IntReg('uw', 'int_reg::DspHi2', None, 1),
    'DSPACX2': IntReg('uw', 'int_reg::DspAcx2', None, 1),
    'DSPLo3': IntReg('uw', 'int_reg::DspLo3', None, 1),
    'DSPHi3': IntReg('uw', 'int_reg::DspHi3', None, 1),
    'DSPACX3': IntReg('uw', 'int_reg::DspAcx3', None, 1),

    #Floating Point Reg Operands
    'Fd': FloatRegOp('sf', 'FD', 'IsFloating', 1),
    'Fs': FloatRegOp('sf', 'FS', 'IsFloating', 2),
    'Ft': FloatRegOp('sf', 'FT', 'IsFloating', 3),
    'Fr': FloatRegOp('sf', 'FR', 'IsFloating', 3),

    #Special Purpose Floating Point Control Reg Operands
    'FIR':  FloatRegOp('uw', 'float_reg::Fir', 'IsFloating', 1),
    'FCCR': FloatRegOp('uw', 'float_reg::Fccr', 'IsFloating', 2),
    'FEXR': FloatRegOp('uw', 'float_reg::Fexr', 'IsFloating', 3),
    'FENR': FloatRegOp('uw', 'float_reg::Fenr', 'IsFloating', 3),
    'FCSR': FloatRegOp('uw', 'float_reg::Fcsr', 'IsFloating', 3),

    #Operands For Paired Singles FP Operations
    'Fd1': FloatRegOp('sf', 'FD', 'IsFloating', 4),
    'Fd2': FloatRegOp('sf', 'FD+1', 'IsFloating', 4),
    'Fs1': FloatRegOp('sf', 'FS', 'IsFloating', 5),
    'Fs2': FloatRegOp('sf', 'FS+1', 'IsFloating', 5),
    'Ft1': FloatRegOp('sf', 'FT', 'IsFloating', 6),
    'Ft2': FloatRegOp('sf', 'FT+1', 'IsFloating', 6),
    'Fr1': FloatRegOp('sf', 'FR', 'IsFloating', 7),
    'Fr2': FloatRegOp('sf', 'FR+1', 'IsFloating', 7),

    #Status Control Reg
    'Status': ControlRegOp('uw', 'misc_reg::Status', None, 1),

    #LL Flag
    'LLFlag': ControlRegOp('uw', 'misc_reg::Llflag', None, 1),

    #Thread pointer value for SE mode
    'TpValue': ControlRegOp('ud', 'misc_reg::TpValue', None, 1),

    # Index Register
    'Index': ControlRegOp('uw','misc_reg::Index',None,1),


    'CP0_RD_SEL': ControlRegOp('uw', '(RD << 3 | SEL)', None, 1),

    #MT Control Regs
    'MVPConf0': ControlRegOp('uw', 'misc_reg::MvpConf0', None, 1),
    'MVPControl': ControlRegOp('uw', 'misc_reg::MvpControl', None, 1),
    'TCBind': ControlRegOp('uw', 'misc_reg::TcBind', None, 1),
    'TCStatus': ControlRegOp('uw', 'misc_reg::TcStatus', None, 1),
    'TCRestart': ControlRegOp('uw', 'misc_reg::TcRestart', None, 1),
    'VPEConf0': ControlRegOp('uw', 'misc_reg::VpeConf0', None, 1),
    'VPEControl': ControlRegOp('uw', 'misc_reg::VpeControl', None, 1),
    'YQMask': ControlRegOp('uw', 'misc_reg::Yqmask', None, 1),

    #CP0 Control Regs
    'EntryHi': ControlRegOp('uw', 'misc_reg::Entryhi',None,1),
    'EntryLo0': ControlRegOp('uw', 'misc_reg::Entrylo0',None,1),
    'EntryLo1': ControlRegOp('uw', 'misc_reg::Entrylo1',None,1),
    'PageMask': ControlRegOp('uw', 'misc_reg::Pagemask',None,1),
    'Random': ControlRegOp('uw', 'misc_reg::Cp0Random',None,1),
    'ErrorEPC': ControlRegOp('uw', 'misc_reg::ErrorEpc',None,1),
    'EPC': ControlRegOp('uw', 'misc_reg::Epc',None,1),
    'DEPC': ControlRegOp('uw', 'misc_reg::Depc',None,1),
    'IntCtl': ControlRegOp('uw', 'misc_reg::Intctl',None,1),
    'SRSCtl': ControlRegOp('uw', 'misc_reg::Srsctl',None,1),
    'Config': ControlRegOp('uw', 'misc_reg::Config',None,1),
    'Config3': ControlRegOp('uw', 'misc_reg::Config3',None,1),
    'Config1': ControlRegOp('uw', 'misc_reg::Config1',None,1),
    'Config2': ControlRegOp('uw', 'misc_reg::Config2',None,1),
    'PageGrain': ControlRegOp('uw', 'misc_reg::Pagegrain',None,1),
    'Debug': ControlRegOp('uw', 'misc_reg::Debug',None,1),
    'Cause': ControlRegOp('uw', 'misc_reg::Cause',None,1),

    #Memory Operand
    'Mem': MemOp('uw', None, (None, 'IsLoad', 'IsStore'), 4),

    #Program Counter Operands
    'PC': PCStateOp('uw', 'pc', (None, None, 'IsControl'), 4),
    'NPC': PCStateOp('uw', 'npc', (None, None, 'IsControl'), 4),
    'NNPC': PCStateOp('uw', 'nnpc', (None, None, 'IsControl'), 4)
}};