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/*
* Copyright 2022 Google Inc.
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* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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#include "arch/x86/bare_metal/workload.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/pcstate.hh"
#include "cpu/thread_context.hh"
#include "params/X86BareMetalWorkload.hh"
#include "sim/system.hh"
namespace gem5
{
namespace X86ISA
{
BareMetalWorkload::BareMetalWorkload(const Params &p) : Workload(p)
{}
void
BareMetalWorkload::initState()
{
Workload::initState();
for (auto *tc: system->threads) {
X86ISA::InitInterrupt(0).invoke(tc);
if (tc->contextId() == 0) {
PCState pc = tc->pcState().as<PCState>();
// Don't start in the microcode ROM which would halt this CPU.
pc.upc(0);
pc.nupc(1);
tc->pcState(pc);
tc->activate();
} else {
// This is an application processor (AP). It should be initialized
// to look like only the BIOS POST has run on it and put then put
// it into a halted state.
tc->suspend();
}
}
}
} // namespace X86ISA
} // namespace gem5