blob: 40f61608d87d7a5dbcce1979a5d47dffe706071f [file] [log] [blame]
# Copyright (c) 2013 ARM Limited
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#
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from m5.params import *
from m5.objects.AbstractMemory import *
# A wrapper for DRAMSim3 multi-channel memory controller
class DRAMsim3(AbstractMemory):
type = "DRAMsim3"
cxx_header = "mem/dramsim3.hh"
cxx_class = "gem5::memory::DRAMsim3"
# A single port for now
port = ResponsePort(
"port for receiving requests fromthe CPU or other requestor"
)
configFile = Param.String(
"ext/dramsim3/DRAMsim3/configs/DDR4_8Gb_x8_2400.ini",
"The configuration file to use with DRAMSim3",
)
filePath = Param.String(
"ext/dramsim3/DRAMsim3/", "Directory to prepend to file names"
)