| # Copyright (c) 2022 The Regents of the University of California |
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| |
| from m5.params import * |
| from m5.proxy import * |
| from m5.objects.MemCtrl import * |
| |
| # HBMCtrl manages two pseudo channels of HBM2 |
| |
| |
| class HBMCtrl(MemCtrl): |
| type = "HBMCtrl" |
| cxx_header = "mem/hbm_ctrl.hh" |
| cxx_class = "gem5::memory::HBMCtrl" |
| |
| # HBMCtrl uses the SimpleMemCtlr's interface |
| # `dram` as the first pseudo channel, the second |
| # pseudo channel interface is following |
| # HBMCtrl has been tested with two HBM_2000_4H_1x64 interfaces |
| dram_2 = Param.DRAMInterface("DRAM memory interface") |
| |
| # For mixed traffic, HBMCtrl with HBM_2000_4H_1x64 interfaaces |
| # gives the best results with following min_r/w_per_switch |
| min_reads_per_switch = 64 |
| min_writes_per_switch = 64 |