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Andreas Sandberg0f33b2c2018-05-02 13:55:10 +01001/*
2 * Copyright (c) 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +010036 */
37
38#ifndef __MEM_MEM_DELAY_HH__
39#define __MEM_MEM_DELAY_HH__
40
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +010041#include "mem/qport.hh"
Gabe Blackcdcc55a2019-04-22 19:45:10 -070042#include "sim/clocked_object.hh"
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +010043
Daniel R. Carvalho974a47d2021-05-09 12:32:07 -030044namespace gem5
45{
46
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +010047struct MemDelayParams;
48struct SimpleMemDelayParams;
49
50/**
51 * This abstract component provides a mechanism to delay
52 * packets. It can be spliced between arbitrary ports of the memory
53 * system and delays packets that pass through it.
54 *
55 * Specialisations of this abstract class should override at least one
56 * of delayReq, delayResp, deleySnoopReq, delaySnoopResp. These
57 * methods receive a PacketPtr as their argument and return a delay in
58 * Ticks. The base class implements an infinite buffer to hold delayed
59 * packets until they are ready. The intention is to use this
60 * component for rapid prototyping of other memory system components
61 * that introduce a packet processing delays.
62 *
63 * NOTE: Packets may be reordered if the delays aren't constant.
64 */
Gabe Blackcdcc55a2019-04-22 19:45:10 -070065class MemDelay : public ClockedObject
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +010066{
67
68 public:
Gabe Black91d83cc2020-10-07 06:49:23 -070069 MemDelay(const MemDelayParams &params);
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +010070
71 void init() override;
72
Gabe Blackd3d24832019-03-07 03:02:35 -080073 protected: // Port interface
74 Port &getPort(const std::string &if_name,
75 PortID idx=InvalidPortID) override;
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +010076
Shivani Parekh392c1ce2020-08-24 11:47:44 -070077 class RequestPort : public QueuedRequestPort
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +010078 {
79 public:
Shivani Parekhcf43bc32020-08-05 17:35:08 -070080 RequestPort(const std::string &_name, MemDelay &_parent);
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +010081
82 protected:
83 bool recvTimingResp(PacketPtr pkt) override;
84
85 void recvFunctionalSnoop(PacketPtr pkt) override;
86
87 Tick recvAtomicSnoop(PacketPtr pkt) override;
88
89 void recvTimingSnoopReq(PacketPtr pkt) override;
90
91 void recvRangeChange() override {
Shivani Parekh392c1ce2020-08-24 11:47:44 -070092 parent.responsePort.sendRangeChange();
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +010093 }
94
95 bool isSnooping() const override {
Shivani Parekh392c1ce2020-08-24 11:47:44 -070096 return parent.responsePort.isSnooping();
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +010097 }
98
99 private:
100 MemDelay& parent;
101 };
102
Shivani Parekh392c1ce2020-08-24 11:47:44 -0700103 class ResponsePort : public QueuedResponsePort
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +0100104 {
105 public:
Shivani Parekhcf43bc32020-08-05 17:35:08 -0700106 ResponsePort(const std::string &_name, MemDelay &_parent);
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +0100107
108 protected:
109 Tick recvAtomic(PacketPtr pkt) override;
110 bool recvTimingReq(PacketPtr pkt) override;
111 void recvFunctional(PacketPtr pkt) override;
112 bool recvTimingSnoopResp(PacketPtr pkt) override;
113
114 AddrRangeList getAddrRanges() const override {
Shivani Parekh392c1ce2020-08-24 11:47:44 -0700115 return parent.requestPort.getAddrRanges();
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +0100116 }
117
118 bool tryTiming(PacketPtr pkt) override { return true; }
119
120 private:
121
122 MemDelay& parent;
123
124 };
125
Robert Kovacsics2f170622018-07-19 18:56:06 +0100126 bool trySatisfyFunctional(PacketPtr pkt);
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +0100127
Shivani Parekh392c1ce2020-08-24 11:47:44 -0700128 RequestPort requestPort;
129 ResponsePort responsePort;
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +0100130
131 ReqPacketQueue reqQueue;
132 RespPacketQueue respQueue;
133 SnoopRespPacketQueue snoopRespQueue;
134
135 protected:
136 /**
137 * Delay a request by some number of ticks.
138 *
139 * @return Ticks to delay packet.
140 */
141 virtual Tick delayReq(PacketPtr pkt) { return 0; }
142
143 /**
144 * Delay a response by some number of ticks.
145 *
146 * @return Ticks to delay packet.
147 */
148 virtual Tick delayResp(PacketPtr pkt) { return 0; }
149
150 /**
151 * Delay a snoop response by some number of ticks.
152 *
153 * @return Ticks to delay packet.
154 */
155 virtual Tick delaySnoopResp(PacketPtr pkt) { return 0; }
156};
157
158/**
159 * Delay packets by a constant time. Delays can be specified
160 * separately for read requests, read responses, write requests, and
161 * write responses.
162 *
163 * This class does not delay snoops or requests/responses that are
164 * neither reads or writes.
165 */
166class SimpleMemDelay : public MemDelay
167{
168 public:
Gabe Black91d83cc2020-10-07 06:49:23 -0700169 SimpleMemDelay(const SimpleMemDelayParams &params);
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +0100170
171 protected:
172 Tick delayReq(PacketPtr pkt) override;
173 Tick delayResp(PacketPtr pkt) override;
174
175 protected: // Params
176 const Tick readReqDelay;
177 const Tick readRespDelay;
178
179 const Tick writeReqDelay;
180 const Tick writeRespDelay;
181};
182
Daniel R. Carvalho974a47d2021-05-09 12:32:07 -0300183} // namespace gem5
184
Andreas Sandberg0f33b2c2018-05-02 13:55:10 +0100185#endif //__MEM_MEM_DELAY_HH__