1. 9a1eb7a Revert "cpu: stop scheduling suspended threads in MinorCPU" by Giacomo Travaglini · 8 months ago
  2. 9852c5d Revert "cpu: fix branching when thread is suspended in MinorCPU" by Giacomo Travaglini · 8 months ago
  3. c1bd279 mem-cache: Use SatCounter for prefetchers by Daniel · 6 months ago
  4. 50a533f base: Add operators to SatCounter by Daniel · 6 months ago
  5. 5b3f91d base: Add GTest to SatCounter by Daniel · 6 months ago
  6. 578dd47 base: Move SatCounter to base directory by Daniel · 6 months ago
  7. 0def916 cpu: Revamp saturating counters by Daniel · 6 months ago
  8. e541767 config: add an option to list and select indirect branch predictor by Jairo Balart · 9 months ago
  9. 0473f8f cpu: Make the indirect predictor into a SimObject by Jairo Balart · 9 months ago
  10. 1291015 mem-ruby: Replace string parameter in MultiBitSelBloomFilter by Daniel R. Carvalho · 5 months ago
  11. 8ddec45 arch-arm: Add initial support for SVE contiguous loads/stores by Giacomo Gabrielli · 2 years ago
  12. c58cb8c cpu,mem: Add support for partial loads/stores and wide mem. accesses by Giacomo Gabrielli · 2 years, 3 months ago
  13. d0e4cdc cpu: Add a memory access predicate by Giacomo Gabrielli · 12 months ago
  14. c4bc234 config, sim-se: bugfix for 54c77aa0 by Brandon Potter · 5 months ago
  15. f14a6d7 configs: Fix FileSystemConfig import by Daniel R. Carvalho · 5 months ago
  16. 436d803 tests: Fix import scope of test by Daniel R. Carvalho · 5 months ago
  17. 8c34a1a mem-ruby: Fix MOESI_CMP_directory blocked line handling by Tiago Muck · 9 months ago
  18. bf0a722 mem-cache: Remove writebacks packet list by Daniel R. Carvalho · 6 months ago
  19. e54c7a6 mem-cache: Handle data expansion by Daniel R. Carvalho · 1 year, 2 months ago
  20. 273aacf mem-cache: Add co-allocation function to compressed tags by Daniel R. Carvalho · 1 year, 4 months ago
  21. a39af1f mem-cache: Add compression and decompression calls by Daniel R. Carvalho · 1 year, 4 months ago
  22. 77a4986 mem-cache: Create BDI Compressor by Daniel R. Carvalho · 1 year, 4 months ago
  23. 0e276f6 mem-cache: Add compression stats by Daniel R. Carvalho · 1 year, 5 months ago
  24. f21f4a0 mem-cache: Create cache compressor by Daniel R. Carvalho · 1 year, 4 months ago
  25. 4b6b068 mem-cache: Add block size to findVictim by Daniel R. Carvalho · 1 year, 4 months ago
  26. 784642b mem-cache: Add compression data to CompressionBlk by Daniel R. Carvalho · 1 year, 7 months ago
  27. bba32e6 mem-cache: Create CacheComp debug flag by Daniel R. Carvalho · 1 year, 5 months ago
  28. e22a6c9 mem-cache: Stub compression framework by Daniel R. Carvalho · 1 year, 5 months ago
  29. 6bf8508 x86: Mark translation as delayed in case of a hw page table walk by Gabor Dozsa · 6 months ago
  30. 7a00e9d sim-se: correct statfs inclusion on !linux host by Andrea Mondelli · 5 months ago
  31. 53e7469 arch-riscv: Implement MHARTID CSR by Alec Roelke · 8 months ago
  32. f75351a sim-se: fix a few bugs/warns from GCC 6 by Joe Gross · 1 year, 6 months ago
  33. d692552 sim-se: add eventfd system call by Brandon Potter · 1 year, 6 months ago
  34. 64687ee mem-cache: Mark block as dirty after a SWPrefetchEXResp by Nikos Nikoleris · 7 months ago
  35. b4b487e arch-riscv,isa: Fix for compressed jump (c_j) imm by Avishai Tvila · 6 months ago
  36. b6d60e8 dev: StreamID generation in DMA device by Giacomo Travaglini · 9 months ago
  37. 6af360e tests: There is no architecture called "timing". by Gabe Black · 6 months ago
  38. 49a71ca dev-arm: Store a PhysProxy port in Gicv3Redist by Giacomo Travaglini · 6 months ago
  39. 3762721 dev-arm: Add named variable for GICD_TYPER.IDBits by Giacomo Travaglini · 6 months ago
  40. 5c89117 dev-arm: Read correct version of ICC_BPR register by Giacomo Travaglini · 6 months ago
  41. 5f29ec8 dev-arm: Get a Gicv3Redistributor ptr from phys address by Giacomo Travaglini · 6 months ago
  42. 68f2f1c dev-arm: Add several LPI methods in Gicv3Redistributor by Giacomo Travaglini · 6 months ago
  43. c16b504 dev-arm: Take LPIs into account when interacting with CPUIF regs by Giacomo Travaglini · 6 months ago
  44. 7ad6c80 dev-arm: Fix GICv3 LPIs priority value by Giacomo Travaglini · 6 months ago
  45. a4f3016 dev-arm: Disable LPI Configuration Table caching by Giacomo Travaglini · 6 months ago
  46. afce686 dev-arm: Check EnableLPIs before checking for pending LPIs by Giacomo Travaglini · 6 months ago
  47. bc300d3 dev-arm: GICv3 LPI tables are using physical addresses by Giacomo Travaglini · 6 months ago
  48. 2df87bc dev-arm: Fix GICv3 LPI loop by Giacomo Travaglini · 6 months ago
  49. 9de1f75 dev-arm: Fix Bitwise operation in GICv3 by Giacomo Travaglini · 6 months ago
  50. 308a06c tests: Add missing kernels to system creation by Daniel R. Carvalho · 6 months ago
  51. 12eab3e arch: Stop using TheISA within the ISAs. by Gabe Black · 6 months ago
  52. ecd6be3 x86: Get rid of some unnecessary TheISA-es in x86. by Gabe Black · 6 months ago
  53. 90f90b8 sparc: Move translation constants from isa_traits.hh into tlb.hh. by Gabe Black · 6 months ago
  54. f19884d sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh. by Gabe Black · 6 months ago
  55. 52031e1 arch: Remove the mt.hh switching header. by Gabe Black · 6 months ago
  56. dc9f1a2 cpu: alpha: Delete all occurrances of the simPalCheck function. by Gabe Black · 6 months ago
  57. e9e3fdc alpha: Implement simPalCheck within the ISA description. by Gabe Black · 6 months ago
  58. 40cc7cd cpu: Remove hwrei from the generic interfaces. by Gabe Black · 6 months ago
  59. 0eb763c sim-se: use DPRINTF_SYSCALL for ioctl/wait4 by Alexandru Dutu · 1 year, 6 months ago
  60. 87ea5ee sim-se: bugfix for 54c77aa055e by Brandon Potter · 6 months ago
  61. eea1fb6 arch: cpu: Track kernel stats using the base ISA agnostic type. by Gabe Black · 6 months ago
  62. f9b7247 alpha: Implement HWREI in the ISA. by Gabe Black · 6 months ago
  63. 2268d07 alpha: Add some control registers to the ISA operands list. by Gabe Black · 6 months ago
  64. 081da0f sim-se: add socket ioctls by Brandon Potter · 1 year, 6 months ago
  65. ca3dd50 systemc: Add a distinct async_request_update mechanism. by Gabe Black · 6 months ago
  66. 88fc141 cpu: Get rid of the (read|set)RegOtherThread methods. by Gabe Black · 6 months ago
  67. a632ee7 mips: Implement readRegOtherThread and setRegOtherThread directly. by Gabe Black · 6 months ago
  68. a4d7473 cpu: Include debug flags regardless of whether the ISA is null. by Gabe Black · 6 months ago
  69. 5ad8040 sim-se: create Proc out files in out dir by Steve Reinhardt · 1 year, 6 months ago
  70. ae89162 arch-arm: Faults DebugFlag now printing inst opcode if available by Giacomo Travaglini · 8 months ago
  71. 529284b arch-arm: Report real instruction encoding when Undefined by Giacomo Travaglini · 8 months ago
  72. 9305bb6 arch, sim: Simplify the AuxVector type. by Gabe Black · 6 months ago
  73. fce9c7a mem: Remove the ISA specialized versions of port proxy's read/write. by Gabe Black · 6 months ago
  74. cdcc55a mem: Minimize the use of MemObject. by Gabe Black · 6 months ago
  75. 3cfff85 python: Get rid of the VectorPort constructor. by Gabe Black · 6 months ago
  76. 6b87ee1 python: Replace the Master/Slave Ports with Request/Response ports. by Gabe Black · 6 months ago
  77. f5ea783 arch-arm: updateMiscReg not setting isHyp in aarch64 by Giacomo Travaglini · 7 months ago
  78. a5f06ab arm: Factor some repetition out of the ProcessInfo constructor. by Gabe Black · 6 months ago
  79. 488ded0 arm: Fix some style issues in stacktrace.cc. by Gabe Black · 6 months ago
  80. 50311fe x86: Refactor the ProcessInfo constructor. by Gabe Black · 6 months ago
  81. ae3a00c configs: faux-filesystem fix w/ ruby in se mode by David Hashe · 1 year, 6 months ago
  82. 26e8889 x86: Fix some style issues in stacktrace.cc. by Gabe Black · 6 months ago
  83. 54c77aa sim-se: add a faux-filesystem by David Hashe · 1 year, 6 months ago
  84. e8d0b75 arch-arm: Remove un-needed hyp flag in TLBI operations by Giacomo Travaglini · 6 months ago
  85. 670d080 arch-arm: Correct target EL field in TLBI operations by Giacomo Travaglini · 6 months ago
  86. 40018b1 dev-arm: Move GICv3 (Re)Ditributor address in Realview.py by Giacomo Travaglini · 6 months ago
  87. ed48d74 dev-arm: Limit number of max PE in GICv3 to 128 by Giacomo Travaglini · 6 months ago
  88. 84c4fd0 dev-arm: Add GICv4 extension switch in GICv3 by Giacomo Travaglini · 6 months ago
  89. c366e19 dev-arm: Check for maximum number of supported PE in GICv3 by Giacomo Travaglini · 6 months ago
  90. 8f010ce config: Add flag options to set the hardware prefetchers to use by Javier Bueno · 7 months ago
  91. 57667ba cpu,mem: missing override specifier by Andrea Mondelli · 6 months ago
  92. e52e6cc systemc: Use the new TLM socket types in the TLM bridge SimObjects. by Gabe Black · 6 months ago
  93. e76777d systemc: Add Port types for initiator and target sockets. by Gabe Black · 6 months ago
  94. 77201c8 dev: Use the new Port role mechanism to make an EtherInt Port type. by Gabe Black · 6 months ago
  95. 3c3f360 python: Generalize the Port.splice function. by Gabe Black · 6 months ago
  96. 9c23850 python: Generalize the dot_writer to handle non Master/Slave roles. by Gabe Black · 6 months ago
  97. e69cce7 python: Make Port roles a more generic concept. by Gabe Black · 6 months ago
  98. 325acb7 python: fix tracing after Python 3 refactor by Ciro Santilli · 6 months ago
  99. c5b3db6 sim-se: Enhance clone for X86KvmCPU by Alexandru Dutu · 6 months ago
  100. 382263c mem-cache: Fix fix of replacement count by Daniel · 6 months ago