- 0f50b62 dev-arm: Remove un-needed Q_CONS_PROD_MASK macro by Giacomo Travaglini · 4 years, 10 months ago
- f82f1dd dev-arm: drain implementation for SMMUv3 by Adrian Herrera · 4 years, 10 months ago
- 09bc8b6 dev-arm: pending SMMU transl update on constructor/destructor by Adrian Herrera · 4 years, 10 months ago
- af8d107 configs: Fix NULL dram-lowp regressions by Giacomo Travaglini · 4 years, 10 months ago
- a2f0167 python: Add support for exporting static class methods from c++ by Nikos Nikoleris · 5 years ago
- b510f95 misc: dot_writer fixup by Tiago Muck · 5 years ago
- d00aa36 python: Fix AddrRange legacy ParamValue wrapper by Nikos Nikoleris · 4 years, 11 months ago
- 8e3164a arch-arm: Move the memacc_code before op_wb in fp loads by Giacomo Travaglini · 4 years, 11 months ago
- d3accb8 dev-arm: Reapply GICv3 changes that were lost during refactoring by Giacomo Travaglini · 5 years ago
- 1500994 base: AddrRange does not merge single interleaved ranges by Tiago Muck · 5 years ago
- b871f12 cpu: Additional TrafficGen stats by Tiago Muck · 5 years ago
- 8be59c2 cpu: Limit TrafficGen outstanding reqs by Tiago Muck · 5 years ago
- 5247008 cpu: TrafficGen as BaseCPU by Tiago Muck · 5 years ago
- a45037a python: Fix cxx_ini_parse for ScopedEnum by Nikos Nikoleris · 5 years ago
- 007d71a configs: Fix read_config to work with new AddrRange serialization by Nikos Nikoleris · 5 years ago
- 1ba2ae7 configs: Add python3 workarounds in read_config by Nikos Nikoleris · 5 years ago
- d776a13 python: Add binding for the new AddrRange c++ constructor by Nikos Nikoleris · 5 years ago
- c3d5e56 base: Extend unit tests for AddrRange by Nikos Nikoleris · 5 years ago
- c1b7a40 base: Extend AddrRange to support more flexible addressing by Nikos Nikoleris · 5 years ago
- 6186565 base: Fix ctz32 for systems where unsigned int is not 32bit by Nikos Nikoleris · 5 years ago
- 542fd37 base: Add function to count trailing zeros in a 64-bit integer by Nikos Nikoleris · 5 years ago
- ec50225 scons: allow passing arbitrary CCFLAGS and LDFLAGS from the CLI by Ciro Santilli · 5 years ago
- c1e040d arch-arm: implement VMINNM scalar thumb by Ciro Santilli · 5 years ago
- 2157395 base: Provide a getter for Fiber::started boolean variable by Giacomo Travaglini · 5 years ago
- 2833eb9 base: Rename TestFiber into SwitchingFiber by Giacomo Travaglini · 5 years ago
- aece7fc arch-arm: Fix WalkerState,Descriptors default constructor by Giacomo Travaglini · 5 years ago
- 2574dc4 dev-arm: Implement a SMMUv3 model by Stanislaw Czerniawski · 5 years ago
- f2be9f1 mem: Option to toggle DRAM low-power states by Matthew Poremba · 5 years ago
- f5cf6d5 mem-ruby: Enable set size increase by John Alsop · 7 years ago
- 0c0cf48 base: Fix missing headers to CircularQueue by Daniel R. Carvalho · 5 years ago
- cc6eff0 Revert "mem-cache: Remove writebacks packet list" by Daniel Carvalho · 5 years ago
- b68735f cpu: Added the Multiperspective Perceptron Predictor (8KB and 64KB) by Javier Bueno · 5 years ago
- 8767484 x86: fix movsd bug on %xmm register by Brandon Potter · 5 years ago
- ea088f5 config, arm: memoryMode test by Willy Wolff · 5 years ago
- ef29f80 arm: Fix decoding of CRC32 instructions in thumb32 by Chun-Chen TK Hsu · 5 years ago
- 019e320 cpu-o3: Increase LSQ buffer sizes to match max vector length by Gabor Dozsa · 6 years ago
- 3b04ba5 arch-arm: Treat SVE prefetch instructions as no-ops by Giacomo Gabrielli · 6 years ago
- 3cf4a04 arch-arm: Add initial support for SVE gather/scatter loads/stores by Giacomo Gabrielli · 6 years ago
- f26f3e2 cpu: Fix rescheduling of progress check events by Tiago Muck · 5 years ago
- e12da9b arch: Add include guards to auto-gen. decode header by Giacomo Gabrielli · 6 years ago
- fc61172 cpu-o3: Add support for pinned writes by Giacomo Gabrielli · 6 years ago
- 5365c18 arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy. by Gabe Black · 5 years ago
- 74e494e cpu: Store the translating proxy with the same pointer in SE or FS mode. by Gabe Black · 5 years ago
- 39896bd cpu, sim: Return PortProxy &s from all the proxy accessors. by Gabe Black · 5 years ago
- f349b08 kern: Replace an explicitly instantiated port proxy with one from the tc. by Gabe Black · 5 years ago
- 9bffae0 arch, base, sim: Demote (SE|FS)TranslatingPortProxy &s to PortProxy &s. by Gabe Black · 5 years ago
- 1cb22bc mem: Remove the now unused Copy* methods from the FS port proxy. by Gabe Black · 5 years ago
- 096598c arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code. by Gabe Black · 5 years ago
- da7e63d sim-se: const for loader's loadSection param by Brandon Potter · 6 years ago
- dc338b4 cpu: Added correct return type for ROB::countInsts by Andrea Mondelli · 5 years ago
- 5cbd972 mem-cache: Accuracy-based rate control for prefetchers by Javier Bueno · 5 years ago
- 08c79a1 sim-se: add a release parameter to Process.py by Ciro Santilli · 5 years ago
- 151b22c mem-cache: Support for page crossing prefetches by Javier Bueno · 5 years ago
- e2e26d3 mem: Add a readString method to the PortProxy which takes a char *. by Gabe Black · 5 years ago
- 1a631bd mem: Use a const T & in write<> to avoid an unnecessary copy. by Gabe Black · 5 years ago
- 8666440 arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods. by Gabe Black · 5 years ago
- d7c4cad mem, arm: Replace the pointer type in PortProxy with void *. by Gabe Black · 5 years ago
- 6a69fc1 mem, arm: Move some helper methods into the base PortProxy class. by Gabe Black · 5 years ago
- ac65b6e arm, mem: Move the SecurePortProxy subclass into it's own file. by Gabe Black · 5 years ago
- c32b2ac mem: Parameterize coherent xbar sanity checks by Tiago Muck · 5 years ago
- c73b7e5 mem: Snoop filter support for large systems by Tiago Muck · 5 years ago
- cdc03f9 base: Add warn_if_once macro by Tiago Muck · 5 years ago
- f318dfe cpu: Remove assert causing issues with x86 Linux boot by Giacomo Gabrielli · 5 years ago
- 8529cda arch-arm: Fix fallthrough when trapping at EL2 by Giacomo Travaglini · 5 years ago
- 32a2311 arch-arm: Trap virtual accesses to GICv3 SGI registers by Giacomo Travaglini · 5 years ago
- e9c7c81 arch-arm: Expose haveGicv3CPUInterface to the ISA interface by Giacomo Travaglini · 5 years ago
- 92518ec arch-arm: Change mcrMrc15TrapToHyp signature by Giacomo Travaglini · 5 years ago
- b8a4c87 mem: Add invalid context id check on LLSC checks by Tiago Muck · 5 years ago
- c022369 sim-se: remove comment for code that moved by Brandon Potter · 6 years ago
- 5830ee7 dev-arm: Provide a GICv3 ITS Implementation by Giacomo Travaglini · 5 years ago
- dd8a769 sim-se: change syscall function signature by Brandon Potter · 6 years ago
- dd2d445 sim-se: remove /sys from special paths by Tony Gutierrez · 6 years ago
- 874bb1a scons: Move the marshal binary to the build directory by Chun-Chen TK Hsu · 5 years ago
- ae9ba7f misc: Added dot_writer for Ruby's network topology by Tiago Muck · 5 years ago
- b4c4729 mem-cache: Add multi-prefetcher adaptor by Andreas Sandberg · 8 years ago
- 526a2fb sim: Make the Process create function use the object loader mechanism. by Gabe Black · 5 years ago
- 50f8539 x86: Add an object file loader for linux. by Gabe Black · 5 years ago
- 8110bd9 sparc: Add an object file loader for linux and solaris. by Gabe Black · 5 years ago
- 45518cc riscv: Add an object file loader for linux. by Gabe Black · 5 years ago
- 5ab2ffd power: Add an object file loader for linux. by Gabe Black · 5 years ago
- 1e0bb9b mips: Add an object file loader for linux. by Gabe Black · 5 years ago
- b2b6772 arm: Add an object file loader for linux and freebsd. by Gabe Black · 5 years ago
- 9601ba9 alpha: Add an object file loader for linux. by Gabe Black · 5 years ago
- c1b748d base: Add a type for keeping track of object file loaders. by Gabe Black · 5 years ago
- 972c38b arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code. by Gabe Black · 5 years ago
- e265600 configs: Generalize FileSystemConfig for non se.py by Jason Lowe-Power · 5 years ago
- 2795018 arch-arm: implement VMINNM and VMAXNM scalar version by Ciro Santilli · 5 years ago
- 0dee5c3 arch-arm: implement VMINNM and VMAXNM SIMD version by Ciro Santilli · 5 years ago
- 396a07e arch-arm: rename operands to match spec in isa/formats/fp.isa by Ciro Santilli · 5 years ago
- 83d5730 mem-ruby: MOESI_CMP_dir cleanup by Tiago Muck · 5 years ago
- 36e49e2 mem-ruby: Cache latencies for MOESI_CMP_dir by Tiago Muck · 5 years ago
- 496d5ed mem-ruby: Hit latencies defined by the controllers by Tiago Muck · 5 years ago
- 42e55cd mem-ruby: Do not change blocked msg enqueue info by Tiago Muck · 5 years ago
- 575ac7a mem-ruby: Unique ranks for MOESI_CMP_dir in ports by Tiago Muck · 5 years ago
- cbf74a7 mem-ruby: Change MOESI_CMP_Dir L2 addressing by Tiago Muck · 5 years ago
- 7b84e3b mem-ruby: Fix MOESI_CMP_dir debug msg by Tiago Muck · 5 years ago
- b98b648 mem-ruby: Prevent response stalls on MOESI_CMP_directory by Tiago Muck · 5 years ago
- abd33d6 arch-arm: Do not check MustBeOne flag for TLB requests from the prefetcher by Javier Bueno · 5 years ago
- f0a53b8 configs: Fix duplicate branchPred reference in Simulation.py by Javier Bueno · 5 years ago
- 27378ec Revert "cpu: fix how a thread starts up in MinorCPU" by Giacomo Travaglini · 5 years ago
