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  1. c1b748d base: Add a type for keeping track of object file loaders. by Gabe Black · 5 years ago
  2. 972c38b arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code. by Gabe Black · 5 years ago
  3. e265600 configs: Generalize FileSystemConfig for non se.py by Jason Lowe-Power · 5 years ago
  4. 2795018 arch-arm: implement VMINNM and VMAXNM scalar version by Ciro Santilli · 5 years ago
  5. 0dee5c3 arch-arm: implement VMINNM and VMAXNM SIMD version by Ciro Santilli · 5 years ago
  6. 396a07e arch-arm: rename operands to match spec in isa/formats/fp.isa by Ciro Santilli · 5 years ago
  7. 83d5730 mem-ruby: MOESI_CMP_dir cleanup by Tiago Muck · 5 years ago
  8. 36e49e2 mem-ruby: Cache latencies for MOESI_CMP_dir by Tiago Muck · 5 years ago
  9. 496d5ed mem-ruby: Hit latencies defined by the controllers by Tiago Muck · 5 years ago
  10. 42e55cd mem-ruby: Do not change blocked msg enqueue info by Tiago Muck · 5 years ago
  11. 575ac7a mem-ruby: Unique ranks for MOESI_CMP_dir in ports by Tiago Muck · 5 years ago
  12. cbf74a7 mem-ruby: Change MOESI_CMP_Dir L2 addressing by Tiago Muck · 5 years ago
  13. 7b84e3b mem-ruby: Fix MOESI_CMP_dir debug msg by Tiago Muck · 5 years ago
  14. b98b648 mem-ruby: Prevent response stalls on MOESI_CMP_directory by Tiago Muck · 5 years ago
  15. abd33d6 arch-arm: Do not check MustBeOne flag for TLB requests from the prefetcher by Javier Bueno · 5 years ago
  16. f0a53b8 configs: Fix duplicate branchPred reference in Simulation.py by Javier Bueno · 5 years ago
  17. 27378ec Revert "cpu: fix how a thread starts up in MinorCPU" by Giacomo Travaglini · 5 years ago
  18. 9a1eb7a Revert "cpu: stop scheduling suspended threads in MinorCPU" by Giacomo Travaglini · 5 years ago
  19. 9852c5d Revert "cpu: fix branching when thread is suspended in MinorCPU" by Giacomo Travaglini · 5 years ago
  20. c1bd279 mem-cache: Use SatCounter for prefetchers by Daniel · 5 years ago
  21. 50a533f base: Add operators to SatCounter by Daniel · 5 years ago
  22. 5b3f91d base: Add GTest to SatCounter by Daniel · 5 years ago
  23. 578dd47 base: Move SatCounter to base directory by Daniel · 5 years ago
  24. 0def916 cpu: Revamp saturating counters by Daniel · 5 years ago
  25. e541767 config: add an option to list and select indirect branch predictor by Jairo Balart · 5 years ago
  26. 0473f8f cpu: Make the indirect predictor into a SimObject by Jairo Balart · 5 years ago
  27. 1291015 mem-ruby: Replace string parameter in MultiBitSelBloomFilter by Daniel R. Carvalho · 5 years ago
  28. 8ddec45 arch-arm: Add initial support for SVE contiguous loads/stores by Giacomo Gabrielli · 7 years ago
  29. c58cb8c cpu,mem: Add support for partial loads/stores and wide mem. accesses by Giacomo Gabrielli · 7 years ago
  30. d0e4cdc cpu: Add a memory access predicate by Giacomo Gabrielli · 6 years ago
  31. c4bc234 config, sim-se: bugfix for 54c77aa0 by Brandon Potter · 5 years ago
  32. f14a6d7 configs: Fix FileSystemConfig import by Daniel R. Carvalho · 5 years ago
  33. 436d803 tests: Fix import scope of test by Daniel R. Carvalho · 5 years ago
  34. 8c34a1a mem-ruby: Fix MOESI_CMP_directory blocked line handling by Tiago Muck · 5 years ago
  35. bf0a722 mem-cache: Remove writebacks packet list by Daniel R. Carvalho · 5 years ago
  36. e54c7a6 mem-cache: Handle data expansion by Daniel R. Carvalho · 6 years ago
  37. 273aacf mem-cache: Add co-allocation function to compressed tags by Daniel R. Carvalho · 6 years ago
  38. a39af1f mem-cache: Add compression and decompression calls by Daniel R. Carvalho · 6 years ago
  39. 77a4986 mem-cache: Create BDI Compressor by Daniel R. Carvalho · 6 years ago
  40. 0e276f6 mem-cache: Add compression stats by Daniel R. Carvalho · 6 years ago
  41. f21f4a0 mem-cache: Create cache compressor by Daniel R. Carvalho · 6 years ago
  42. 4b6b068 mem-cache: Add block size to findVictim by Daniel R. Carvalho · 6 years ago
  43. 784642b mem-cache: Add compression data to CompressionBlk by Daniel R. Carvalho · 6 years ago
  44. bba32e6 mem-cache: Create CacheComp debug flag by Daniel R. Carvalho · 6 years ago
  45. e22a6c9 mem-cache: Stub compression framework by Daniel R. Carvalho · 6 years ago
  46. 6bf8508 x86: Mark translation as delayed in case of a hw page table walk by Gabor Dozsa · 5 years ago
  47. 7a00e9d sim-se: correct statfs inclusion on !linux host by Andrea Mondelli · 5 years ago
  48. 53e7469 arch-riscv: Implement MHARTID CSR by Alec Roelke · 5 years ago
  49. f75351a sim-se: fix a few bugs/warns from GCC 6 by Joe Gross · 6 years ago
  50. d692552 sim-se: add eventfd system call by Brandon Potter · 6 years ago
  51. 64687ee mem-cache: Mark block as dirty after a SWPrefetchEXResp by Nikos Nikoleris · 5 years ago
  52. b4b487e arch-riscv,isa: Fix for compressed jump (c_j) imm by Avishai Tvila · 5 years ago
  53. b6d60e8 dev: StreamID generation in DMA device by Giacomo Travaglini · 5 years ago
  54. 6af360e tests: There is no architecture called "timing". by Gabe Black · 5 years ago
  55. 49a71ca dev-arm: Store a PhysProxy port in Gicv3Redist by Giacomo Travaglini · 5 years ago
  56. 3762721 dev-arm: Add named variable for GICD_TYPER.IDBits by Giacomo Travaglini · 5 years ago
  57. 5c89117 dev-arm: Read correct version of ICC_BPR register by Giacomo Travaglini · 5 years ago
  58. 5f29ec8 dev-arm: Get a Gicv3Redistributor ptr from phys address by Giacomo Travaglini · 5 years ago
  59. 68f2f1c dev-arm: Add several LPI methods in Gicv3Redistributor by Giacomo Travaglini · 5 years ago
  60. c16b504 dev-arm: Take LPIs into account when interacting with CPUIF regs by Giacomo Travaglini · 5 years ago
  61. 7ad6c80 dev-arm: Fix GICv3 LPIs priority value by Giacomo Travaglini · 5 years ago
  62. a4f3016 dev-arm: Disable LPI Configuration Table caching by Giacomo Travaglini · 5 years ago
  63. afce686 dev-arm: Check EnableLPIs before checking for pending LPIs by Giacomo Travaglini · 5 years ago
  64. bc300d3 dev-arm: GICv3 LPI tables are using physical addresses by Giacomo Travaglini · 5 years ago
  65. 2df87bc dev-arm: Fix GICv3 LPI loop by Giacomo Travaglini · 5 years ago
  66. 9de1f75 dev-arm: Fix Bitwise operation in GICv3 by Giacomo Travaglini · 5 years ago
  67. 308a06c tests: Add missing kernels to system creation by Daniel R. Carvalho · 5 years ago
  68. 12eab3e arch: Stop using TheISA within the ISAs. by Gabe Black · 5 years ago
  69. ecd6be3 x86: Get rid of some unnecessary TheISA-es in x86. by Gabe Black · 5 years ago
  70. 90f90b8 sparc: Move translation constants from isa_traits.hh into tlb.hh. by Gabe Black · 5 years ago
  71. f19884d sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh. by Gabe Black · 5 years ago
  72. 52031e1 arch: Remove the mt.hh switching header. by Gabe Black · 5 years ago
  73. dc9f1a2 cpu: alpha: Delete all occurrances of the simPalCheck function. by Gabe Black · 5 years ago
  74. e9e3fdc alpha: Implement simPalCheck within the ISA description. by Gabe Black · 5 years ago
  75. 40cc7cd cpu: Remove hwrei from the generic interfaces. by Gabe Black · 5 years ago
  76. 0eb763c sim-se: use DPRINTF_SYSCALL for ioctl/wait4 by Alexandru Dutu · 6 years ago
  77. 87ea5ee sim-se: bugfix for 54c77aa055e by Brandon Potter · 5 years ago
  78. eea1fb6 arch: cpu: Track kernel stats using the base ISA agnostic type. by Gabe Black · 5 years ago
  79. f9b7247 alpha: Implement HWREI in the ISA. by Gabe Black · 5 years ago
  80. 2268d07 alpha: Add some control registers to the ISA operands list. by Gabe Black · 5 years ago
  81. 081da0f sim-se: add socket ioctls by Brandon Potter · 6 years ago
  82. ca3dd50 systemc: Add a distinct async_request_update mechanism. by Gabe Black · 5 years ago
  83. 88fc141 cpu: Get rid of the (read|set)RegOtherThread methods. by Gabe Black · 5 years ago
  84. a632ee7 mips: Implement readRegOtherThread and setRegOtherThread directly. by Gabe Black · 5 years ago
  85. a4d7473 cpu: Include debug flags regardless of whether the ISA is null. by Gabe Black · 5 years ago
  86. 5ad8040 sim-se: create Proc out files in out dir by Steve Reinhardt · 6 years ago
  87. ae89162 arch-arm: Faults DebugFlag now printing inst opcode if available by Giacomo Travaglini · 5 years ago
  88. 529284b arch-arm: Report real instruction encoding when Undefined by Giacomo Travaglini · 5 years ago
  89. 9305bb6 arch, sim: Simplify the AuxVector type. by Gabe Black · 5 years ago
  90. fce9c7a mem: Remove the ISA specialized versions of port proxy's read/write. by Gabe Black · 5 years ago
  91. cdcc55a mem: Minimize the use of MemObject. by Gabe Black · 5 years ago
  92. 3cfff85 python: Get rid of the VectorPort constructor. by Gabe Black · 5 years ago
  93. 6b87ee1 python: Replace the Master/Slave Ports with Request/Response ports. by Gabe Black · 5 years ago
  94. f5ea783 arch-arm: updateMiscReg not setting isHyp in aarch64 by Giacomo Travaglini · 5 years ago
  95. a5f06ab arm: Factor some repetition out of the ProcessInfo constructor. by Gabe Black · 5 years ago
  96. 488ded0 arm: Fix some style issues in stacktrace.cc. by Gabe Black · 5 years ago
  97. 50311fe x86: Refactor the ProcessInfo constructor. by Gabe Black · 5 years ago
  98. ae3a00c configs: faux-filesystem fix w/ ruby in se mode by David Hashe · 6 years ago
  99. 26e8889 x86: Fix some style issues in stacktrace.cc. by Gabe Black · 5 years ago
  100. 54c77aa sim-se: add a faux-filesystem by David Hashe · 6 years ago