- e8d0b75 arch-arm: Remove un-needed hyp flag in TLBI operations by Giacomo Travaglini · 5 years ago
- 670d080 arch-arm: Correct target EL field in TLBI operations by Giacomo Travaglini · 5 years ago
- 40018b1 dev-arm: Move GICv3 (Re)Ditributor address in Realview.py by Giacomo Travaglini · 5 years ago
- ed48d74 dev-arm: Limit number of max PE in GICv3 to 128 by Giacomo Travaglini · 5 years ago
- 84c4fd0 dev-arm: Add GICv4 extension switch in GICv3 by Giacomo Travaglini · 5 years ago
- c366e19 dev-arm: Check for maximum number of supported PE in GICv3 by Giacomo Travaglini · 5 years ago
- 8f010ce config: Add flag options to set the hardware prefetchers to use by Javier Bueno · 5 years ago
- 57667ba cpu,mem: missing override specifier by Andrea Mondelli · 5 years ago
- e52e6cc systemc: Use the new TLM socket types in the TLM bridge SimObjects. by Gabe Black · 5 years ago
- e76777d systemc: Add Port types for initiator and target sockets. by Gabe Black · 5 years ago
- 77201c8 dev: Use the new Port role mechanism to make an EtherInt Port type. by Gabe Black · 5 years ago
- 3c3f360 python: Generalize the Port.splice function. by Gabe Black · 5 years ago
- 9c23850 python: Generalize the dot_writer to handle non Master/Slave roles. by Gabe Black · 5 years ago
- e69cce7 python: Make Port roles a more generic concept. by Gabe Black · 5 years ago
- 325acb7 python: fix tracing after Python 3 refactor by Ciro Santilli · 5 years ago
- c5b3db6 sim-se: Enhance clone for X86KvmCPU by Alexandru Dutu · 5 years ago
- 382263c mem-cache: Fix fix of replacement count by Daniel · 5 years ago
- 620d1c6 cpu: Eliminate the ProxyThreadContext class. by Gabe Black · 5 years ago
- 3a106e1 configs: Use param to get number of processors by Po-Hao Su · 5 years ago
- 7976b56 mem-cache: Fix increasing replacement count by Daniel R. Carvalho · 5 years ago
- 639b400 mem-cache: Remove blk_addr from Queue::trySatisfyFunctional by Daniel R. Carvalho · 5 years ago
- 2d84dc4 mem-cache: Add match functions to QueueEntry by Daniel R. Carvalho · 5 years ago
- d4cee4d mem: Add packet matching functions by Daniel R. Carvalho · 5 years ago
- 9f32d74 mem-cache: Move Target to QueueEntry by Daniel R. Carvalho · 5 years ago
- f699e91 mem-cache: Assert Entry inherits from QueueEntry in Queue by Daniel R. Carvalho · 5 years ago
- 5fabb99 mem: Make DRAMCtrl::decodeAddr const by Daniel R. Carvalho · 5 years ago
- 22abf79 mem: Allow packet to provide its own addr range by Daniel R. Carvalho · 5 years ago
- 3d4e412 mem: missing override specifier by Andrea Mondelli · 5 years ago
- f9e833b mem: Teach SimpleMem to return a MemBackdoor when appropriate. by Gabe Black · 5 years ago
- 73e14fb mem: Maintain a back door into the AbstractMem's backing store. by Gabe Black · 5 years ago
- b2b9285 tests: Add tests for learning_gem5 configs by Rutuja Oza · 5 years ago
- 10f946c tests: Add protocol as an option to SconsFixture by Jason Lowe-Power · 5 years ago
- 6b81e08 tests: add riscv to cpu tests by Hoa Nguyen · 5 years ago
- 04bc162 mem-cache: Fix RRPV for RRIP by Anis Peysieux · 5 years ago
- 740756e arch-arm: Enable PMSELR_EL0 read in PMU by Giacomo Travaglini · 5 years ago
- 680a689 mem: Plumb backdoor requests through the xbar classes. by Gabe Black · 5 years ago
- 729d994 systemc: Teach the TLM bridges how to use gem5's new backdoor mechanism. by Gabe Black · 5 years ago
- 64f415f mem: Add sendAtomicBackdoor/recvAtomicBackdoor port methods. by Gabe Black · 5 years ago
- a8d5dd1 mem-cache: Fix MSHR handling of cache clean requests by Nikos Nikoleris · 5 years ago
- daa9dcb cpu: O3 switchFreeList checking VecElems instead of FloatRegs by Giacomo Travaglini · 5 years ago
- 7f9c984 learning_gem5,configs: Update ruby_test by Jason Lowe-Power · 5 years ago
- c1e646d learning_gem5: Fix vector port panic in SimpleCache by Jason Lowe-Power · 5 years ago
- 36bce39 configs: Fix import path error in learning_gem5 part3 by Jason Lowe-Power · 5 years ago
- 6bcd13f configs: Add full path for learning_gem5 binaries by Jason Lowe-Power · 5 years ago
- ca687ea configs: Removed redudant exec-style import by Ryan Gambord · 5 years ago
- 2cf18a8 mem: Add a MemBackdoor type to track memory backdoors. by Gabe Black · 5 years ago
- d0f8765 cpu: Correctly account for executed instructions in simple cpus by Nikos Nikoleris · 5 years ago
- 271f2ae mem-cache: ambiguous use of abs function by Ryan Gambord · 5 years ago
- 529d0cd mem: Reverse order of write/read mem queue check by Jason Lowe-Power · 5 years ago
- 07eca72 tests: Add Jenkins presubmit and continuous test scripts by Jason Lowe-Power · 6 years ago
- c2c1a97 mem-cache: AMPM Prefetcher fails when restoring from a checkpoint by Javier Bueno · 5 years ago
- e13d6dc misc: Removed inconsistency in O3* debug msgs by Andrea Mondelli · 5 years ago
- 5084b90 arch-mips: added missing override specifier (o3) by Andrea Mondelli · 5 years ago
- 5caa451 mem-cache: Fix PIF prefetcher compilation error with NULL ISA by Javier Bueno · 5 years ago
- f662b8a mem-cache: ISB prefetcher was triggering an assertion by Javier Bueno · 5 years ago
- 06b305b mem-cache: Fix panic in Indirect Memory prefetcher by Javier Bueno · 5 years ago
- e7a1636 dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt by Giacomo Travaglini · 5 years ago
- 4628d87 mem-cache: Proactive Instruction Fetch Implementation by Ivan Pizarro · 5 years ago
- 283e092 dev-arm: Correct cast of template parameter by Andrea Mondelli · 5 years ago
- 2a98a99 systemc: Templatize the gem5/TLM bridge SimObjects. by Gabe Black · 5 years ago
- b2efb72 systemc: Delete extra code from src/systemc/tlm_bridge. by Gabe Black · 5 years ago
- e65a89e systemc: Create unified gem5/TLM bridge SimObjects. by Gabe Black · 5 years ago
- 9a042da tlm: Initial import of tlm/gem5 bridge code. by Gabe Black · 5 years ago
- 87c4a97 systemc: Provide a utility Port TLM socket wrapper class. by Gabe Black · 5 years ago
- 1a27580 cpu: Added a probe to notify the address of retired instructions by Javier Bueno · 5 years ago
- cbaae54 mem-cache: Remove extra cache header from AMAP by Daniel R. Carvalho · 5 years ago
- a93fe3f arch-arm: Fix use of bitwise operators on booleans by Javier Setoain · 5 years ago
- 93ad0d4 arch-arm: Fix index generation for VecElem operands by Giacomo Travaglini · 5 years ago
- 631bfb6 dev-arm: Rename GIC maintenance interrupt from ppint to maint_int by Giacomo Travaglini · 5 years ago
- e8a6811 dev-arm: Fix GICv3 overflow for INTID > 256 by Giacomo Travaglini · 5 years ago
- e36839e dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0) by Giacomo Travaglini · 5 years ago
- 9059aaf config: Use the corresponding HPI Caches when using the HPI cpu by Javier Bueno · 5 years ago
- 78f1f4d cpu: Fixed the indirect branch predictor GHR handling by Pau Cabre · 5 years ago
- 4fc7dfb mem: Deleting this init() method was accidentally dropped during rebase. by Gabe Black · 5 years ago
- 599d2c9 mem: Clean up the xbars a little. by Gabe Black · 5 years ago
- fcc4c4f base: Make AddrRangeMap able to return non-const iterators. by Gabe Black · 5 years ago
- c67d89f configs: fix class reference in CacheConfigs by Javier Bueno · 5 years ago
- 61f0e7e dev-arm: Set/Unset dma coherent mode from python by Giacomo Travaglini · 5 years ago
- ca4c0a1 base,python: Fix to allow multiple --debug-ignore values. by Isaac Sánchez Barrera · 5 years ago
- 149c1fc configs: Remove default kernel value from system creation by Daniel R. Carvalho · 6 years ago
- 8e1a141 arch-arm: Add missing fall-through defaults by Javier Setoain · 5 years ago
- f838a33 arch-power: Rename program counter registers by Sandipan Das · 5 years ago
- 4847330 arch-power: Simplify doubleword operand types by Sandipan Das · 5 years ago
- 4effe34 misc: missing override specifier by Andrea Mondelli · 5 years ago
- 759795a sim-se: Fixed initialization array size by Tiago Muck · 6 years ago
- d94e5b5 base: Fix CircularQueue's operator-= when negative subtraction by Giacomo Travaglini · 5 years ago
- bbcbde7 base: Fix CircularQueue when diffing iterators by Giacomo Travaglini · 5 years ago
- 487ea06 dev-arm: ambiguous use of getPort() by Andrea Mondelli · 5 years ago
- 699ba19 tests: Add ignore for stdin not terminal by Jason Lowe-Power · 5 years ago
- 19eb23f tests: Use full path for DownloadedProgram by Jason Lowe-Power · 5 years ago
- ee0e0ff tests: Fix race condition in download fixture by Jason Lowe-Power · 5 years ago
- 76d9c83 ext,tests: Add back failing exceptions by Jason Lowe-Power · 5 years ago
- 4c28149 tests,ext: Add skip_cleanup implementation for TempdirFixture by Jason Lowe-Power · 5 years ago
- fced86b ext,tests: Make return code based on test results by Jason Lowe-Power · 5 years ago
- f871fd3 ext,test: Provide default terminal size by Jason Lowe-Power · 5 years ago
- 541d899 cpu-kvm: Added informative error message by Ryan Gambord · 5 years ago
- 81e34b3 mem-cache: Added the STeMS prefetcher by Javier Bueno · 5 years ago
- dee6fe7 systemc: Hook up gem5_getPort to the gem5 getPort mechanism. by Gabe Black · 5 years ago
- d3d2483 arch, cpu, dev, gpu, mem, sim, python: start using getPort. by Gabe Black · 5 years ago
- 378d9cc python: Switch to the new getPort mechanism to connect ports. by Gabe Black · 5 years ago
