commit 47fd797f1ecd303da3263b180904a7a0b0e18581
author Giacomo Travaglini <giacomo.travaglini@arm.com> Wed Jan 09 20:10:29 2019 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Jan 25 12:51:29 2019 +0000
tree c1bdd2b5184ea89bb373922edbeb8e51602c4df0
parent b045de7e6969d5a40d4a3f9b178844cc911ac4c2

arch-arm: Inital vector rename mode depending on A32/A64

Change-Id: I6b99833641b0ab6534471d5ff3ca5d3791285481
Reviewed-on: https://gem5-review.googlesource.com/c/15599
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/arm/ArmISA.py

diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 52c42cb..b4e8536 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -87,10 +87,6 @@
     id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
         "AArch64 Auxiliary Feature Register 1")
 
-    # Initial vector register rename mode
-    vecRegRenameMode = Param.VecRegRenameMode('Full',
-        "Initial rename mode for vecregs")
-
     # 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
     id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006,
         "AArch64 Debug Feature Register 0")

src/arch/arm/isa.cc

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 6cbf8db..97de97e 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -62,7 +62,7 @@
     : SimObject(p),
       system(NULL),
       _decoderFlavour(p->decoderFlavour),
-      _vecRegRenameMode(p->vecRegRenameMode),
+      _vecRegRenameMode(Enums::Full),
       pmu(p->pmu),
       impdefAsNop(p->impdef_nop)
 {
@@ -103,6 +103,10 @@
         haveGICv3CPUInterface = true;
     }
 
+    // Initial rename mode depends on highestEL
+    const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
+        highestELIs64 ? Enums::Full : Enums::Elem;
+
     initializeMiscRegMetadata();
     preUnflattenMiscReg();