stats: update stats for cache occupancy and clock domain changes

commit: f3585c841e964c98911784a187fc4f081a02a0a6 [log] [tgz]
author: Ali Saidi <Ali.Saidi@ARM.com> Fri Jan 24 15:29:33 2014 -0600
committer: Ali Saidi <Ali.Saidi@ARM.com> Fri Jan 24 15:29:33 2014 -0600
tree: 2a5a3edeaeb0ffe37ca3a04b884f8f66c7538bbf
parent: cfc4a999828a5b51f4c514e3a7c47b4eebc450b9 [diff]
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index 38f343b..01fef3e 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini

@@ -15,16 +15,16 @@
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+pal=/dist/binaries/ts_osfpal
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -175,6 +175,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.dcache.tags
@@ -191,6 +192,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.dtb]
@@ -520,6 +522,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.icache.tags
@@ -536,6 +539,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.interrupts]
@@ -545,6 +549,7 @@
 [system.cpu0.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu0.itb]
 type=AlphaTLB
@@ -675,6 +680,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.dcache.tags
@@ -691,6 +697,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.dtb]
@@ -1020,6 +1027,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.icache.tags
@@ -1036,6 +1044,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.interrupts]
@@ -1045,6 +1054,7 @@
 [system.cpu1.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu1.itb]
 type=AlphaTLB
@@ -1081,7 +1091,7 @@
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -1104,7 +1114,7 @@
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -1138,6 +1148,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -1154,6 +1165,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.l2c]
@@ -1171,6 +1183,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.l2c.tags
@@ -1187,6 +1200,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.membus]
@@ -1267,7 +1281,7 @@
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
index 0bcb6e8..20fe2d6 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr

@@ -2,4 +2,3 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
index ef1ae14..d125f29 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout

@@ -1,13 +1,13 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 16 2013 01:34:33
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 19:30:57
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 125036000
-Exiting @ tick 1902738973500 because m5_exit instruction encountered
+info: Launching CPU 1 @ 126320000
+Exiting @ tick 1903338216000 because m5_exit instruction encountered

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index 3ddbcdb..4177c2e 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                1903338216000                       # Number of ticks simulated
 final_tick                               1903338216000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 100362                       # Simulator instruction rate (inst/s)
-host_op_rate                                   100362                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3404824916                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 359096                       # Number of bytes of host memory used
-host_seconds                                   559.01                       # Real time elapsed on the host
+host_inst_rate                                 150214                       # Simulator instruction rate (inst/s)
+host_op_rate                                   150214                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5096064990                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 314972                       # Number of bytes of host memory used
+host_seconds                                   373.49                       # Real time elapsed on the host
 sim_insts                                    56103611                       # Number of instructions simulated
 sim_ops                                      56103611                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.inst           740992                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data         24346432                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2650176                       # Number of bytes read from this memory
@@ -421,6 +423,7 @@
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 system.membus.respLayer2.occupancy          376321991                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                   345713                       # number of replacements
 system.l2c.tags.tagsinuse                65292.619294                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    2607692                       # Total number of references to valid blocks.
@@ -438,6 +441,15 @@
 system.l2c.tags.occ_percent::cpu1.inst       0.020833                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.008543                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.996286                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        65211                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          179                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1         2154                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         5524                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6881                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        50473                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.995041                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 27399611                       # Number of tag accesses
+system.l2c.tags.data_accesses                27399611                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.inst             754547                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.data             572386                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.inst             313557                       # number of ReadReq hits
@@ -732,6 +744,11 @@
 system.iocache.tags.occ_blocks::tsunami.ide     0.213166                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::tsunami.ide     0.013323                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.013323                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               375543                       # Number of tag accesses
+system.iocache.tags.data_accesses              375543                       # Number of data accesses
 system.iocache.ReadReq_misses::tsunami.ide          175                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -1129,8 +1146,8 @@
 system.cpu0.int_regfile_writes               32453910                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                   110308                       # number of floating regfile reads
 system.cpu0.fp_regfile_writes                  111090                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1526243                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                747832                       # number of misc regfile writes
+system.cpu0.misc_regfile_reads                1625466                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                747841                       # number of misc regfile writes
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1275,6 +1292,13 @@
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.693534                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995495                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.995495                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           86                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          314                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses          7662265                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses         7662265                       # Number of data accesses
 system.cpu0.icache.ReadReq_hits::cpu0.inst      6090993                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total        6090993                       # number of ReadReq hits
 system.cpu0.icache.demand_hits::cpu0.inst      6090993                       # number of demand (read+write) hits
@@ -1359,6 +1383,13 @@
 system.cpu0.dcache.tags.occ_blocks::cpu0.data   471.490981                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.920881                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.920881                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          220                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          243                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         50559091                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        50559091                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data      5751167                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total        5751167                       # number of ReadReq hits
 system.cpu0.dcache.WriteReq_hits::cpu0.data      3244504                       # number of WriteReq hits
@@ -1814,8 +1845,8 @@
 system.cpu1.int_regfile_writes               10191479                       # number of integer regfile writes
 system.cpu1.fp_regfile_reads                    58039                       # number of floating regfile reads
 system.cpu1.fp_regfile_writes                   58174                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 621722                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                265027                       # number of misc regfile writes
+system.cpu1.misc_regfile_reads                1024653                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                265032                       # number of misc regfile writes
 system.cpu1.icache.tags.replacements           316719                       # number of replacements
 system.cpu1.icache.tags.tagsinuse          504.225697                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs            1849767                       # Total number of references to valid blocks.
@@ -1825,6 +1856,12 @@
 system.cpu1.icache.tags.occ_blocks::cpu1.inst   504.225697                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.984816                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.984816                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          420                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses          2498600                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         2498600                       # Number of data accesses
 system.cpu1.icache.ReadReq_hits::cpu1.inst      1849767                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total        1849767                       # number of ReadReq hits
 system.cpu1.icache.demand_hits::cpu1.inst      1849767                       # number of demand (read+write) hits
@@ -1909,6 +1946,12 @@
 system.cpu1.dcache.tags.occ_blocks::cpu1.data   495.920224                       # Average occupied blocks per requestor
 system.cpu1.dcache.tags.occ_percent::cpu1.data     0.968594                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_percent::total     0.968594                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          341                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1           35                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          306                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.666016                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         17217310                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        17217310                       # Number of data accesses
 system.cpu1.dcache.ReadReq_hits::cpu1.data      2089496                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total        2089496                       # number of ReadReq hits
 system.cpu1.dcache.WriteReq_hits::cpu1.data      1222054                       # number of WriteReq hits

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index 275c9f1..80c9d15 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini

@@ -15,16 +15,16 @@
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+pal=/dist/binaries/ts_osfpal
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -175,6 +175,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.dcache.tags
@@ -191,6 +192,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.dtb]
@@ -520,6 +522,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.icache.tags
@@ -536,6 +539,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.interrupts]
@@ -545,6 +549,7 @@
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -566,6 +571,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.cpu.l2cache.tags
@@ -582,6 +588,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.cpu.toL2Bus]
@@ -625,7 +632,7 @@
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -648,7 +655,7 @@
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -682,6 +689,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -698,6 +706,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.membus]
@@ -778,7 +787,7 @@
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
index 0bcb6e8..20fe2d6 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr

@@ -2,4 +2,3 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index 7f8767e..6b0c7ba 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout

@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 16 2013 01:34:33
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 19:25:00
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1860200687500 because m5_exit instruction encountered
+Exiting @ tick 1860197780500 because m5_exit instruction encountered

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index c08f755..674a7df 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                1860197780500                       # Number of ticks simulated
 final_tick                               1860197780500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 103834                       # Simulator instruction rate (inst/s)
-host_op_rate                                   103834                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3645751305                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 355004                       # Number of bytes of host memory used
-host_seconds                                   510.24                       # Real time elapsed on the host
+host_inst_rate                                 153122                       # Simulator instruction rate (inst/s)
+host_op_rate                                   153122                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5376333902                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 310876                       # Number of bytes of host memory used
+host_seconds                                   346.00                       # Real time elapsed on the host
 sim_insts                                    52979882                       # Number of instructions simulated
 sim_ops                                      52979882                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            963968                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          24878976                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
@@ -417,6 +419,11 @@
 system.iocache.tags.occ_blocks::tsunami.ide     1.261116                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::tsunami.ide     0.078820                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.078820                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
+system.iocache.tags.data_accesses              375525                       # Number of data accesses
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -521,6 +528,7 @@
 system.cpu.branchPred.BTBHitPct             61.928509                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                  906521                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect              39211                       # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -814,7 +822,7 @@
 system.cpu.int_regfile_writes                40316653                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                    166009                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                   167434                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 1986207                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                 2028435                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                 938984                       # number of misc regfile writes
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
@@ -952,6 +960,13 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   509.660060                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.995430                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.995430                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          112                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          324                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses           9566377                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses          9566377                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst      7489392                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total         7489392                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst       7489392                       # number of demand (read+write) hits
@@ -1040,6 +1055,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.081017                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.094308                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.996979                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65167                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          492                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3492                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3315                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2416                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55452                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994370                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         26727370                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        26727370                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst       995146                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       827013                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1822159                       # number of ReadReq hits
@@ -1232,6 +1256,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.994567                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999989                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999989                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          415                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           94                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          63738376                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63738376                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data      7205308                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total         7205308                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      4203634                       # number of WriteReq hits

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
index 8069712..933f62f 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini

@@ -15,16 +15,16 @@
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+pal=/dist/binaries/ts_osfpal
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -108,6 +108,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.dcache.tags
@@ -124,6 +125,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.dtb]
@@ -146,6 +148,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.icache.tags
@@ -162,6 +165,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.interrupts]
@@ -171,6 +175,7 @@
 [system.cpu0.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu0.itb]
 type=AlphaTLB
@@ -218,6 +223,7 @@
 [system.cpu1.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu1.itb]
 type=AlphaTLB
@@ -646,6 +652,7 @@
 [system.cpu2.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu2.itb]
 type=AlphaTLB
@@ -682,7 +689,7 @@
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -705,7 +712,7 @@
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -739,6 +746,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -755,6 +763,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.l2c]
@@ -772,6 +781,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.l2c.tags
@@ -788,6 +798,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.membus]
@@ -868,7 +879,7 @@
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
index 3c54e08..b501a6b 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr

@@ -1,6 +1,5 @@
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
index 6d6f549..ecd39bc 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout

@@ -1,6254 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 16 2013 01:34:47
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 19:37:21
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: Entering event queue @ 0.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1000000000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2000000000.  Starting simulation...
-info: Entering event queue @ 2000005000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2000007000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3000007000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3000031000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4000031000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 5000031000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5000032000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 6000032000.  Starting simulation...
-info: Entering event queue @ 7566911500.  Starting simulation...
-info: Entering event queue @ 7566971250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 7566976000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 8566976000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 9566976000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 9566983500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 10566983500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 10567083000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 11567083000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 12567083000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 12567090500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 13567090500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 13567098000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 14567098000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 15567098000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 15567105500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 16567105500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 16567113000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 17567113000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 18567113000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 18567120500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 19567120500.  Starting simulation...
-info: Entering event queue @ 19567148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 19567153500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 20567153500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 21567153500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 21567161000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 22567161000.  Starting simulation...
-info: Entering event queue @ 22567173500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 22567179000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 23567179000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 24567179000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 24567186500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 25567186500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 25567194000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 26567194000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 27567194000.  Starting simulation...
-info: Entering event queue @ 27567201500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 27567202500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 28567202500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 28567210000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 29567210000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 30567210000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 30567217500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 31567217500.  Starting simulation...
-info: Entering event queue @ 31567226000.  Starting simulation...
-info: Entering event queue @ 31567232000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 31567236500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 32567236500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 33567236500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 33567244000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 34567244000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 34567251500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 35567251500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 36567251500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 36567259000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 37567259000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 37567266500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 38567266500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 39567266500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 39567274000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 40567274000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 40567277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 41567277000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 42567277000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 42567284500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 43567284500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 43945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 44945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 45945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 46945335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 47851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 48851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 49851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 50851585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 51757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 52757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 53757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 54757835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 55664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 56664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 57664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 58664085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 59570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 60570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 61570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 62570335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 63476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 64476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 65476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 66476585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 67382835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 68382835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 69382835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 70382835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 71289085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 72289085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 73289085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 74289085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 75195335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 76195335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 77195335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 78195335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 79101585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 80101585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 81101585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 82101585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 83007835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 84007835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 85007835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 86007835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 86914085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 87914085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 88914085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 89914085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 90820335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 91820335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 92820335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 93820335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 94726585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 95726585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 96726585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 97726585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 98632835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 99632835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 100632835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 101632835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 102539085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 103539085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 104539085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 105539085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 106445335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 107445335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 108445335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 109445335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 110351585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 111351585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 112351585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 113351585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 114257835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 115257835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 116257835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 117257835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 118164085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 119164085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 120164085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 121164085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 122070335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 123070335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 124070335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 125070335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 125976585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 126976585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 127976585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 128976585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 129882835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 130882835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 131882835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 132882835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 133789085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 134789085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 135789085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 136789085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 137695335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 138695335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 139695335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 140695335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 141601585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 142601585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 143601585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 144601585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 145507835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 146507835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 147507835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 147507843000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 148507843000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 149414085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 150414085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 151414085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 152414085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 153320335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 154320335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 155320335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 156320335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 157226585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 158226585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 159226585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 160226585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 161132835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 162132835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 163132835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 164132835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 165039085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 166039085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 167039085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 168039085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 168945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 169945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 170945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 171945335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 172851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 173851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 174851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 175851585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 176757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 177757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 178757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 179757835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 180664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 181664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 182664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 183664085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 184570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 185570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 186570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 187570335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 188476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 189476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 190476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 191476585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 192382835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 193382835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 194382835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 195382835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 196289085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 197289085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 198289085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 199289085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 200195335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 201195335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 202195335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 203195335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 204101585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 205101585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 206101585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 207101585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 208007835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 209007835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 210007835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 211007835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 211914085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 212914085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 213914085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 214914085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 215820335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 216820335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 217820335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 218820335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 219726585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 220726585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 221726585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 222726585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 223632835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 224632835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 225632835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 226632835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 227539085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 228539085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 229539085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 230539085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 231445335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 232445335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 233445335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 234445335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 235351585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 236351585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 237351585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 238351585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 239257835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 240257835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 241257835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 242257835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 243164085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 244164085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 245164085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 246164085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 247070335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 248070335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 249070335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 250070335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 250976585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 251976585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 252976585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 252976593000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 253976593000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 254882835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 255882835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 256882835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 257882835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 258789085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 259789085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 260789085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 261789085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 262695335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 263695335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 264695335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 265695335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 266601585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 267601585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 268601585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 269601585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 270507835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 271507835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 272507835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 273507835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 274414085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 275414085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 276414085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 277414085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 278320335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 279320335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 280320335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 281320335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 282226585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 283226585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 284226585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 285226585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 286132835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 287132835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 288132835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 289132835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 290039085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 291039085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 292039085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 293039085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 293945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 294945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 295945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 296945335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 297851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 298851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 299851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 300851585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 301757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 302757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 303757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 304757835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 305664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 306664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 307664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 308664085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 309570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 310570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 311570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 312570335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 313476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 314476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 315476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 316476585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 317382835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 318382835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 319382835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 320382835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 321289085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 322289085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 323289085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 324289085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 325195335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 326195335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 327195335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 328195335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 329101585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 330101585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 331101585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 332101585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 333007835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 334007835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 335007835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 336007835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 336914085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 337914085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 338914085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 339914085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 340820335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 341820335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 342820335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 343820335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 344726585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 345726585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 346726585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 347726585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 348632835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 349632835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 350632835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 351632835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 352539085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 353539085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 354539085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 355539085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 356445335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 357445335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 358445335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 359445335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 360351585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 361351585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 362351585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 363351585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 364257835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 365257835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 366257835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 367257835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 368164085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 369164085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 370164085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 371164085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 372070335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 373070335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 374070335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 375070335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 375976585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 376976585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 377976585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 378976585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 379882835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 380882835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 381882835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 382882835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 383789085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 384789085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 385789085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 386789085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 387695335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 388695335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 389695335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 390695335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 391601585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 392601585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 393601585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 394601585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 395507835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 396507835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 397507835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 398507835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 399414085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 400414085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 401414085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 402414085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 403320335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 404320335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 405320335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 406320335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 407226585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 408226585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 409226585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 410226585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 411132835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 412132835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 413132835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 414132835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 415039085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 416039085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 417039085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 418039085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 418945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 419945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 420945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 421945335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 422851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 423851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 424851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 425851585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 426757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 427757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 428757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 429757835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 430664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 431664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 432664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 433664085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 434570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 435570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 436570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 437570335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 438476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 439476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 440476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 441476585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 442382835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 443382835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 444382835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 445382835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 446289085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 447289085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 448289085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 449289085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 450195335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 451195335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 452195335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 453195335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 454101585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 455101585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 456101585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 457101585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 458007835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 459007835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 460007835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 461007835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 461914085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 462914085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 463914085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 464914085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 465820335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 466820335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 467820335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 468820335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 469726585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 470726585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 471726585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 472726585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 473632835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 474632835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 475632835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 476632835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 477539085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 478539085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 479539085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 480539085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 481445335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 482445335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 483445335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 484445335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 485351585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 486351585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 487351585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 488351585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 489257835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 490257835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 491257835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 492257835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 493164085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 494164085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 495164085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 496164085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 497070335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 498070335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 499070335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 500070335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 500976585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 501976585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 502976585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 503976585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 504882835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 505882835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 506882835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 507882835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 508789085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 509789085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 510789085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 511789085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 512695335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 513695335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 514695335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 515695335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 516601585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 517601585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 518601585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 519601585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 520507835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 521507835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 522507835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 523507835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 524414085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 525414085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 526414085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 527414085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 528320335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 529320335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 530320335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 531320335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 532226585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 533226585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 534226585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 535226585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 536132835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 537132835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 538132835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 539132835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 540039085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 541039085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 542039085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 543039085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 543945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 544945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 545945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 546945335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 547851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 548851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 549851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 550851585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 551757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 552757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 553757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 554757835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 555664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 556664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 557664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 558664085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 559570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 560570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 561570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 562570335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 563476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 564476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 565476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 566476585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 567382835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 568382835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 569382835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 569382939000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 570382939000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 571289085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 572289085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 573289085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 574289085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 575195335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 576195335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 577195335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 578195335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 579101585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 580101585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 581101585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 582101585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 583007835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 584007835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 585007835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 586007835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 586914085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 587914085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 588914085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 589914085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 590820335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 591820335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 592820335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 593820335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 594726585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 595726585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 596726585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 597726585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 598632835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 599632835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 600632835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 601632835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 602539085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 603539085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 604539085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 605539085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 606445335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 607445335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 608445335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 609445335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 610351585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 611351585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 612351585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 613351585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 614257835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 615257835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 616257835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 617257835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 618164085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 619164085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 620164085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 621164085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 622070335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 623070335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 624070335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 624070336500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 625070336500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 625195317000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 626195317000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 627195317000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 628195317000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 628906271500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 629906271500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 630906271500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 631906271500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 632812523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 633812523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 634812523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 635812523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 636718773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 637718773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 638718773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 639718773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 640625023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 641625023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 642625023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 643625023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 644531273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 645531273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 646531273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 647531273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 648437523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 649437523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 650437523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 651437523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 652343773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 653343773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 654343773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 655343773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 656250023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 657250023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 658250023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 659250023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 660156273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 661156273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 662156273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 663156273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 664062523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 665062523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 666062523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 667062523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 667968773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 668968773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 669968773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 670968773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 671875023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 672875023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 673875023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 674875023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 675781273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 676781273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 677781273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 678781273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 679687523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 680687523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 681687523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 682687523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 683593773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 684593773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 685593773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 686593773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 687500023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 688500023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 689500023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 690500023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 691406273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 692406273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 693406273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 694406273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 695312523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 696312523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 697312523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 698312523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 699218773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 700218773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 701218773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 702218773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 703125023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 704125023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 705125023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 706125023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 707031273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 708031273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 709031273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 710031273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 710937523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 711937523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 712937523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 713937523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 714843773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 715843773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 716843773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 717843773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 718750023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 719750023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 720750023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 721750023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 722656273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 723656273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 724656273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 725656273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 726562523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 727562523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 728562523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 729562523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 730468773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 731468773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 732468773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 732468780500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 733468780500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 734375023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 735375023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 736375023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 736375030500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 737375030500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 738281273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 739281273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 740281273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 740281280500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 741281280500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 742187523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 743187523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 744187523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 745187523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 746093773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 747093773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 748093773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 749093773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 750000023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 751000023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 752000023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 753000023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 753906273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 754906273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 755906273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 755906280500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 756906280500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 757812523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 758812523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 759812523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 760812523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 761718773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 762718773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 763718773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 764718773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 765625023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 766625023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 767625023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 768625023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 769531273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 770531273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 771531273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 772531273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 773437523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 774437523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 775437523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 776437523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 777343773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 778343773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 779343773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 780343773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 781250023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 782250023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 783250023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 784250023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 785156273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 786156273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 787156273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 788156273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 789062523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 790062523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 791062523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 792062523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 792968773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 793968773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 794968773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 795968773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 796875023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 797875023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 798875023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 799875023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 800781273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 801781273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 802781273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 803781273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 804687523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 805687523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 806687523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 807687523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 808593773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 809593773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 810593773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 811593773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 812500023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 813500023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 814500023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 815500023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 816406273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 817406273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 818406273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 819406273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 820312523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 821312523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 822312523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 823312523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 824218773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 825218773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 826218773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 827218773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 828125023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 829125023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 830125023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 831125023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 832031273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 833031273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 834031273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 835031273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 835937523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 836937523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 837937523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 838937523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 839843773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 840843773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 841843773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 841843780500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 842843780500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 843750023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 844750023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 845750023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 846750023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 847656273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 848656273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 849656273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 850656273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 851562523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 852562523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 853562523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 854562523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 855468773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 856468773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 857468773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 858468773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 859375023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 860375023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 861375023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 862375023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 863281273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 864281273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 865281273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 866281273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 867187523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 868187523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 869187523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 870187523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 871093773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 872093773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 873093773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 874093773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 875000023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 876000023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 877000023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 878000023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 878906273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 879906273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 880906273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 881906273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 882812523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 883812523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 884812523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 885812523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 886718773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 887718773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 888718773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 889718773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 890625023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 891625023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 892625023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 893625023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 894531273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 895531273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 896531273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 897531273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 898437523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 899437523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 900437523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 901437523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 902343773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 903343773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 904343773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 905343773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 906250023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 907250023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 908250023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 909250023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 910156273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 911156273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 912156273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 913156273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 914062523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 915062523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 916062523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 917062523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 917968773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 918968773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 919968773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 920968773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 921875023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 922875023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 923875023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 924875023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 925781273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 926781273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 927781273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 928781273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 929687523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 930687523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 931687523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 932687523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 933593773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 934593773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 935593773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 936593773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 937500023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 938500023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 939500023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 940500023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 941406273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 942406273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 943406273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 944406273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 945312523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 946312523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 947312523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 947312530500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 948312530500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 949218773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 950218773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 951218773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 952218773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 953125023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 954125023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 955125023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 956125023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 957031273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 958031273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 959031273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 960031273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 960937523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 961937523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 962937523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 963937523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 964843773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 965843773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 966843773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 967843773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 968750023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 969750023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 970750023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 971750023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 972656273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 973656273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 974656273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 975656273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 976562523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 977562523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 978562523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 979562523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 980468773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 981468773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 982468773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 983468773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 984375023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 985375023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 986375023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 987375023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 988281273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 989281273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 990281273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 991281273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 992187523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 993187523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 994187523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 995187523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 996093773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 997093773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 998093773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 999093773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1000000023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1001000023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1002000023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1003000023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1003906273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1004906273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1005906273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1006906273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1007812523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1008812523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1009812523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1010812523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1011718773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1012718773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1013718773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1013718780500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1014718780500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1015625023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1016625023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1017625023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1018625023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1019531273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1020531273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1021531273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1022531273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1023437523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1024437523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1025437523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1026437523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1027343773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1028343773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1029343773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1030343773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1031250023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1032250023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1033250023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1034250023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1035156273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1036156273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1037156273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1038156273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1039062523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1040062523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1041062523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1042062523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1042968773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1043968773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1044968773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1045968773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1046875023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1047875023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1048875023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1049875023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1050781273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1051781273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1052781273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1053781273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1054687523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1055687523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1056687523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1057687523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1058593773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1059593773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1060593773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1061593773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1062500023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1063500023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1064500023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1065500023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1066406273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1067406273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1068406273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1069406273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1070312523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1071312523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1072312523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1073312523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1074218773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1075218773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1076218773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1077218773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1078125023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1079125023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1080125023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1081125023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1082031273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1083031273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1084031273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1085031273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1085937523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1086937523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1087937523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1088937523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1089843773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1090843773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1091843773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1092843773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1093750023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1094750023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1095750023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1096750023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1097656273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1098656273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1099656273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1100656273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1101562523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1102562523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1103562523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1104562523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1105468773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1106468773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1107468773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1108468773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1109375023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1110375023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1111375023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1112375023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1113281273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1114281273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1115281273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1116281273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1117187523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1118187523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1119187523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1120187523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1121093773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1122093773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1123093773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1124093773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1125000023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1126000023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1127000023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1128000023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1128906273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1129906273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1130906273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1131906273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1132812523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1133812523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1134812523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1135812523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1136718773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1137718773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1138718773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1139718773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1140625023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1141625023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1142625023000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1143625023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1144531273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1145531273000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1146531273000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1147531273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1148437523000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1149437523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1150437523000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1151437523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1152343773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1153343773000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1154343773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1155343773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1156250023000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1157250023000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1158250023000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1158250030500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1159250030500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1160338579500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1161338579500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1162338579500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1163338579500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1163338582500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1164338582500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1165338582500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1166338582500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1166338585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1167338585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1168338585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1169338585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1169921898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1170921898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1171921898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1172921898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1173828148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1174828148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1175828148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1176828148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1177734398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1178734398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1179734398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1180734398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1181640648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1182640648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1183640648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1184640648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1185546898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1186546898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1187546898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1188546898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1189453148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1190453148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1191453148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1192453148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1193359398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1194359398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1195359398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1196359398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1197265648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1198265648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1199265648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1200265648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1201171898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1202171898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1203171898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1204171898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1205078148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1206078148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1207078148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1208078148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1208984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1209984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1210984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1211984398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1212890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1213890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1214890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1215890648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1216796898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1217796898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1218796898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1219796898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1220703148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1221703148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1222703148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1223703148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1224609398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1225609398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1226609398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1227609398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1228515648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1229515648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1230515648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1231515648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1232421898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1233421898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1234421898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1235421898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1236328148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1237328148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1238328148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1239328148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1240234398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1241234398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1242234398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1243234398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1244140648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1245140648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1246140648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1247140648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1248046898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1249046898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1250046898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1251046898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1251953148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1252953148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1253953148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1254953148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1255859398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1256859398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1257859398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1258859398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1259765648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1260765648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1261765648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1262765648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1263671898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1264671898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1265671898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1266671898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1267578148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1268578148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1269578148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1270578148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1271484398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1272484398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1273484398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1274484398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1275390648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1276390648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1277390648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1278390648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1279296898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1280296898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1281296898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1282296898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1283203148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1284203148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1285203148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1286203148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1287109398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1288109398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1289109398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1290109398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1291015648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1292015648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1293015648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1294015648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1294921898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1295921898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1296921898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1297921898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1298828148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1299828148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1300828148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1301828148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1302734398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1303734398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1304734398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1305734398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1306640648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1307640648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1308640648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1309640648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1310546898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1311546898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1312546898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1313546898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1314453148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1315453148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1316453148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1317453148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1318359398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1319359398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1320359398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1321359398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1322265648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1323265648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1324265648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1325265648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1326171898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1327171898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1328171898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1329171898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1330078148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1331078148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1332078148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1333078148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1333984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1334984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1335984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1336984398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1337890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1338890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1339890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1340890648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1341796898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1342796898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1343796898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1344796898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1345703148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1346703148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1347703148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1348703148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1349609398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1350609398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1351609398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1352609398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1353515648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1354515648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1355515648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1356515648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1357421898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1358421898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1359421898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1360421898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1361328148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1362328148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1363328148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1364328148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1365234398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1366234398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1367234398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1368234398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1369140648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1370140648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1371140648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1372140648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1373046898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1374046898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1375046898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1376046898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1376953148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1377953148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1378953148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1379953148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1380859398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1381859398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1382859398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1383859398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1384765648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1385765648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1386765648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1387765648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1388671898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1389671898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1390671898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1391671898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1392578148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1393578148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1394578148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1395578148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1396484398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1397484398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1398484398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1399484398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1400390648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1401390648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1402390648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1403390648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1404296898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1405296898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1406296898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1407296898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1408203148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1409203148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1410203148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1411203148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1412109398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1413109398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1414109398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1415109398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1416015648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1417015648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1418015648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1419015648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1419921898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1420921898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1421921898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1422921898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1423828148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1424828148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1425828148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1426828148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1427734398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1428734398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1429734398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1430734398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1431640648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1432640648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1433640648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1434640648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1435546898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1436546898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1437546898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1438546898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1439453148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1440453148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1441453148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1442453148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1443359398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1444359398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1445359398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1446359398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1447265648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1448265648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1449265648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1450265648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1451171898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1452171898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1453171898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1454171898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1455078148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1456078148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1457078148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1458078148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1458984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1459984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1460984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1461984398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1462890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1463890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1464890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1465890648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1466796898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1467796898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1468796898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1469796898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1470703148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1471703148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1472703148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1473703148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1474609398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1475609398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1476609398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1477609398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1478515648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1479515648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1480515648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1481515648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1482421898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1483421898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1484421898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1485421898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1486328148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1487328148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1488328148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1489328148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1490234398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1491234398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1492234398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1493234398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1494140648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1495140648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1496140648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1497140648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1498046898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1499046898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1500046898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1501046898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1501953148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1502953148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1503953148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1504953148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1505859398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1506859398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1507859398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1508859398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1509765648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1510765648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1511765648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1512765648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1513671898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1514671898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1515671898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1516671898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1517578148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1518578148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1519578148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1520578148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1521484398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1522484398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1523484398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1524484398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1525390648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1526390648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1527390648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1528390648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1529296898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1530296898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1531296898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1532296898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1533203148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1534203148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1535203148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1536203148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1537109398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1538109398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1539109398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1540109398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1541015648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1542015648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1543015648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1544015648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1544921898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1545921898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1546921898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1547921898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1548828148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1549828148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1550828148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1551828148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1552734398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1553734398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1554734398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1555734398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1556640648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1557640648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1558640648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1559640648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1560546898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1561546898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1562546898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1563546898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1564453148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1565453148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1566453148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1567453148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1568359398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1569359398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1570359398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1571359398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1572265648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1573265648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1574265648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1575265648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1576171898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1577171898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1578171898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1579171898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1580078148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1581078148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1582078148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1583078148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1583984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1584984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1585984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1586984398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1587890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1588890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1589890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1590890648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1591796898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1592796898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1593796898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1594796898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1595703148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1596703148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1597703148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1598703148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1599609398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1600609398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1601609398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1602609398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1603515648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1604515648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1605515648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1606515648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1607421898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1608421898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1609421898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1610421898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1611328148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1612328148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1613328148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1614328148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1615234398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1616234398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1617234398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1618234398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1619140648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1620140648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1621140648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1622140648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1623046898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1624046898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1625046898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1626046898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1626953148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1627953148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1628953148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1629953148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1630859398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1631859398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1632859398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1633859398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1634765648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1635765648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1636765648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1637765648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1638671898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1639671898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1640671898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1641671898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1642578148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1643578148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1644578148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1645578148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1646484398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1647484398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1648484398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1649484398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1650390648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1651390648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1652390648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1653390648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1654296898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1655296898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1656296898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1657296898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1658203148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1659203148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1660203148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1661203148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1662109398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1663109398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1664109398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1665109398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1666015648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1667015648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1668015648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1669015648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1669921898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1670921898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1671921898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1672921898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1673828148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1674828148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1675828148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1676828148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1677734398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1678734398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1679734398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1680734398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1681640648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1682640648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1683640648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1684640648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1685546898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1686546898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1687546898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1688546898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1689453148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1690453148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1691453148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1692453148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1693359398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1694359398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1695359398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1695359405500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1696359405500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1697265648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1698265648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1699265648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1700265648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1701171898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1702171898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1703171898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1704171898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1705078148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1706078148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1707078148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1707078155500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1708078155500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1708984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1709984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1710984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1711984398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1712890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1713890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1714890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1715890648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1716796898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1717796898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1718796898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1719796898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1720703148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1721703148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1722703148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1723703148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1724609398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1725609398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1726609398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1727609398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1728515648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1729515648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1730515648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1731515648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1732421898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1733421898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1734421898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1735421898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1736328148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1737328148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1738328148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1739328148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1740234398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1741234398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1742234398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1743234398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1744140648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1745140648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1746140648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1746140655500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1747140655500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1748046898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1749046898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1750046898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1751046898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1751953148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1752953148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1753953148000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1754953148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1755859398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1756859398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1757859398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1758859398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1759765648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1760765648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1761765648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1762765648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1763671898000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1764671898000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1765671898000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1766671898000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1767578148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1768578148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1769578148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1769578155500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1770578155500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1771484398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1772484398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1773484398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1774484398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1775390648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1776390648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1777390648000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1778390648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1778390871500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1779390871500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1780390871500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1781390871500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1782226585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1783226585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1784226585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1784226593000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1785226593000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1786132835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1787132835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1788132835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1789132835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1790039085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1791039085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1792039085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1793039085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1793945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1794945335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1795945335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1795945343000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1796945343000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1797851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1798851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1799851585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1800851585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1801757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1802757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1803757835500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1804757835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1805664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1806664085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1807664085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1807664093000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1808664093000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1809570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1810570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1811570335500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1812570335500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1813476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1814476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1815476585500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1816476585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1817382835500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1818382835500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1819382835500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1819382844500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1820382844500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1820383742000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1821383742000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1822383742000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1822383749500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1823383749500.  Starting simulation...
-info: Entering event queue @ 1823383883000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1823383890500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1824383890500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1825383890500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1826383890500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1827148460500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1828148460500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1829148460500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1830148460500.  Starting simulation...
-info: Entering event queue @ 1830148471500.  Starting simulation...
-info: Entering event queue @ 1830148476000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1830148477000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1831148477000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1832148477000.  Starting simulation...
-info: Entering event queue @ 1832148513000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1832148757750.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1833148757750.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1833984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1834984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1835984398000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1836984398000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1837890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1838890648000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1839890648000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1839890655500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1840890655500.  Starting simulation...
-info: Entering event queue @ 1840890668000.  Starting simulation...
-info: Entering event queue @ 1840890674500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1840890679000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1841890679000.  Starting simulation...

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
index caa1e90..3ead642 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                1842697218000                       # Number of ticks simulated
 final_tick                               1842697218000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 189301                       # Simulator instruction rate (inst/s)
-host_op_rate                                   189301                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4767309141                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 353980                       # Number of bytes of host memory used
-host_seconds                                   386.53                       # Real time elapsed on the host
+host_inst_rate                                 281851                       # Simulator instruction rate (inst/s)
+host_op_rate                                   281851                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7098045398                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 310872                       # Number of bytes of host memory used
+host_seconds                                   259.61                       # Real time elapsed on the host
 sim_insts                                    73170192                       # Number of instructions simulated
 sim_ops                                      73170192                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.inst           489152                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data         20102912                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
@@ -375,6 +377,7 @@
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.membus.respLayer2.occupancy          152995500                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                   337398                       # number of replacements
 system.l2c.tags.tagsinuse                65420.701532                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    2472173                       # Total number of references to valid blocks.
@@ -396,6 +399,15 @@
 system.l2c.tags.occ_percent::cpu2.inst       0.032789                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu2.data       0.031610                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.998241                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        65163                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          988                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         5636                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         2991                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55380                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 26143118                       # Number of tag accesses
+system.l2c.tags.data_accesses                26143118                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.inst             520243                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.data             493553                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.inst             124286                       # number of ReadReq hits
@@ -676,6 +688,11 @@
 system.iocache.tags.occ_blocks::tsunami.ide     1.254904                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::tsunami.ide     0.078431                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.078431                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
+system.iocache.tags.data_accesses              375525                       # Number of data accesses
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -1026,6 +1043,13 @@
 system.cpu0.icache.tags.occ_percent::cpu1.inst     0.194517                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::cpu2.inst     0.312998                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.998419                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses         45349405                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        45349405                       # Number of data accesses
 system.cpu0.icache.ReadReq_hits::cpu0.inst     33358489                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::cpu1.inst      7831408                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::cpu2.inst      2239644                       # number of ReadReq hits
@@ -1156,6 +1180,13 @@
 system.cpu0.dcache.tags.occ_percent::cpu1.data     0.257733                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::cpu2.data     0.255131                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          266                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         63261634                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        63261634                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data      4082373                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::cpu1.data      1085171                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::cpu2.data      2396693                       # number of ReadReq hits
@@ -1763,7 +1794,7 @@
 system.cpu2.int_regfile_writes               22654603                       # number of integer regfile writes
 system.cpu2.fp_regfile_reads                    67639                       # number of floating regfile reads
 system.cpu2.fp_regfile_writes                   67817                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                5347337                       # number of misc regfile reads
+system.cpu2.misc_regfile_reads                5361637                       # number of misc regfile reads
 system.cpu2.misc_regfile_writes                256988                       # number of misc regfile writes
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
index 25f2809..d289659 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini

@@ -12,7 +12,7 @@
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -23,7 +23,7 @@
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
@@ -75,7 +75,7 @@
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-arm-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -288,6 +288,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.dcache.tags
@@ -304,6 +305,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.dtb]
@@ -643,6 +645,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.icache.tags
@@ -659,6 +662,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.interrupts]
@@ -713,6 +717,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.cpu.l2cache.tags
@@ -729,6 +734,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.cpu.toL2Bus]
@@ -782,6 +788,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -798,6 +805,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.membus]

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
index 90faba5..ccd2508 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr

@@ -1,7 +1,6 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
-warn: DTB file specified, but no device tree support in kernel
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
@@ -11,22 +10,25 @@
 warn: 	instruction 'mcr dccimvac' unimplemented
 warn: 	instruction 'mcr dccmvau' unimplemented
 warn: 	instruction 'mcr icimvau' unimplemented
-warn: 6117297500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
-warn: 6125706500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
-warn: 6160975500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
-warn: 6176055500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
-warn: 6715294500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
+warn: 6165886500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
+warn: 6172734500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
+warn: 6181171500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
+warn: 6216960500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
+warn: 6232347500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
+warn: 6775306000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
 warn: LCD dual screen mode not supported
-warn: 51807478000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
+warn: 51869237500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr bpiallis' unimplemented
-warn: 2474714862500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
-warn: 2488540668500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2489750451500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
-warn: 2510845218000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2511359133500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2517064152000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
-warn: 2517573704500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
-warn: 2518135055000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
-warn: 2518136146000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
-hack: be nice to actually delete the event here
+warn: 2475417694000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
+warn: 2489281853500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2490491047500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
+warn: 2511643992000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2512158375000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2516381302500: Instruction results do not match! (Values may not actually be integers) Inst: 0xee6b2, checker: 0
+warn: 2516399186500: Instruction results do not match! (Values may not actually be integers) Inst: 0x4001f92c, checker: 0x4001ef10
+warn: 2517881609000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
+warn: 2518389750000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
+warn: 2518949430500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
+warn: 2518950618000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
+warn: 2519498238000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
index 6df74fa..a9e6de1 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout

@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:31:27
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 23 2014 00:07:43
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2524309551500 because m5_exit instruction encountered
+Exiting @ tick 2525131633500 because m5_exit instruction encountered

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index d7c49d4..e81d47f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                2525131633500                       # Number of ticks simulated
 final_tick                               2525131633500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  41051                       # Simulator instruction rate (inst/s)
-host_op_rate                                    52821                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1718892257                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 447424                       # Number of bytes of host memory used
-host_seconds                                  1469.05                       # Real time elapsed on the host
+host_inst_rate                                  63748                       # Simulator instruction rate (inst/s)
+host_op_rate                                    82026                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2669254242                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 403420                       # Number of bytes of host memory used
+host_seconds                                   946.01                       # Real time elapsed on the host
 sim_insts                                    60305678                       # Number of instructions simulated
 sim_ops                                      77596684                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker         2688                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
@@ -928,6 +930,7 @@
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy         40921719549                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                14384927                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          11469310                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            704177                       # Number of conditional branches incorrect
@@ -958,8 +961,8 @@
 system.cpu.checker.dtb.hits                  26214250                       # DTB hits
 system.cpu.checker.dtb.misses                    9498                       # DTB misses
 system.cpu.checker.dtb.accesses              26223748                       # DTB accesses
-system.cpu.checker.itb.inst_hits             61479663                       # ITB inst hits
-system.cpu.checker.itb.inst_misses               4471                       # ITB inst misses
+system.cpu.checker.itb.inst_hits             61479661                       # ITB inst hits
+system.cpu.checker.itb.inst_misses               4473                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
 system.cpu.checker.itb.write_hits                   0                       # DTB write hits
@@ -968,7 +971,7 @@
 system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
 system.cpu.checker.itb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.itb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries             4682                       # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_entries             4683                       # Number of entries that have been flushed from TLB
 system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
 system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
 system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
@@ -976,8 +979,8 @@
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
 system.cpu.checker.itb.inst_accesses         61484134                       # ITB inst accesses
-system.cpu.checker.itb.hits                  61479663                       # DTB hits
-system.cpu.checker.itb.misses                    4471                       # DTB misses
+system.cpu.checker.itb.hits                  61479661                       # DTB hits
+system.cpu.checker.itb.misses                    4473                       # DTB misses
 system.cpu.checker.itb.accesses              61484134                       # DTB accesses
 system.cpu.checker.numCycles                 77882476                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
@@ -1332,6 +1335,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   511.579102                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999178                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999178                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          225                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          150                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          12500309                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         12500309                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     10457750                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        10457750                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      10457750                       # number of demand (read+write) hits
@@ -1432,6 +1443,19 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124721                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.095140                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.783737                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           19                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65375                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           18                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          355                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3055                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6962                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54965                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000290                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997543                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         18784884                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        18784884                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        52523                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10409                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.inst       967861                       # number of ReadReq hits
@@ -1687,6 +1711,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.993331                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999987                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          192                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         101519243                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        101519243                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     13755484                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        13755484                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      7258628                       # number of WriteReq hits
@@ -1846,6 +1877,8 @@
 system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
+system.iocache.tags.data_accesses                   0                       # Number of data accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index 98e6f22..5b8c354 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini

@@ -12,7 +12,7 @@
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -23,7 +23,7 @@
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
@@ -75,7 +75,7 @@
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-arm-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -204,6 +204,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.dcache.tags
@@ -220,6 +221,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.dtb]
@@ -559,6 +561,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.icache.tags
@@ -575,6 +578,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.interrupts]
@@ -738,6 +742,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.dcache.tags
@@ -754,6 +759,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.dtb]
@@ -1093,6 +1099,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.icache.tags
@@ -1109,6 +1116,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.interrupts]
@@ -1188,6 +1196,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -1204,6 +1213,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.l2c]
@@ -1221,6 +1231,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.l2c.tags
@@ -1237,6 +1248,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.membus]

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
index 4ccac5e..5a43c8b 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr

@@ -1,7 +1,6 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
-warn: DTB file specified, but no device tree support in kernel
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
@@ -15,4 +14,3 @@
 warn: LCD dual screen mode not supported
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr icialluis' unimplemented
-hack: be nice to actually delete the event here

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
index 5def9d8..8a51f63 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout

@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:18:35
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 23 2014 00:17:38
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1104038330000 because m5_exit instruction encountered
+Exiting @ tick 1104766159000 because m5_exit instruction encountered

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index fbdae72..3b2b0bf 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                1104766159000                       # Number of ticks simulated
 final_tick                               1104766159000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  49697                       # Simulator instruction rate (inst/s)
-host_op_rate                                    63978                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              891289209                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 450492                       # Number of bytes of host memory used
-host_seconds                                  1239.51                       # Real time elapsed on the host
+host_inst_rate                                  77156                       # Simulator instruction rate (inst/s)
+host_op_rate                                    99328                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1383749494                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 406496                       # Number of bytes of host memory used
+host_seconds                                   798.39                       # Real time elapsed on the host
 sim_insts                                    61600257                       # Number of instructions simulated
 sim_ops                                      79301805                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd     48758784                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker          832                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
@@ -799,6 +801,7 @@
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 system.membus.respLayer2.occupancy        13759512942                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.2                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                    72740                       # number of replacements
 system.l2c.tags.tagsinuse                53860.173191                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    1837966                       # Total number of references to valid blocks.
@@ -822,6 +825,18 @@
 system.l2c.tags.occ_percent::cpu1.inst       0.056491                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.057637                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.821841                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65179                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          312                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3125                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         8680                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        53038                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.994553                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 18564692                       # Number of tag accesses
+system.l2c.tags.data_accesses                18564692                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.dtb.walker        22002                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.itb.walker         4348                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.inst             385872                       # number of ReadReq hits
@@ -1696,8 +1711,8 @@
 system.cpu0.int_regfile_writes               34094081                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                     3288                       # number of floating regfile reads
 system.cpu0.fp_regfile_writes                     904                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads               13012931                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                451079                       # number of misc regfile writes
+system.cpu0.misc_regfile_reads               13200315                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                451289                       # number of misc regfile writes
 system.cpu0.icache.tags.replacements           392190                       # number of replacements
 system.cpu0.icache.tags.tagsinuse          510.931857                       # Cycle average of tags in use
 system.cpu0.icache.tags.total_refs            3792228                       # Total number of references to valid blocks.
@@ -1707,6 +1722,14 @@
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   510.931857                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.997914                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.997914                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          210                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          170                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses          4608911                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses         4608911                       # Number of data accesses
 system.cpu0.icache.ReadReq_hits::cpu0.inst      3792228                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total        3792228                       # number of ReadReq hits
 system.cpu0.icache.demand_hits::cpu0.inst      3792228                       # number of demand (read+write) hits
@@ -1799,6 +1822,13 @@
 system.cpu0.dcache.tags.occ_blocks::cpu0.data   459.475838                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.897414                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.897414                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          179                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          314                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         45150578                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        45150578                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data      5781234                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total        5781234                       # number of ReadReq hits
 system.cpu0.dcache.WriteReq_hits::cpu0.data      3158881                       # number of WriteReq hits
@@ -2267,8 +2297,8 @@
 system.cpu1.int_regfile_writes               55271640                       # number of integer regfile writes
 system.cpu1.fp_regfile_reads                     5031                       # number of floating regfile reads
 system.cpu1.fp_regfile_writes                    2324                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads               18454230                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                405462                       # number of misc regfile writes
+system.cpu1.misc_regfile_reads               18630847                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                405526                       # number of misc regfile writes
 system.cpu1.icache.tags.replacements           595825                       # number of replacements
 system.cpu1.icache.tags.tagsinuse          480.685801                       # Cycle average of tags in use
 system.cpu1.icache.tags.total_refs            6935518                       # Total number of references to valid blocks.
@@ -2278,6 +2308,12 @@
 system.cpu1.icache.tags.occ_blocks::cpu1.inst   480.685801                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.938839                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.938839                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          510                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses          8173146                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         8173146                       # Number of data accesses
 system.cpu1.icache.ReadReq_hits::cpu1.inst      6935518                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total        6935518                       # number of ReadReq hits
 system.cpu1.icache.demand_hits::cpu1.inst      6935518                       # number of demand (read+write) hits
@@ -2370,6 +2406,11 @@
 system.cpu1.dcache.tags.occ_blocks::cpu1.data   473.291027                       # Average occupied blocks per requestor
 system.cpu1.dcache.tags.occ_percent::cpu1.data     0.924397                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_percent::total     0.924397                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          354                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          354                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.691406                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         58866831                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        58866831                       # Number of data accesses
 system.cpu1.dcache.ReadReq_hits::cpu1.data      8309635                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total        8309635                       # number of ReadReq hits
 system.cpu1.dcache.WriteReq_hits::cpu1.data      4139080                       # number of WriteReq hits
@@ -2529,6 +2570,8 @@
 system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
+system.iocache.tags.data_accesses                   0                       # Number of data accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index 49d73e9..276d3e8 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini

@@ -12,7 +12,7 @@
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -23,7 +23,7 @@
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
@@ -75,7 +75,7 @@
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-arm-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -204,6 +204,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.dcache.tags
@@ -220,6 +221,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.dtb]
@@ -559,6 +561,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.icache.tags
@@ -575,6 +578,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.interrupts]
@@ -629,6 +633,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.cpu.l2cache.tags
@@ -645,6 +650,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.cpu.toL2Bus]
@@ -698,6 +704,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -714,6 +721,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.membus]

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
index eda827f..4174229 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr

@@ -1,7 +1,6 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
-warn: DTB file specified, but no device tree support in kernel
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
@@ -14,4 +13,3 @@
 warn: LCD dual screen mode not supported
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr bpiallis' unimplemented
-hack: be nice to actually delete the event here

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
index 3406cd0..d1ec33d 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout

@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:15:54
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 23 2014 00:04:18
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2524309551500 because m5_exit instruction encountered
+Exiting @ tick 2525131633500 because m5_exit instruction encountered

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index 65955f3..6bfde3a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                2525131633500                       # Number of ticks simulated
 final_tick                               2525131633500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  49653                       # Simulator instruction rate (inst/s)
-host_op_rate                                    63890                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2079077169                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 446400                       # Number of bytes of host memory used
-host_seconds                                  1214.54                       # Real time elapsed on the host
+host_inst_rate                                  76415                       # Simulator instruction rate (inst/s)
+host_op_rate                                    98325                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3199664494                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 402400                       # Number of bytes of host memory used
+host_seconds                                   789.19                       # Real time elapsed on the host
 sim_insts                                    60305678                       # Number of instructions simulated
 sim_ops                                      77596684                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker         2688                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
@@ -928,6 +930,7 @@
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy         40921719549                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                14384927                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          11469310                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            704177                       # Number of conditional branches incorrect
@@ -1287,6 +1290,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   511.579102                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999178                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999178                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          225                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          150                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          12500309                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         12500309                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     10457750                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        10457750                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      10457750                       # number of demand (read+write) hits
@@ -1387,6 +1398,19 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124721                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.095140                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.783737                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           19                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65375                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           18                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          355                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3055                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6962                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54965                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000290                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997543                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         18784884                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        18784884                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        52523                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10409                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.inst       967861                       # number of ReadReq hits
@@ -1642,6 +1666,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.993331                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999987                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          192                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         101519243                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        101519243                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     13755484                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        13755484                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      7258628                       # number of WriteReq hits
@@ -1801,6 +1832,8 @@
 system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
+system.iocache.tags.data_accesses                   0                       # Number of data accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
index 745161c..bf231cd 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini

@@ -12,7 +12,7 @@
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -23,12 +23,12 @@
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
 mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -75,7 +75,7 @@
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-arm-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -137,6 +137,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.dcache.tags
@@ -153,6 +154,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.dtb]
@@ -185,6 +187,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.icache.tags
@@ -201,6 +204,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.interrupts]
@@ -819,6 +823,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -835,6 +840,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.l2c]
@@ -852,6 +858,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.l2c.tags
@@ -868,6 +875,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.membus]

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
index b4a6065..d17b0e3 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr

@@ -1,14 +1,12 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
-warn: DTB file specified, but no device tree support in kernel
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
 warn: The ccsidr register isn't implemented and always reads as 0.
 warn: 	instruction 'mcr bpiallis' unimplemented
 warn: 	instruction 'mcr icialluis' unimplemented
-hack: be nice to actually delete the event here
 warn: 	instruction 'mcr dccimvac' unimplemented
 warn: 	instruction 'mcr dccmvau' unimplemented
 warn: 	instruction 'mcr icimvau' unimplemented
@@ -27,3 +25,5 @@
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
index 7de6a94..0571464 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout

@@ -1,4144 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:10:22
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 23 2014 00:23:40
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-info: Using bootloader at address 0x80000000
-info: Entering event queue @ 0.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1000000000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2000000000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2000002000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3000002000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3000005000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4000005000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 5000005000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5000005500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 6000005500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 6000011500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 7000011500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 8000011500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 8000193000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 9000193000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 9000195500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 10000195500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 11000195500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 11000203000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 12000203000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 12000210500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 13000210500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 14000210500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 14000218000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 15000218000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 15000660500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 16000660500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 17000660500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 17000668000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 18000668000.  Starting simulation...
-info: Entering event queue @ 26061002500.  Starting simulation...
-info: Entering event queue @ 26061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 26061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 27061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 28061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 29061009500.  Starting simulation...
-info: Entering event queue @ 36061002500.  Starting simulation...
-info: Entering event queue @ 36061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 36061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 37061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 38061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 38061018500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 39061018500.  Starting simulation...
-info: Entering event queue @ 39061063500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 39061151000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 40061151000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 41061151000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 41061158500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 42061158500.  Starting simulation...
-info: Entering event queue @ 42061194500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 42061214750.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 43061214750.  Starting simulation...
-switching cpus
-info: Entering event queue @ 43061215000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 44061215000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 44061215500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 45061215500.  Starting simulation...
-info: Entering event queue @ 45061226000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 45061230500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 46061230500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 47061230500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 47061231000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 48061231000.  Starting simulation...
-info: Entering event queue @ 48061238500.  Starting simulation...
-info: Entering event queue @ 48061242500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 48061247000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 49061247000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 50061247000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 51061247000.  Starting simulation...
-info: Entering event queue @ 56061002500.  Starting simulation...
-info: Entering event queue @ 56061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 56061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 57061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 58061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 59061014000.  Starting simulation...
-info: Entering event queue @ 66061002500.  Starting simulation...
-info: Entering event queue @ 66061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 66061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 67061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 68061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 69061009500.  Starting simulation...
-info: Entering event queue @ 76061002500.  Starting simulation...
-info: Entering event queue @ 76061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 76061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 77061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 78061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 79061014000.  Starting simulation...
-info: Entering event queue @ 86061002500.  Starting simulation...
-info: Entering event queue @ 86061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 86061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 87061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 88061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 89061009500.  Starting simulation...
-info: Entering event queue @ 96061002500.  Starting simulation...
-info: Entering event queue @ 96061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 96061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 97061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 98061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 99061009500.  Starting simulation...
-info: Entering event queue @ 106061002500.  Starting simulation...
-info: Entering event queue @ 106061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 106061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 107061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 108061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 109061009500.  Starting simulation...
-info: Entering event queue @ 116061002500.  Starting simulation...
-info: Entering event queue @ 116061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 116061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 117061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 118061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 119061009500.  Starting simulation...
-info: Entering event queue @ 126061002500.  Starting simulation...
-info: Entering event queue @ 126061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 126061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 127061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 128061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 129061014000.  Starting simulation...
-info: Entering event queue @ 136061002500.  Starting simulation...
-info: Entering event queue @ 136206506250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 136206509000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 137206509000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 138206509000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 139206509000.  Starting simulation...
-info: Entering event queue @ 146061002500.  Starting simulation...
-info: Entering event queue @ 146061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 146061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 147061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 148061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 149061014000.  Starting simulation...
-info: Entering event queue @ 156061002500.  Starting simulation...
-info: Entering event queue @ 156061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 156061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 157061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 158061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 159061009500.  Starting simulation...
-info: Entering event queue @ 166061002500.  Starting simulation...
-info: Entering event queue @ 166061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 166061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 167061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 168061009500.  Starting simulation...
-info: Entering event queue @ 168904109250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 168904112000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 169904112000.  Starting simulation...
-info: Entering event queue @ 176061002500.  Starting simulation...
-info: Entering event queue @ 176061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 176061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 177061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 178061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 179061009500.  Starting simulation...
-info: Entering event queue @ 186061002500.  Starting simulation...
-info: Entering event queue @ 186061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 186061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 187061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 188061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 189061014000.  Starting simulation...
-info: Entering event queue @ 196061002500.  Starting simulation...
-info: Entering event queue @ 196061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 196061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 197061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 198061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 199061014000.  Starting simulation...
-info: Entering event queue @ 206061002500.  Starting simulation...
-info: Entering event queue @ 206061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 206061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 207061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 208061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 209061009500.  Starting simulation...
-info: Entering event queue @ 216061002500.  Starting simulation...
-info: Entering event queue @ 216061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 216061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 217061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 218061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 219061014000.  Starting simulation...
-info: Entering event queue @ 226061002500.  Starting simulation...
-info: Entering event queue @ 226061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 226061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 227061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 228061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 229061009500.  Starting simulation...
-info: Entering event queue @ 236061002500.  Starting simulation...
-info: Entering event queue @ 236061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 236061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 237061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 238061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 239061014000.  Starting simulation...
-info: Entering event queue @ 246061002500.  Starting simulation...
-info: Entering event queue @ 246061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 246061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 247061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 248061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 249061009500.  Starting simulation...
-info: Entering event queue @ 256061002500.  Starting simulation...
-info: Entering event queue @ 256061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 256061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 257061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 258061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 259061009500.  Starting simulation...
-info: Entering event queue @ 266061002500.  Starting simulation...
-info: Entering event queue @ 267151610250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 267151613000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 268151613000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 269151613000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 270151613000.  Starting simulation...
-info: Entering event queue @ 276061002500.  Starting simulation...
-info: Entering event queue @ 276061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 276061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 277061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 278061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 279061009500.  Starting simulation...
-info: Entering event queue @ 286061002500.  Starting simulation...
-info: Entering event queue @ 286061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 286061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 287061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 288061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 289061014000.  Starting simulation...
-info: Entering event queue @ 296061002500.  Starting simulation...
-info: Entering event queue @ 296061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 296061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 297061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 298061014000.  Starting simulation...
-info: Entering event queue @ 299887862250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 299887865000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 300887865000.  Starting simulation...
-info: Entering event queue @ 306061002500.  Starting simulation...
-info: Entering event queue @ 306061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 306061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 307061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 308061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 309061014000.  Starting simulation...
-info: Entering event queue @ 316061002500.  Starting simulation...
-info: Entering event queue @ 316061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 316061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 317061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 318061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 319061009500.  Starting simulation...
-info: Entering event queue @ 326061002500.  Starting simulation...
-info: Entering event queue @ 326061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 326061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 327061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 328061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 329061009500.  Starting simulation...
-info: Entering event queue @ 336061002500.  Starting simulation...
-info: Entering event queue @ 336061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 336061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 337061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 338061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 339061009500.  Starting simulation...
-info: Entering event queue @ 346061002500.  Starting simulation...
-info: Entering event queue @ 346061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 346061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 347061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 348061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 349061014000.  Starting simulation...
-info: Entering event queue @ 356061002500.  Starting simulation...
-info: Entering event queue @ 356061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 356061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 357061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 358061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 359061014000.  Starting simulation...
-info: Entering event queue @ 366061002500.  Starting simulation...
-info: Entering event queue @ 366061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 366061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 367061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 368061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 369061009500.  Starting simulation...
-info: Entering event queue @ 376061002500.  Starting simulation...
-info: Entering event queue @ 376061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 376061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 377061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 378061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 379061014000.  Starting simulation...
-info: Entering event queue @ 386061002500.  Starting simulation...
-info: Entering event queue @ 386061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 386061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 387061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 388061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 389061009500.  Starting simulation...
-info: Entering event queue @ 396061003500.  Starting simulation...
-info: Entering event queue @ 396061011000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 396061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 397061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 398061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 399061015500.  Starting simulation...
-info: Entering event queue @ 406061002500.  Starting simulation...
-info: Entering event queue @ 406061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 406061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 407061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 408061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 409061009500.  Starting simulation...
-info: Entering event queue @ 416061002500.  Starting simulation...
-info: Entering event queue @ 416061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 416061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 417061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 418061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 419061009500.  Starting simulation...
-info: Entering event queue @ 426061002500.  Starting simulation...
-info: Entering event queue @ 426061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 426061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 427061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 428061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 429061009500.  Starting simulation...
-info: Entering event queue @ 436061002500.  Starting simulation...
-info: Entering event queue @ 436061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 436061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 437061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 438061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 439061009500.  Starting simulation...
-info: Entering event queue @ 446061002500.  Starting simulation...
-info: Entering event queue @ 446061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 446061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 447061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 448061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 449061014000.  Starting simulation...
-info: Entering event queue @ 456061003500.  Starting simulation...
-info: Entering event queue @ 456061012000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 456061016500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 457061016500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 458061016500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 459061016500.  Starting simulation...
-info: Entering event queue @ 466061003500.  Starting simulation...
-info: Entering event queue @ 466061011000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 466061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 467061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 468061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 469061015500.  Starting simulation...
-info: Entering event queue @ 476061002500.  Starting simulation...
-info: Entering event queue @ 476061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 476061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 477061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 478061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 479061009500.  Starting simulation...
-info: Entering event queue @ 486061002500.  Starting simulation...
-info: Entering event queue @ 486061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 486061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 487061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 488061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 489061009500.  Starting simulation...
-info: Entering event queue @ 496061002500.  Starting simulation...
-info: Entering event queue @ 496305189250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 496305192000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 497305192000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 498305192000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 499305192000.  Starting simulation...
-info: Entering event queue @ 506061002500.  Starting simulation...
-info: Entering event queue @ 506061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 506061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 507061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 508061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 509061014000.  Starting simulation...
-info: Entering event queue @ 516061002500.  Starting simulation...
-info: Entering event queue @ 516061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 516061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 517061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 518061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 519061014000.  Starting simulation...
-info: Entering event queue @ 526061002500.  Starting simulation...
-info: Entering event queue @ 526061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 526061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 527061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 528061009500.  Starting simulation...
-info: Entering event queue @ 529041477250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 529041480000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 530041480000.  Starting simulation...
-info: Entering event queue @ 536061002500.  Starting simulation...
-info: Entering event queue @ 536061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 536061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 537061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 538061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 539061014000.  Starting simulation...
-info: Entering event queue @ 546061002500.  Starting simulation...
-info: Entering event queue @ 546061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 546061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 547061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 548061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 549061009500.  Starting simulation...
-info: Entering event queue @ 556061002500.  Starting simulation...
-info: Entering event queue @ 556061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 556061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 557061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 558061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 559061014000.  Starting simulation...
-info: Entering event queue @ 566061002500.  Starting simulation...
-info: Entering event queue @ 566061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 566061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 567061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 568061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 569061009500.  Starting simulation...
-info: Entering event queue @ 576061002500.  Starting simulation...
-info: Entering event queue @ 576061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 576061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 577061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 578061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 579061009500.  Starting simulation...
-info: Entering event queue @ 586061002500.  Starting simulation...
-info: Entering event queue @ 586061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 586061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 587061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 588061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 589061009500.  Starting simulation...
-info: Entering event queue @ 596061002500.  Starting simulation...
-info: Entering event queue @ 596061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 596061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 597061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 598061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 599061009500.  Starting simulation...
-info: Entering event queue @ 606061002500.  Starting simulation...
-info: Entering event queue @ 606061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 606061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 607061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 608061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 609061014000.  Starting simulation...
-info: Entering event queue @ 616061003500.  Starting simulation...
-info: Entering event queue @ 616061010500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 616061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 617061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 618061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 619061015000.  Starting simulation...
-info: Entering event queue @ 626061003500.  Starting simulation...
-info: Entering event queue @ 627250298250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 627250301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 628250301000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 629250301000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 630250301000.  Starting simulation...
-info: Entering event queue @ 636061002500.  Starting simulation...
-info: Entering event queue @ 636061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 636061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 637061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 638061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 639061009500.  Starting simulation...
-info: Entering event queue @ 646061002500.  Starting simulation...
-info: Entering event queue @ 646061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 646061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 647061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 648061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 649061009500.  Starting simulation...
-info: Entering event queue @ 656061002500.  Starting simulation...
-info: Entering event queue @ 656061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 656061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 657061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 658061009500.  Starting simulation...
-info: Entering event queue @ 659986582250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 659986585000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 660986585000.  Starting simulation...
-info: Entering event queue @ 666061002500.  Starting simulation...
-info: Entering event queue @ 666061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 666061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 667061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 668061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 669061014000.  Starting simulation...
-info: Entering event queue @ 676061002500.  Starting simulation...
-info: Entering event queue @ 676061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 676061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 677061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 678061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 679061014000.  Starting simulation...
-info: Entering event queue @ 686061002500.  Starting simulation...
-info: Entering event queue @ 686061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 686061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 687061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 688061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 689061009500.  Starting simulation...
-info: Entering event queue @ 696061002500.  Starting simulation...
-info: Entering event queue @ 696061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 696061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 697061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 698061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 699061014000.  Starting simulation...
-info: Entering event queue @ 706061002500.  Starting simulation...
-info: Entering event queue @ 706061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 706061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 707061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 708061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 709061009500.  Starting simulation...
-info: Entering event queue @ 716061002500.  Starting simulation...
-info: Entering event queue @ 716061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 716061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 717061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 718061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 719061014000.  Starting simulation...
-info: Entering event queue @ 726061002500.  Starting simulation...
-info: Entering event queue @ 726061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 726061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 727061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 728061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 729061009500.  Starting simulation...
-info: Entering event queue @ 736061002500.  Starting simulation...
-info: Entering event queue @ 736061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 736061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 737061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 738061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 739061009500.  Starting simulation...
-info: Entering event queue @ 746061002500.  Starting simulation...
-info: Entering event queue @ 746061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 746061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 747061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 748061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 749061009500.  Starting simulation...
-info: Entering event queue @ 756061002500.  Starting simulation...
-info: Entering event queue @ 756061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 756061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 757061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 758061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 759061009500.  Starting simulation...
-info: Entering event queue @ 766061002500.  Starting simulation...
-info: Entering event queue @ 766061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 766061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 767061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 768061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 769061014000.  Starting simulation...
-info: Entering event queue @ 776061002500.  Starting simulation...
-info: Entering event queue @ 776061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 776061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 777061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 778061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 779061014000.  Starting simulation...
-info: Entering event queue @ 786061002500.  Starting simulation...
-info: Entering event queue @ 786061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 786061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 787061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 788061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 789061014000.  Starting simulation...
-info: Entering event queue @ 796061002500.  Starting simulation...
-info: Entering event queue @ 796061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 796061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 797061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 798061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 799061009500.  Starting simulation...
-info: Entering event queue @ 806061002500.  Starting simulation...
-info: Entering event queue @ 806061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 806061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 807061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 808061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 809061009500.  Starting simulation...
-info: Entering event queue @ 816061002500.  Starting simulation...
-info: Entering event queue @ 816061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 816061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 817061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 818061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 819061009500.  Starting simulation...
-info: Entering event queue @ 826061002500.  Starting simulation...
-info: Entering event queue @ 826061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 826061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 827061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 828061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 829061014000.  Starting simulation...
-info: Entering event queue @ 836061002500.  Starting simulation...
-info: Entering event queue @ 836061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 836061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 837061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 838061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 839061014000.  Starting simulation...
-info: Entering event queue @ 846061002500.  Starting simulation...
-info: Entering event queue @ 846061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 846061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 847061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 848061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 849061009500.  Starting simulation...
-info: Entering event queue @ 856061002500.  Starting simulation...
-info: Entering event queue @ 856404222250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 856404225000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 857404225000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 858404225000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 859404225000.  Starting simulation...
-info: Entering event queue @ 866061002500.  Starting simulation...
-info: Entering event queue @ 866061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 866061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 867061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 868061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 869061009500.  Starting simulation...
-info: Entering event queue @ 876061002500.  Starting simulation...
-info: Entering event queue @ 876061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 876061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 877061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 878061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 879061014000.  Starting simulation...
-info: Entering event queue @ 886061002500.  Starting simulation...
-info: Entering event queue @ 886061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 886061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 887061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 888061009500.  Starting simulation...
-info: Entering event queue @ 889140509250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 889140512000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 890140512000.  Starting simulation...
-info: Entering event queue @ 896061002500.  Starting simulation...
-info: Entering event queue @ 896061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 896061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 897061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 898061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 899061009500.  Starting simulation...
-info: Entering event queue @ 906061002500.  Starting simulation...
-info: Entering event queue @ 906061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 906061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 907061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 908061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 909061009500.  Starting simulation...
-info: Entering event queue @ 916061002500.  Starting simulation...
-info: Entering event queue @ 916061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 916061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 917061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 918061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 919061009500.  Starting simulation...
-info: Entering event queue @ 926061002500.  Starting simulation...
-info: Entering event queue @ 926061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 926061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 927061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 928061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 929061014000.  Starting simulation...
-info: Entering event queue @ 936061003500.  Starting simulation...
-info: Entering event queue @ 936061010500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 936061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 937061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 938061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 939061015000.  Starting simulation...
-info: Entering event queue @ 946061003500.  Starting simulation...
-info: Entering event queue @ 946061011000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 946061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 947061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 948061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 949061015500.  Starting simulation...
-info: Entering event queue @ 956061002500.  Starting simulation...
-info: Entering event queue @ 956061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 956061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 957061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 958061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 959061009500.  Starting simulation...
-info: Entering event queue @ 966061002500.  Starting simulation...
-info: Entering event queue @ 966061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 966061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 967061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 968061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 969061009500.  Starting simulation...
-info: Entering event queue @ 976061002500.  Starting simulation...
-info: Entering event queue @ 976061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 976061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 977061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 978061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 979061009500.  Starting simulation...
-info: Entering event queue @ 986061003500.  Starting simulation...
-info: Entering event queue @ 987349326250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 987349329000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 988349329000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 989349329000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 990349329000.  Starting simulation...
-info: Entering event queue @ 996061002500.  Starting simulation...
-info: Entering event queue @ 996061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 996061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 997061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 998061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 999061014000.  Starting simulation...
-info: Entering event queue @ 1006061002500.  Starting simulation...
-info: Entering event queue @ 1006061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1006061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1007061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1008061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1009061009500.  Starting simulation...
-info: Entering event queue @ 1016061002500.  Starting simulation...
-info: Entering event queue @ 1016061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1016061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1017061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1018061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1019061014000.  Starting simulation...
-info: Entering event queue @ 1026061002500.  Starting simulation...
-info: Entering event queue @ 1026061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1026061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1027061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1028061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1029061009500.  Starting simulation...
-info: Entering event queue @ 1036061002500.  Starting simulation...
-info: Entering event queue @ 1036061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1036061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1037061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1038061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1039061014000.  Starting simulation...
-info: Entering event queue @ 1046061002500.  Starting simulation...
-info: Entering event queue @ 1046061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1046061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1047061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1048061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1049061009500.  Starting simulation...
-info: Entering event queue @ 1056061002500.  Starting simulation...
-info: Entering event queue @ 1056061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1056061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1057061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1058061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1059061009500.  Starting simulation...
-info: Entering event queue @ 1066061002500.  Starting simulation...
-info: Entering event queue @ 1066061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1066061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1067061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1068061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1069061009500.  Starting simulation...
-info: Entering event queue @ 1076061002500.  Starting simulation...
-info: Entering event queue @ 1076061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1076061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1077061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1078061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1079061009500.  Starting simulation...
-info: Entering event queue @ 1086061002500.  Starting simulation...
-info: Entering event queue @ 1086061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1086061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1087061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1088061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1089061014000.  Starting simulation...
-info: Entering event queue @ 1096061003500.  Starting simulation...
-info: Entering event queue @ 1096061010500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1096061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1097061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1098061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1099061015000.  Starting simulation...
-info: Entering event queue @ 1106061003500.  Starting simulation...
-info: Entering event queue @ 1106061011000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1106061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1107061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1108061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1109061015500.  Starting simulation...
-info: Entering event queue @ 1116061002500.  Starting simulation...
-info: Entering event queue @ 1116061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1116061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1117061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1118061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1119061009500.  Starting simulation...
-info: Entering event queue @ 1126061002500.  Starting simulation...
-info: Entering event queue @ 1126061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1126061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1127061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1128061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1129061009500.  Starting simulation...
-info: Entering event queue @ 1136061002500.  Starting simulation...
-info: Entering event queue @ 1136061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1136061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1137061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1138061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1139061009500.  Starting simulation...
-info: Entering event queue @ 1146061002500.  Starting simulation...
-info: Entering event queue @ 1146061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1146061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1147061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1148061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1149061014000.  Starting simulation...
-info: Entering event queue @ 1156061002500.  Starting simulation...
-info: Entering event queue @ 1156061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1156061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1157061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1158061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1159061014000.  Starting simulation...
-info: Entering event queue @ 1166061002500.  Starting simulation...
-info: Entering event queue @ 1166061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1166061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1167061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1168061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1169061009500.  Starting simulation...
-info: Entering event queue @ 1176061002500.  Starting simulation...
-info: Entering event queue @ 1176061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1176061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1177061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1178061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1179061014000.  Starting simulation...
-info: Entering event queue @ 1186061002500.  Starting simulation...
-info: Entering event queue @ 1186061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1186061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1187061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1188061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1189061009500.  Starting simulation...
-info: Entering event queue @ 1196061003500.  Starting simulation...
-info: Entering event queue @ 1196061011000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1196061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1197061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1198061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1199061015500.  Starting simulation...
-info: Entering event queue @ 1206061002500.  Starting simulation...
-info: Entering event queue @ 1206061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1206061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1207061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1208061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1209061009500.  Starting simulation...
-info: Entering event queue @ 1216061002500.  Starting simulation...
-info: Entering event queue @ 1216502945250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1216502948000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1217502948000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1218502948000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1219502948000.  Starting simulation...
-info: Entering event queue @ 1226061002500.  Starting simulation...
-info: Entering event queue @ 1226061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1226061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1227061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1228061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1229061009500.  Starting simulation...
-info: Entering event queue @ 1236061002500.  Starting simulation...
-info: Entering event queue @ 1236061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1236061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1237061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1238061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1239061009500.  Starting simulation...
-info: Entering event queue @ 1246061002500.  Starting simulation...
-info: Entering event queue @ 1246061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1246061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1247061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1248061014000.  Starting simulation...
-info: Entering event queue @ 1249239189250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1249239192000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1250239192000.  Starting simulation...
-info: Entering event queue @ 1256061003500.  Starting simulation...
-info: Entering event queue @ 1256061010500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1256061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1257061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1258061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1259061015000.  Starting simulation...
-info: Entering event queue @ 1266061003500.  Starting simulation...
-info: Entering event queue @ 1266061011000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1266061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1267061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1268061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1269061015500.  Starting simulation...
-info: Entering event queue @ 1276061002500.  Starting simulation...
-info: Entering event queue @ 1276061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1276061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1277061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1278061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1279061009500.  Starting simulation...
-info: Entering event queue @ 1286061002500.  Starting simulation...
-info: Entering event queue @ 1286061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1286061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1287061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1288061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1289061009500.  Starting simulation...
-info: Entering event queue @ 1296061002500.  Starting simulation...
-info: Entering event queue @ 1296061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1296061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1297061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1298061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1299061009500.  Starting simulation...
-info: Entering event queue @ 1306061002500.  Starting simulation...
-info: Entering event queue @ 1306061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1306061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1307061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1308061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1309061014000.  Starting simulation...
-info: Entering event queue @ 1316061002500.  Starting simulation...
-info: Entering event queue @ 1316061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1316061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1317061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1318061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1319061014000.  Starting simulation...
-info: Entering event queue @ 1326061002500.  Starting simulation...
-info: Entering event queue @ 1326061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1326061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1327061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1328061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1329061009500.  Starting simulation...
-info: Entering event queue @ 1336061002500.  Starting simulation...
-info: Entering event queue @ 1336061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1336061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1337061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1338061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1339061014000.  Starting simulation...
-info: Entering event queue @ 1346061002500.  Starting simulation...
-info: Entering event queue @ 1347448013250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1347448016000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1348448016000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1349448016000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1350448016000.  Starting simulation...
-info: Entering event queue @ 1356061002500.  Starting simulation...
-info: Entering event queue @ 1356061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1356061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1357061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1358061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1359061014000.  Starting simulation...
-info: Entering event queue @ 1366061002500.  Starting simulation...
-info: Entering event queue @ 1366061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1366061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1367061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1368061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1369061009500.  Starting simulation...
-info: Entering event queue @ 1376061002500.  Starting simulation...
-info: Entering event queue @ 1376061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1376061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1377061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1378061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1379061009500.  Starting simulation...
-info: Entering event queue @ 1386061002500.  Starting simulation...
-info: Entering event queue @ 1386061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1386061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1387061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1388061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1389061009500.  Starting simulation...
-info: Entering event queue @ 1396061002500.  Starting simulation...
-info: Entering event queue @ 1396061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1396061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1397061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1398061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1399061009500.  Starting simulation...
-info: Entering event queue @ 1406061002500.  Starting simulation...
-info: Entering event queue @ 1406061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1406061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1407061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1408061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1409061014000.  Starting simulation...
-info: Entering event queue @ 1416061003500.  Starting simulation...
-info: Entering event queue @ 1416061010500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1416061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1417061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1418061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1419061015000.  Starting simulation...
-info: Entering event queue @ 1426061003500.  Starting simulation...
-info: Entering event queue @ 1426061011000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1426061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1427061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1428061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1429061015500.  Starting simulation...
-info: Entering event queue @ 1436061002500.  Starting simulation...
-info: Entering event queue @ 1436061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1436061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1437061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1438061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1439061009500.  Starting simulation...
-info: Entering event queue @ 1446061002500.  Starting simulation...
-info: Entering event queue @ 1446061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1446061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1447061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1448061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1449061009500.  Starting simulation...
-info: Entering event queue @ 1456061002500.  Starting simulation...
-info: Entering event queue @ 1456061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1456061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1457061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1458061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1459061009500.  Starting simulation...
-info: Entering event queue @ 1466061002500.  Starting simulation...
-info: Entering event queue @ 1466061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1466061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1467061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1468061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1469061014000.  Starting simulation...
-info: Entering event queue @ 1476061002500.  Starting simulation...
-info: Entering event queue @ 1476061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1476061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1477061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1478061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1479061014000.  Starting simulation...
-info: Entering event queue @ 1486061002500.  Starting simulation...
-info: Entering event queue @ 1486061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1486061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1487061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1488061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1489061009500.  Starting simulation...
-info: Entering event queue @ 1496061002500.  Starting simulation...
-info: Entering event queue @ 1496061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1496061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1497061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1498061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1499061014000.  Starting simulation...
-info: Entering event queue @ 1506061002500.  Starting simulation...
-info: Entering event queue @ 1506061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1506061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1507061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1508061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1509061009500.  Starting simulation...
-info: Entering event queue @ 1516061002500.  Starting simulation...
-info: Entering event queue @ 1516061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1516061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1517061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1518061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1519061014000.  Starting simulation...
-info: Entering event queue @ 1526061002500.  Starting simulation...
-info: Entering event queue @ 1526061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1526061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1527061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1528061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1529061009500.  Starting simulation...
-info: Entering event queue @ 1536061002500.  Starting simulation...
-info: Entering event queue @ 1536061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1536061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1537061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1538061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1539061009500.  Starting simulation...
-info: Entering event queue @ 1546061002500.  Starting simulation...
-info: Entering event queue @ 1546061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1546061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1547061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1548061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1549061009500.  Starting simulation...
-info: Entering event queue @ 1556061002500.  Starting simulation...
-info: Entering event queue @ 1556061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1556061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1557061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1558061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1559061009500.  Starting simulation...
-info: Entering event queue @ 1566061002500.  Starting simulation...
-info: Entering event queue @ 1566061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1566061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1567061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1568061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1569061014000.  Starting simulation...
-info: Entering event queue @ 1576061003500.  Starting simulation...
-info: Entering event queue @ 1576601934250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1576601937000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1577601937000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1578601937000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1579601937000.  Starting simulation...
-info: Entering event queue @ 1586061003500.  Starting simulation...
-info: Entering event queue @ 1586061011000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1586061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1587061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1588061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1589061015500.  Starting simulation...
-info: Entering event queue @ 1596061002500.  Starting simulation...
-info: Entering event queue @ 1596061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1596061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1597061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1598061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1599061009500.  Starting simulation...
-info: Entering event queue @ 1606061002500.  Starting simulation...
-info: Entering event queue @ 1606061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1606061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1607061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1608061009500.  Starting simulation...
-info: Entering event queue @ 1609338221250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1609338224000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1610338224000.  Starting simulation...
-info: Entering event queue @ 1616061002500.  Starting simulation...
-info: Entering event queue @ 1616061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1616061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1617061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1618061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1619061009500.  Starting simulation...
-info: Entering event queue @ 1626061002500.  Starting simulation...
-info: Entering event queue @ 1626061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1626061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1627061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1628061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1629061014000.  Starting simulation...
-info: Entering event queue @ 1636061002500.  Starting simulation...
-info: Entering event queue @ 1636061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1636061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1637061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1638061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1639061014000.  Starting simulation...
-info: Entering event queue @ 1646061002500.  Starting simulation...
-info: Entering event queue @ 1646061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1646061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1647061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1648061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1649061009500.  Starting simulation...
-info: Entering event queue @ 1656061002500.  Starting simulation...
-info: Entering event queue @ 1656061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1656061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1657061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1658061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1659061014000.  Starting simulation...
-info: Entering event queue @ 1666061002500.  Starting simulation...
-info: Entering event queue @ 1666061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1666061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1667061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1668061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1669061009500.  Starting simulation...
-info: Entering event queue @ 1676061002500.  Starting simulation...
-info: Entering event queue @ 1676061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1676061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1677061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1678061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1679061014000.  Starting simulation...
-info: Entering event queue @ 1686061002500.  Starting simulation...
-info: Entering event queue @ 1686061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1686061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1687061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1688061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1689061009500.  Starting simulation...
-info: Entering event queue @ 1696061002500.  Starting simulation...
-info: Entering event queue @ 1696061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1696061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1697061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1698061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1699061009500.  Starting simulation...
-info: Entering event queue @ 1706061002500.  Starting simulation...
-info: Entering event queue @ 1707547042250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1707547045000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1708547045000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1709547045000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1710547045000.  Starting simulation...
-info: Entering event queue @ 1716061002500.  Starting simulation...
-info: Entering event queue @ 1716061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1716061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1717061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1718061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1719061009500.  Starting simulation...
-info: Entering event queue @ 1726061002500.  Starting simulation...
-info: Entering event queue @ 1726061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1726061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1727061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1728061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1729061014000.  Starting simulation...
-info: Entering event queue @ 1736061003500.  Starting simulation...
-info: Entering event queue @ 1736061010500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1736061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1737061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1738061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1739061015000.  Starting simulation...
-info: Entering event queue @ 1746061003500.  Starting simulation...
-info: Entering event queue @ 1746061011000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1746061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1747061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1748061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1749061015500.  Starting simulation...
-info: Entering event queue @ 1756061002500.  Starting simulation...
-info: Entering event queue @ 1756061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1756061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1757061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1758061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1759061009500.  Starting simulation...
-info: Entering event queue @ 1766061002500.  Starting simulation...
-info: Entering event queue @ 1766061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1766061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1767061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1768061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1769061009500.  Starting simulation...
-info: Entering event queue @ 1776061002500.  Starting simulation...
-info: Entering event queue @ 1776061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1776061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1777061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1778061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1779061009500.  Starting simulation...
-info: Entering event queue @ 1786061003500.  Starting simulation...
-info: Entering event queue @ 1786061011500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1786061016000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1787061016000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1788061016000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1789061016000.  Starting simulation...
-info: Entering event queue @ 1796061002500.  Starting simulation...
-info: Entering event queue @ 1796061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1796061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1797061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1798061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1799061014000.  Starting simulation...
-info: Entering event queue @ 1806061002500.  Starting simulation...
-info: Entering event queue @ 1806061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1806061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1807061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1808061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1809061009500.  Starting simulation...
-info: Entering event queue @ 1816061002500.  Starting simulation...
-info: Entering event queue @ 1816061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1816061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1817061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1818061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1819061014000.  Starting simulation...
-info: Entering event queue @ 1826061002500.  Starting simulation...
-info: Entering event queue @ 1826061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1826061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1827061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1828061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1829061009500.  Starting simulation...
-info: Entering event queue @ 1836061002500.  Starting simulation...
-info: Entering event queue @ 1836061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1836061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1837061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1838061014000.  Starting simulation...
-info: Entering event queue @ 1838124570250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1838124573000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1839124573000.  Starting simulation...
-info: Entering event queue @ 1846061002500.  Starting simulation...
-info: Entering event queue @ 1846061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1846061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1847061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1848061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1849061009500.  Starting simulation...
-info: Entering event queue @ 1856061002500.  Starting simulation...
-info: Entering event queue @ 1856061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1856061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1857061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1858061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1859061009500.  Starting simulation...
-info: Entering event queue @ 1866061002500.  Starting simulation...
-info: Entering event queue @ 1866061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1866061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1867061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1868061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1869061009500.  Starting simulation...
-info: Entering event queue @ 1876061002500.  Starting simulation...
-info: Entering event queue @ 1876061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1876061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1877061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1878061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1879061009500.  Starting simulation...
-info: Entering event queue @ 1886061002500.  Starting simulation...
-info: Entering event queue @ 1886061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1886061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1887061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1888061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1889061014000.  Starting simulation...
-info: Entering event queue @ 1896061003500.  Starting simulation...
-info: Entering event queue @ 1896061010500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1896061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1897061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1898061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1899061015000.  Starting simulation...
-info: Entering event queue @ 1906061003500.  Starting simulation...
-info: Entering event queue @ 1906061011000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1906061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1907061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1908061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1909061015500.  Starting simulation...
-info: Entering event queue @ 1916061002500.  Starting simulation...
-info: Entering event queue @ 1916061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1916061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1917061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1918061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1919061009500.  Starting simulation...
-info: Entering event queue @ 1926061002500.  Starting simulation...
-info: Entering event queue @ 1926061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1926061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1927061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1928061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1929061009500.  Starting simulation...
-info: Entering event queue @ 1936061002500.  Starting simulation...
-info: Entering event queue @ 1936700970250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1936700973000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1937700973000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1938700973000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1939700973000.  Starting simulation...
-info: Entering event queue @ 1946061002500.  Starting simulation...
-info: Entering event queue @ 1946061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1946061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1947061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1948061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1949061014000.  Starting simulation...
-info: Entering event queue @ 1956061002500.  Starting simulation...
-info: Entering event queue @ 1956061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1956061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1957061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1958061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1959061014000.  Starting simulation...
-info: Entering event queue @ 1966061002500.  Starting simulation...
-info: Entering event queue @ 1966061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1966061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1967061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1968061009500.  Starting simulation...
-info: Entering event queue @ 1969436945250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1969436948000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1970436948000.  Starting simulation...
-info: Entering event queue @ 1976061002500.  Starting simulation...
-info: Entering event queue @ 1976061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1976061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1977061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1978061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1979061014000.  Starting simulation...
-info: Entering event queue @ 1986061002500.  Starting simulation...
-info: Entering event queue @ 1986061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1986061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1987061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1988061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1989061009500.  Starting simulation...
-info: Entering event queue @ 1996061003500.  Starting simulation...
-info: Entering event queue @ 1996061011000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1996061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1997061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1998061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1999061015500.  Starting simulation...
-info: Entering event queue @ 2006061002500.  Starting simulation...
-info: Entering event queue @ 2006061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2006061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2007061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2008061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2009061009500.  Starting simulation...
-info: Entering event queue @ 2016061002500.  Starting simulation...
-info: Entering event queue @ 2016061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2016061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2017061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2018061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2019061009500.  Starting simulation...
-info: Entering event queue @ 2026061002500.  Starting simulation...
-info: Entering event queue @ 2026061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2026061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2027061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2028061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2029061009500.  Starting simulation...
-info: Entering event queue @ 2036061002500.  Starting simulation...
-info: Entering event queue @ 2036061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2036061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2037061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2038061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2039061009500.  Starting simulation...
-info: Entering event queue @ 2046061002500.  Starting simulation...
-info: Entering event queue @ 2046061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2046061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2047061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2048061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2049061014000.  Starting simulation...
-info: Entering event queue @ 2056061003500.  Starting simulation...
-info: Entering event queue @ 2056061010500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2056061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2057061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2058061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2059061015000.  Starting simulation...
-info: Entering event queue @ 2066061003500.  Starting simulation...
-info: Entering event queue @ 2067645765250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2067645768000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2068645768000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2069645768000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2070645768000.  Starting simulation...
-info: Entering event queue @ 2076061002500.  Starting simulation...
-info: Entering event queue @ 2076061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2076061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2077061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2078061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2079061009500.  Starting simulation...
-info: Entering event queue @ 2086061002500.  Starting simulation...
-info: Entering event queue @ 2086061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2086061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2087061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2088061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2089061009500.  Starting simulation...
-info: Entering event queue @ 2096061002500.  Starting simulation...
-info: Entering event queue @ 2096061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2096061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2097061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2098061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2099061009500.  Starting simulation...
-info: Entering event queue @ 2106061002500.  Starting simulation...
-info: Entering event queue @ 2106061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2106061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2107061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2108061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2109061014000.  Starting simulation...
-info: Entering event queue @ 2116061002500.  Starting simulation...
-info: Entering event queue @ 2116061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2116061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2117061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2118061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2119061014000.  Starting simulation...
-info: Entering event queue @ 2126061002500.  Starting simulation...
-info: Entering event queue @ 2126061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2126061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2127061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2128061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2129061009500.  Starting simulation...
-info: Entering event queue @ 2136061002500.  Starting simulation...
-info: Entering event queue @ 2136061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2136061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2137061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2138061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2139061014000.  Starting simulation...
-info: Entering event queue @ 2146061002500.  Starting simulation...
-info: Entering event queue @ 2146061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2146061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2147061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2148061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2149061009500.  Starting simulation...
-info: Entering event queue @ 2156061002500.  Starting simulation...
-info: Entering event queue @ 2156061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2156061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2157061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2158061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2159061014000.  Starting simulation...
-info: Entering event queue @ 2166061002500.  Starting simulation...
-info: Entering event queue @ 2166061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2166061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2167061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2168061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2169061009500.  Starting simulation...
-info: Entering event queue @ 2176061002500.  Starting simulation...
-info: Entering event queue @ 2176061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2176061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2177061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2178061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2179061009500.  Starting simulation...
-info: Entering event queue @ 2186061002500.  Starting simulation...
-info: Entering event queue @ 2186061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2186061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2187061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2188061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2189061009500.  Starting simulation...
-info: Entering event queue @ 2196061002500.  Starting simulation...
-info: Entering event queue @ 2196061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2196061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2197061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2198061009500.  Starting simulation...
-info: Entering event queue @ 2198295410250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2198295413000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2199295413000.  Starting simulation...
-info: Entering event queue @ 2206061002500.  Starting simulation...
-info: Entering event queue @ 2206061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2206061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2207061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2208061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2209061014000.  Starting simulation...
-info: Entering event queue @ 2216061003500.  Starting simulation...
-info: Entering event queue @ 2216061010500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2216061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2217061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2218061015000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2219061015000.  Starting simulation...
-info: Entering event queue @ 2226061003500.  Starting simulation...
-info: Entering event queue @ 2226061011000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2226061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2227061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2228061015500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2229061015500.  Starting simulation...
-info: Entering event queue @ 2236061002500.  Starting simulation...
-info: Entering event queue @ 2236061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2236061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2237061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2238061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2239061009500.  Starting simulation...
-info: Entering event queue @ 2246061002500.  Starting simulation...
-info: Entering event queue @ 2246061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2246061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2247061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2248061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2249061009500.  Starting simulation...
-info: Entering event queue @ 2256061002500.  Starting simulation...
-info: Entering event queue @ 2256061009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2256061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2257061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2258061009500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2259061009500.  Starting simulation...
-info: Entering event queue @ 2266061002500.  Starting simulation...
-info: Entering event queue @ 2266061009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2266061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2267061014000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2268061014000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2268061021500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2269061021500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2269061148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2270061148000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2271061148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2271061155500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2272061155500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2272061191000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2273061191000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2274061191000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2274061278000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2275061278000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2275061305000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2276061305000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2277061305000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2277061449000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2278061449000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2278061476000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2279061476000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2280061476000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2280061529000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2281061529000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2281070598000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2282070598000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2283070598000.  Starting simulation...
-info: Entering event queue @ 2283070605500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2283070607500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2284070607500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2284072321000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2285072321000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2286072321000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2286072412000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2287072412000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2287072517000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2288072517000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2289072517000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2289072627000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2290072627000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2290072768000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2291072768000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2292072768000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2292072780000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2293072780000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2293072888000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2294072888000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2295072888000.  Starting simulation...
-info: Entering event queue @ 2296800002250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2296800005000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2297800005000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2297800079000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2298800079000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2299800079000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2299800134000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2300800134000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2300800209000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2301800209000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2302800209000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2302800293000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2303800293000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2303800354000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2304800354000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2305800354000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2305800437000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2306800437000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2306800538000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2307800538000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2308800538000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2308800680000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2309800680000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2309800703000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2310800703000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2311800703000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2311800722000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2312800722000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2312800881000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2313800881000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2314800881000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2314800888500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2315800888500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2315801041000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2316801041000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2317801041000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2317801187000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2318801187000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2318801316000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2319801316000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2320801316000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2320801362000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2321801362000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2321801451000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2322801451000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2323801451000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2323801593000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2324801593000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2324801757000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2325801757000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2326801757000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2326801907000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2327801907000.  Starting simulation...
-info: Entering event queue @ 2329536286250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2329536289000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2330536289000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2331536289000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2331536409000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2332536409000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2332536496000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2333536496000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2334536496000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2334536578000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2335536578000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2335536696000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2336536696000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2337536696000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2337536812000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2338536812000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2338536969000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2339536969000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2340536969000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2340536997000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2341536997000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2341537098500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2342537098500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2343537098500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2343537168000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2344537168000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2344537177500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2345537177500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2346537177500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2346537288000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2347537288000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2347537394000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2348537394000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2349537394000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2349537514000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2350537514000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2350537663000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2351537663000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2352537663000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2352537779000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2353537779000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2353537905000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2354537905000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2355537905000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2355538017000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2356538017000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2356538152000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2357538152000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2358538152000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2358538294000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2359538294000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2359542534000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2360542534000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2361542534000.  Starting simulation...
-info: Entering event queue @ 2362129237250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2362129240000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2363129240000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2363133658000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2364133658000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2365133658000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2365133769000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2366133769000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2366133837000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2367133837000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2368133837000.  Starting simulation...
-info: Entering event queue @ 2368133844500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2368133845000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2369133845000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2369133852500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2370133852500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2371133852500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2371134001000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2372134001000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2372143233000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2373143233000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2374143233000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2374143240500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2375143240500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2375145136500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2376145136500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2377145136500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2377145199000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2378145199000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2378149152000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2379149152000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2379149152500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2380149152500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2380149276000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2381149276000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2381149328000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2382149328000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2383149328000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2383149380000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2384149380000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2384149451500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2385149451500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2386149451500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2386149459000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2387149459000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2387152521500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2388152521500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2389152521500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2389152529000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2390152529000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2390152536500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2391152536500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2392152536500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2392152544000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2393152544000.  Starting simulation...
-info: Entering event queue @ 2395010782250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2395010785000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2396010785000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2396010785500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2397010785500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2397010793000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2398010793000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2398010844000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2399010844000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2399010844500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2400010844500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2400010852000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2401010852000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2401010917000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2402010917000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2403010917000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2403010924500.  Starting simulation...

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index 3eab7d5..f17311f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt

@@ -4,25 +4,15 @@
 sim_ticks                                2403658742000                       # Number of ticks simulated
 final_tick                               2403658742000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 141358                       # Simulator instruction rate (inst/s)
-host_op_rate                                   181555                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5632122143                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 447420                       # Number of bytes of host memory used
-host_seconds                                   426.78                       # Real time elapsed on the host
+host_inst_rate                                 228698                       # Simulator instruction rate (inst/s)
+host_op_rate                                   293732                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9112018126                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 403420                       # Number of bytes of host memory used
+host_seconds                                   263.79                       # Real time elapsed on the host
 sim_insts                                    60328128                       # Number of instructions simulated
 sim_ops                                      77483556                       # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    114819072                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
@@ -530,6 +520,18 @@
 system.physmem.avgGap                       172554.83                       # Average gap between requests
 system.physmem.pageHitRate                      99.64                       # Row buffer hit rate, read and write combined
 system.physmem.prechargeAllPercent               0.75                       # Percentage of time for which DRAM has all the banks in precharge state
+system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
 system.membus.throughput                     55672581                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq            13813538                       # Transaction distribution
 system.membus.trans_dist::ReadResp           13813538                       # Transaction distribution
@@ -566,6 +568,7 @@
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.membus.respLayer2.occupancy        30355600750                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                    63253                       # number of replacements
 system.l2c.tags.tagsinuse                50392.264505                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    1749443                       # Total number of references to valid blocks.
@@ -597,6 +600,18 @@
 system.l2c.tags.occ_percent::cpu2.inst       0.025666                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu2.data       0.024115                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.768925                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023            2                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65394                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          340                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2645                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6480                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55890                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000031                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.997833                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 17683343                       # Number of tag accesses
+system.l2c.tags.data_accesses                17683343                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.dtb.walker         8706                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.itb.walker         3165                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.inst             467858                       # number of ReadReq hits
@@ -1235,6 +1250,14 @@
 system.cpu0.icache.tags.occ_percent::cpu1.inst     0.015011                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::cpu2.inst     0.019937                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999226                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          138                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          158                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses         45450915                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        45450915                       # Number of data accesses
 system.cpu0.icache.ReadReq_hits::cpu0.inst     31849634                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::cpu1.inst      8050768                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::cpu2.inst      3742157                       # number of ReadReq hits
@@ -1365,6 +1388,13 @@
 system.cpu0.dcache.tags.occ_percent::cpu1.data     0.015892                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::cpu2.data     0.013350                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          197                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         98826136                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        98826136                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data      6861592                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::cpu1.data      1819766                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::cpu2.data      4641843                       # number of ReadReq hits
@@ -1988,6 +2018,8 @@
 system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
+system.iocache.tags.data_accesses                   0                       # Number of data accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
index bd21d2c..3aa1712 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini

@@ -12,7 +12,7 @@
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -23,7 +23,7 @@
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
@@ -75,7 +75,7 @@
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-arm-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -204,6 +204,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.dcache.tags
@@ -220,6 +221,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.dtb]
@@ -559,6 +561,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.icache.tags
@@ -575,6 +578,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.interrupts]
@@ -1114,6 +1118,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -1130,6 +1135,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.l2c]
@@ -1147,6 +1153,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.l2c.tags
@@ -1163,6 +1170,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.membus]

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
index c194b71..1059ef8 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr

@@ -1,14 +1,12 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
-warn: DTB file specified, but no device tree support in kernel
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
 warn: The ccsidr register isn't implemented and always reads as 0.
 warn: 	instruction 'mcr bpiallis' unimplemented
 warn: 	instruction 'mcr icialluis' unimplemented
-hack: be nice to actually delete the event here
 warn: 	instruction 'mcr dccimvac' unimplemented
 warn: 	instruction 'mcr dccmvau' unimplemented
 warn: 	instruction 'mcr icimvau' unimplemented
@@ -17,9 +15,3 @@
 warn: 	instruction 'mcr bpiallis' unimplemented
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
index e9eaa0c..74e20af 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout

@@ -1,2622 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:34:20
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 23 2014 00:28:14
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-info: Using bootloader at address 0x80000000
-info: Entering event queue @ 0.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1000000000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1000007500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2000007500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2000060000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 3000060000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3000063500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 4000063500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4000079500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 5000079500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5000082000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 6000082000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 6000085000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 7000085000.  Starting simulation...
-info: Entering event queue @ 7000092500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 7000096500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 8000096500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 8000104000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 9000104000.  Starting simulation...
-info: Entering event queue @ 9000125000.  Starting simulation...
-info: Entering event queue @ 9000130000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 9000134500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 10000134500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 10000250000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 11000250000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 11000557000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 12000557000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 12000567000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 13000567000.  Starting simulation...
-info: Entering event queue @ 13000584000.  Starting simulation...
-info: Entering event queue @ 13000589000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 13000593500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 14000593500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 14000684000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 15000684000.  Starting simulation...
-info: Entering event queue @ 15000698000.  Starting simulation...
-info: Entering event queue @ 15000703000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 15000707500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 16000707500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 16000715000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 17000715000.  Starting simulation...
-info: Entering event queue @ 17000770000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 17000896000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 18000896000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 26407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 27407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 36407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 37407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 46407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 47407630000.  Starting simulation...
-info: Entering event queue @ 48415862250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 48415869750.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 49415869750.  Starting simulation...
-info: Entering event queue @ 49415893500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 49415994500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 50415994500.  Starting simulation...
-info: Entering event queue @ 50416030500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 50416112000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 51416112000.  Starting simulation...
-info: Entering event queue @ 51416127500.  Starting simulation...
-info: Entering event queue @ 51416132000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 51416136500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 52416136500.  Starting simulation...
-info: Entering event queue @ 52416144500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 52416149000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 53416149000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 53416152000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 54416152000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 54416158000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 55416158000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 55416494500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 56416494500.  Starting simulation...
-info: Entering event queue @ 56416502000.  Starting simulation...
-info: Entering event queue @ 56416506500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 56416511000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 57416511000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 66407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 67407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 76407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 77407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 86407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 87407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 96407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 97407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 106407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 107407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 116407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 117407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 126407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 127407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 136407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 137407630000.  Starting simulation...
-info: Entering event queue @ 146407630000.  Starting simulation...
-info: Entering event queue @ 146556126250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 146556129000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 147556129000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 156407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 157407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 166407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 167407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 176407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 177407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 186407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 187407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 196407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 197407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 206407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 207407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 207407637500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 208407637500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 216407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 217407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 226407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 227407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 236407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 237407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 246407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 247407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 256407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 257407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 266407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 267407630000.  Starting simulation...
-info: Entering event queue @ 276407630000.  Starting simulation...
-info: Entering event queue @ 277500885250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 277500888000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 278500888000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 286407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 287407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 296407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 297407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 306407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 307407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 316407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 317407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 326407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 327407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 336407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 337407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 346407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 347407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 356407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 357407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 366407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 367407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 376407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 377407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 386407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 387407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 396407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 397407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 406407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 407407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 416407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 417407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 426407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 427407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 436407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 437407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 446407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 447407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 456407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 457407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 466407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 467407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 476407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 477407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 486407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 487407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 496407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 497407630000.  Starting simulation...
-info: Entering event queue @ 506407630000.  Starting simulation...
-info: Entering event queue @ 506654813250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 506654816000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 507654816000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 516407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 517407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 526407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 527407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 536407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 537407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 546407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 547407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 556407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 557407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 566407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 567407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 576407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 577407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 586407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 587407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 596407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 597407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 606407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 607407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 616407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 617407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 626407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 627407630000.  Starting simulation...
-info: Entering event queue @ 636407630000.  Starting simulation...
-info: Entering event queue @ 637599918250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 637599921000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 638599921000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 646407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 647407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 656407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 657407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 666407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 667407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 676407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 677407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 686407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 687407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 696407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 697407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 706407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 707407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 716407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 717407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 726407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 727407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 736407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 737407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 746407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 747407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 756407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 757407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 766407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 767407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 776407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 777407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 786407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 787407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 796407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 797407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 806407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 807407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 816407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 817407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 826407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 827407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 836407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 837407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 846407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 847407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 856407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 857407630000.  Starting simulation...
-info: Entering event queue @ 866407630000.  Starting simulation...
-info: Entering event queue @ 866753842250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 866753845000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 867753845000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 876407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 877407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 886407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 887407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 896407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 897407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 906407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 907407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 916407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 917407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 926407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 927407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 936407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 937407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 946407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 947407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 956407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 957407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 966407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 967407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 976407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 977407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 986407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 987407630000.  Starting simulation...
-info: Entering event queue @ 996407630000.  Starting simulation...
-info: Entering event queue @ 997698950250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 997698953000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 998698953000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1006407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1007407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1016407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1017407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1026407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1027407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1036407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1037407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1046407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1047407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1056407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1057407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1066407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1067407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1076407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1077407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1086407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1087407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1096407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1097407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1106407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1107407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1116407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1117407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1126407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1127407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1136407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1137407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1146407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1147407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1156407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1157407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1166407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1167407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1176407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1177407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1186407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1187407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1196407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1197407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1206407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1207407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1216407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1217407630000.  Starting simulation...
-info: Entering event queue @ 1226407630000.  Starting simulation...
-info: Entering event queue @ 1226852565250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1226852568000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1227852568000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1236407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1237407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1246407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1247407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1256407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1257407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1266407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1267407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1276407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1277407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1286407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1287407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1296407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1297407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1306407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1307407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1316407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1317407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1326407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1327407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1336407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1337407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1346407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1347407630000.  Starting simulation...
-info: Entering event queue @ 1356407630000.  Starting simulation...
-info: Entering event queue @ 1357797666250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1357797669000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1358797669000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1366407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1367407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1376407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1377407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1386407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1387407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1396407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1397407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1406407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1407407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1416407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1417407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1426407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1427407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1436407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1437407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1446407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1447407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1456407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1457407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1466407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1467407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1476407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1477407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1486407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1487407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1496407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1497407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1506407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1507407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1516407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1517407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1526407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1527407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1536407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1537407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1546407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1547407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1556407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1557407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1566407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1567407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1576407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1577407630000.  Starting simulation...
-info: Entering event queue @ 1586407630000.  Starting simulation...
-info: Entering event queue @ 1586951590250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1586951593000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1587951593000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1596407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1597407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1606407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1607407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1616407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1617407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1626407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1627407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1636407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1637407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1646407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1647407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1656407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1657407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1666407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1667407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1676407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1677407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1686407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1687407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1696407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1697407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1706407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1707407630000.  Starting simulation...
-info: Entering event queue @ 1716407630000.  Starting simulation...
-info: Entering event queue @ 1717896662250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1717896665000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1718896665000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1726407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1727407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1736407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1737407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1746407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1747407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1756407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1757407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1766407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1767407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1776407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1777407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1786407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1787407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1796407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1797407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1806407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1807407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1816407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1817407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1826407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1827407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1836407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1837407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1846407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1847407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1856407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1857407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1866407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1867407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1876407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1877407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1886407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1887407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1896407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1897407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1906407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1907407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1916407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1917407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1926407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1927407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1936407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1937407630000.  Starting simulation...
-info: Entering event queue @ 1946407630000.  Starting simulation...
-info: Entering event queue @ 1947050277250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1947050280000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1948050280000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1956407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1957407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1966407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1967407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1976407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1977407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1986407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1987407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1996407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1997407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2006407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2007407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2016407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2017407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2026407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2027407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2036407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2037407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2046407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2047407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2056407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2057407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2066407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2067407630000.  Starting simulation...
-info: Entering event queue @ 2076407630000.  Starting simulation...
-info: Entering event queue @ 2077995385250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2077995388000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2078995388000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2086407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2087407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2096407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2097407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2106407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2107407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2116407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2117407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2126407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2127407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2136407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2137407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2146407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2147407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2156407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2157407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2166407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2167407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2176407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2177407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2186407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2187407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2196407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2197407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2206407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2207407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2216407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2217407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2226407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2227407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2236407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2237407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2246407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2247407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2256407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2257407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2266407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2267407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2276407630000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2277407630000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2277409537500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2278409537500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2278414867500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2279414867500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2279419426000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2280419426000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2280419476000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2281419476000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2281429116500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2282429116500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2282429246000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2283429246000.  Starting simulation...
-info: Entering event queue @ 2283429488500.  Starting simulation...
-info: Entering event queue @ 2283429494500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2283429499000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2284429499000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2284429592000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2285429592000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2285429739000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2286429739000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2286429753500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2287429753500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2287429870500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2288429870500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2288429988500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2289429988500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2289430124000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2290430124000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2290430180500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2291430180500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2291430236000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2292430236000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2292430259000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2293430259000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2293433076000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2294433076000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2294433155000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2295433155000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2295433172000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2296433172000.  Starting simulation...
-info: Entering event queue @ 2296433181500.  Starting simulation...
-info: Entering event queue @ 2296433186000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2296433190500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2297433190500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2297433312000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2298433312000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2298433344000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2299433344000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2299433455000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2300433455000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2300433479000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2301433479000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2301433503000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2302433503000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2302440698000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2303440698000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2303440805000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2304440805000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2304440909000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2305440909000.  Starting simulation...
-info: Entering event queue @ 2307149622250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2307149625000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2308149625000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2308149782000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2309149782000.  Starting simulation...
-info: Entering event queue @ 2309152871000.  Starting simulation...
-info: Entering event queue @ 2309152877000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2309152881500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2310152881500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2310153091000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2311153091000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2311153129000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2312153129000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2312162803000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2313162803000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2313162841000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2314162841000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2314162969000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2315162969000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2315169643000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2316169643000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2316169714000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2317169714000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2317169776000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2318169776000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2318175119000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2319175119000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2319175239000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2320175239000.  Starting simulation...
-info: Entering event queue @ 2320175450500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2320175458000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2321175458000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2321175591500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2322175591500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2322175626000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2323175626000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2323175647000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2324175647000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2324175714000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2325175714000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2325175854000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2326175854000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2326180829000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2327180829000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2327180923000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2328180923000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2328180942000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2329180942000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2329181056000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2330181056000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2330181099000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2331181099000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2331181224000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2332181224000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2332181371000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2333181371000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2333183918000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2334183918000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2334184003000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2335184003000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2335184065500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2336184065500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2336184220000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2337184220000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2337184247000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2338184247000.  Starting simulation...
-info: Entering event queue @ 2339885909250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2339885912000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2340885912000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2340885975000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2341885975000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2341885983000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2342885983000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2342893450000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2343893450000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2343893492000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2344893492000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2344893590000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2345893590000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2345900652000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2346900652000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2346900696000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2347900696000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2347900767000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2348900767000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2348900774500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2349900774500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2349900793000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2350900793000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2350900953500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2351900953500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2351901376000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2352901376000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2352901383500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2353901383500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2353901423000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2354901423000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2354908569000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2355908569000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2355908584000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2356908584000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2356908737000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2357908737000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2357915083000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2358915083000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2358915112000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2359915112000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2359915187000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2360915187000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2360922523000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2361922523000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2361922658000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2362922658000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2362922750500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2363922750500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2363922762000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2364922762000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2364922771000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2365922771000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2365927824000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2366927824000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2366927896000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2367927896000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2367927978000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2368927978000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2368928076000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2369928076000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2369928159000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2370928159000.  Starting simulation...
-info: Entering event queue @ 2372622506250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2372622509000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2373622509000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2373622667000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2374622667000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2374625947000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2375625947000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2375625991000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2376625991000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2376626046000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2377626046000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2377626053500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2378626053500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2378626119000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2379626119000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2379633260000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2380633260000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2380633388000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2381633388000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2381633484000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2382633484000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2382639954000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2383639954000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2383640101000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2384640101000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2384640241000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2385640241000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2385646694000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2386646694000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2386646793000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2387646793000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2387646908500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2388646908500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2388646947500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2389646947500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2389647000500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2390647000500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2390647107000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2391647107000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2391647193000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2392647193000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2392647232000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2393647232000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2393655582000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2394655582000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2394655705000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2395655705000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2395655800000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2396655800000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2396655896000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2397655896000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2397656000000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2398656000000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2398656109000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2399656109000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2399656252000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2400656252000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2400658939000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2401658939000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2401659076000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2402659076000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2402659185500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2403659185500.  Starting simulation...
-info: Entering event queue @ 2405358441250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2405358444000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2406358444000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2406358469000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2407358469000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2407367356000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2408367356000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2408367376000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2409367376000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2409367470000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2410367470000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2410374541000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2411374541000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2411374671000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2412374671000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2412374731500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2413374731500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2413381673000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2414381673000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2414381740000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2415381740000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2415381765000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2416381765000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2416388872000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2417388872000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2417388890000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2418388890000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2418388899500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2419388899500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2419388941000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2420388941000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2420389055000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2421389055000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2421389132000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2422389132000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2422389169500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2423389169500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2423389212000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2424389212000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2424392828000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2425392828000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2425392965000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2426392965000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2426393102000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2427393102000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2427396556000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2428396556000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2428396645000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2429396645000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2429396754000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2430396754000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2430403859000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2431403859000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2431403964000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2432403964000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2432404100500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2433404100500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2433404250000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2434404250000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2434410611000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2435410611000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2435410707000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2436410707000.  Starting simulation...
-info: Entering event queue @ 2438094729250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2438094732000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2439094732000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2439094850000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2440094850000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2440094895000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2441094895000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2441099330000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2442099330000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2442099486000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2443099486000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2443099600500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2444099600500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2444106551000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2445106551000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2445106624000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2446106624000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2446106663000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2447106663000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2447106677500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2448106677500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2448106732000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2449106732000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2449106788500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2450106788500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2450106864000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2451106864000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2451106954500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2452106954500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2452107027000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2453107027000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2453107165000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2454107165000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2454112628000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2455112628000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2455112711000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2456112711000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2456112857000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2457112857000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2457112869000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2458112869000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2458113021000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2459113021000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2459113070000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2460113070000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2460113176000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2461113176000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2461114992000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2462114992000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2462115142000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2463115142000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2463115302000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2464115302000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2464122382000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2465122382000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2465122453000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2466122453000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2466122567000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2467122567000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2467122667000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2468122667000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2468122726000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2469122726000.  Starting simulation...
-info: Entering event queue @ 2470831329250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2470831332000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2471831332000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2471831399000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2472831399000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2472831434000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2473831434000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2473831443000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2474831443000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2474831496500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2475831496500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2475831610000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2476831610000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2476831728000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2477831728000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2477831824000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2478831824000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2478833712000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2479833712000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2479833747000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2480833747000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2480833839000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2481833839000.  Starting simulation...
-info: Entering event queue @ 2481835884000.  Starting simulation...
-info: Entering event queue @ 2481835889000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2481835893500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2482835893500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2482837674000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2483837674000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2483837738000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2484837738000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2484841149000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2485841149000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2485841199000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2486841199000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2486841323500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2487841323500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2487841419000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2488841419000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2488841557500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2489841557500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2489841714000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2490841714000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2490841815000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2491841815000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2491846012000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2492846012000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2492846092000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2493846092000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2493846192000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2494846192000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2494846274000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2495846274000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2495846428000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2496846428000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2496846578500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2497846578500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2497846655000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2498846655000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2498846726000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2499846726000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2499846861000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2500846861000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2500851435000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2501851435000.  Starting simulation...
-info: Entering event queue @ 2503567610250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2503567613000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2504567613000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2504567726000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2505567726000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2505574981000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2506574981000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2506575012000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2507575012000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2507575052000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2508575052000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2508575160000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2509575160000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2509575287000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2510575287000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2510575294500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2511575294500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2511575312000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2512575312000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2512575405000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2513575405000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2513575444000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2514575444000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2514575602000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2515575602000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2515575628500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2516575628500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2516575659000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2517575659000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2517575698000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2518575698000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2518577085000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2519577085000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2519577132000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2520577132000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2520577256500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2521577256500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2521584198000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2522584198000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2522584259000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2523584259000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2523584372000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2524584372000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2524584455500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2525584455500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2525591164000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2526591164000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2526591230000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2527591230000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2527591238000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2528591238000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2528597259000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2529597259000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2529597411000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2530597411000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2530597561500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2531597561500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2531597646000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2532597646000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2532597765000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2533597765000.  Starting simulation...
-info: Entering event queue @ 2533597774500.  Starting simulation...
-info: Entering event queue @ 2533597779000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2533597780000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2534597780000.  Starting simulation...
-info: Entering event queue @ 2536303549250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2536303552000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2537303552000.  Starting simulation...
-info: Entering event queue @ 2537303556000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2537303560500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2538303560500.  Starting simulation...
-info: Entering event queue @ 2538303568500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2538303573000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2539303573000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2539303580500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2540303580500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2540303606000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2541303606000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2541303613500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2542303613500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2542303621000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2543303621000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2543303628500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2544303628500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2544303636000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2545303636000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2545303749000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2546303749000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2546303779000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2547303779000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2547303786500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2548303786500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2548303794000.  Starting simulation...

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
index 5fef90c..5e74bf3 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                2549345168000                       # Number of ticks simulated
 final_tick                               2549345168000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  48945                       # Simulator instruction rate (inst/s)
-host_op_rate                                    62980                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2068782078                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 448444                       # Number of bytes of host memory used
-host_seconds                                  1232.29                       # Real time elapsed on the host
+host_inst_rate                                  76720                       # Simulator instruction rate (inst/s)
+host_op_rate                                    98719                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3242754050                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 404480                       # Number of bytes of host memory used
+host_seconds                                   786.17                       # Real time elapsed on the host
 sim_insts                                    60314699                       # Number of instructions simulated
 sim_ops                                      77609228                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker         1856                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
@@ -639,6 +641,7 @@
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 system.membus.respLayer2.occupancy        34186627978                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                    64357                       # number of replacements
 system.l2c.tags.tagsinuse                51453.251473                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    1905423                       # Total number of references to valid blocks.
@@ -662,6 +665,18 @@
 system.l2c.tags.occ_percent::cpu1.inst       0.051046                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.044272                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.785114                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023           24                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65363                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4           24                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          345                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3051                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6862                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55068                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000366                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.997360                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 18937227                       # Number of tag accesses
+system.l2c.tags.data_accesses                18937227                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.dtb.walker        32950                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.itb.walker         7107                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.inst             506567                       # number of ReadReq hits
@@ -1517,6 +1532,13 @@
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.624663                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::cpu1.inst     0.374504                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999166                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          210                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          167                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses         12566622                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        12566622                       # Number of data accesses
 system.cpu0.icache.ReadReq_hits::cpu0.inst      5233615                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::cpu1.inst      5282125                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total       10515740                       # number of ReadReq hits
@@ -1644,6 +1666,13 @@
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.497473                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::cpu1.data     0.502514                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          300                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses        101674783                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       101674783                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data      6830201                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::cpu1.data      6949651                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total       13779852                       # number of ReadReq hits
@@ -2200,6 +2229,8 @@
 system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
+system.iocache.tags.data_accesses                   0                       # Number of data accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
index 927b487..6f15742 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini

@@ -12,7 +12,7 @@
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -23,12 +23,12 @@
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
 mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -75,7 +75,7 @@
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-arm-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -130,6 +130,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.dcache.tags
@@ -146,6 +147,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.dtb]
@@ -178,6 +180,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.icache.tags
@@ -194,6 +197,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.interrupts]
@@ -352,6 +356,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -368,6 +373,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.l2c]
@@ -385,6 +391,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.l2c.tags
@@ -401,6 +408,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.membus]

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
index e2fadf9..4dfb66c 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr

@@ -1,12 +1,10 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
-warn: DTB file specified, but no device tree support in kernel
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
 warn: The ccsidr register isn't implemented and always reads as 0.
-hack: be nice to actually delete the event here
 warn: 	instruction 'mcr bpiallis' unimplemented
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr dccimvac' unimplemented
@@ -33,3 +31,13 @@
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
index 6d8b916..25848b9 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout

@@ -1,10536 +1,8 @@
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:46:41
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 23 2014 00:31:08
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-info: Using bootloader at address 0x80000000
-info: Entering event queue @ 0.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1000000000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1000007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2000007500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2000015000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 3000015000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3000081000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 4000081000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4000151000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 5000151000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5000197000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 6000197000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 6000198000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 7000198000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 7000198500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 8000198500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 8000199000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 9000199000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 9000200000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 10000200000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 10000269500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 11000269500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 11000272000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 12000272000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 12000273000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 13000273000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 13000274000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 14000274000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 14000275000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 15000275000.  Starting simulation...
-info: Entering event queue @ 15000288500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 15000290000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 16000290000.  Starting simulation...
-info: Entering event queue @ 16000302500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 16000306000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 17000306000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 17000313500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 18000313500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 18000314500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 19000314500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 19000322000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 20000322000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 20000329500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 21000329500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 21000337000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 22000337000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 22000344500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 23000344500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 23000395000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 24000395000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 24000402500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 25000402500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 25000410000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 26000410000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 26000417500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 27000417500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 27000425000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 28000425000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 28000432500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 29000432500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 29000440000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 30000440000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 30000447500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 31000447500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 31000455000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 32000455000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 32000462500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 33000462500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 33000470000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 34000470000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 34000694000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 35000694000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 35000701500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 36000701500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 36000709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 37000709000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 37000716500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 38000716500.  Starting simulation...
-info: Entering event queue @ 38000736000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 38000832750.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 39000832750.  Starting simulation...
-switching cpus
-info: Entering event queue @ 39000840250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 40000840250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 40000847750.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 41000847750.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 42000847750.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 43000847750.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 44000847750.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 45000847750.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 46000847750.  Starting simulation...
-switching cpus
-info: Entering event queue @ 46000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 47000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 48000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 49000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 50000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 51000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 52000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 53000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 54000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 55000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 56000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 57000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 58000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 59000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 60000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 61000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 62000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 63000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 64000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 65000855250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 66000855250.  Starting simulation...
-info: Entering event queue @ 67631497250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 67631500000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 68631500000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 68631519500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 69631519500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 69631527000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 70631527000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 70631534500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 71631534500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 71631554500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 72631554500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 72631563500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 73631563500.  Starting simulation...
-info: Entering event queue @ 73631597500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 73631689750.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 74631689750.  Starting simulation...
-switching cpus
-info: Entering event queue @ 74631697250.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 75631697250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 75631727500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 76631727500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 76631736500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 77631736500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 77631744000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 78631744000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 78631751500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 79631751500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 79631773500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 80631773500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 80631802500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 81631802500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 81631810000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 82631810000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 82631817500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 83631817500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 83631834500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 84631834500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 84631842000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 85631842000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 85631849500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 86631849500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 86631857000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 87631857000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 87631864500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 88631864500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 88631872000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 89631872000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 89631879500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 90631879500.  Starting simulation...
-info: Entering event queue @ 90631913500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 90631921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 91631921000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 91631938500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 92631938500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 92631957500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 93631957500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 93631965000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 94631965000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 94631983500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 95631983500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 95632005500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 96632005500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 96632013000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 97632013000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 97632020500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 98632020500.  Starting simulation...
-info: Entering event queue @ 100364210250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 100364213000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 101364213000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 101364220500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 102364220500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 102364228000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 103364228000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 103364235500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 104364235500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 104364260500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 105364260500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 105364274500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 106364274500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 106364300500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 107364300500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 107364308000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 108364308000.  Starting simulation...
-info: Entering event queue @ 108364322500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 108364326000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 109364326000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 109364326500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 110364326500.  Starting simulation...
-info: Entering event queue @ 110364339000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 110364342500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 111364342500.  Starting simulation...
-info: Entering event queue @ 111364349500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 111364351000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 112364351000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 112364355500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 113364355500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 113364357000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 114364357000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 114364358000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 115364358000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 115364361500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 116364361500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 116364363000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 117364363000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 117364363500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 118364363500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 118364371000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 119364371000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 119364374000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 120364374000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 120364381500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 121364381500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 121364389000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 122364389000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 123364389000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 124364389000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 125364389000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 126364389000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 127364389000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 128364389000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 129364389000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 130364389000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 131364389000.  Starting simulation...
-info: Entering event queue @ 133099170250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 133099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 134099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 135099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 136099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 137099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 138099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 139099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 140099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 141099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 142099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 143099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 144099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 145099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 146099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 147099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 148099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 149099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 150099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 151099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 152099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 153099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 154099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 155099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 156099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 157099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 158099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 159099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 160099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 161099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 162099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 163099173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 164099173000.  Starting simulation...
-info: Entering event queue @ 165835457250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 165835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 166835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 167835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 168835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 169835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 170835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 171835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 172835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 173835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 174835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 175835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 176835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 177835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 178835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 179835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 180835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 181835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 182835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 183835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 184835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 185835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 186835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 187835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 188835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 189835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 190835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 191835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 192835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 193835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 194835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 195835460000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 196835460000.  Starting simulation...
-info: Entering event queue @ 198571738250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 198571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 199571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 200571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 201571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 202571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 203571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 204571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 205571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 206571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 207571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 208571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 209571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 210571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 211571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 212571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 213571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 214571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 215571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 216571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 217571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 218571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 219571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 220571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 221571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 222571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 223571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 224571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 225571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 226571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 227571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 228571741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 229571741000.  Starting simulation...
-info: Entering event queue @ 231307990250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 231307993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 232307993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 233307993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 234307993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 235307993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 236307993000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 236308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 237308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 238308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 239308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 240308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 241308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 242308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 243308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 244308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 245308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 246308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 247308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 248308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 249308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 250308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 251308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 252308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 253308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 254308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 255308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 256308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 257308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 258308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 259308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 260308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 261308000500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 262308000500.  Starting simulation...
-info: Entering event queue @ 264044274250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 264044277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 265044277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 266044277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 267044277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 268044277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 269044277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 270044277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 271044277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 272044277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 273044277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 274044277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 275044277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 276044277000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 276044278500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 277044278500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 277044286000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 278044286000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 278044293500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 279044293500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 279044301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 280044301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 281044301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 282044301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 283044301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 284044301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 285044301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 286044301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 287044301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 288044301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 289044301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 290044301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 291044301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 292044301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 293044301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 294044301000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 295044301000.  Starting simulation...
-info: Entering event queue @ 296780565250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 296780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 297780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 298780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 299780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 300780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 301780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 302780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 303780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 304780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 305780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 306780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 307780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 308780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 309780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 310780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 311780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 312780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 313780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 314780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 315780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 316780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 317780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 318780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 319780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 320780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 321780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 322780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 323780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 324780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 325780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 326780568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 327780568000.  Starting simulation...
-info: Entering event queue @ 329516810250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 329516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 330516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 331516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 332516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 333516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 334516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 335516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 336516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 337516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 338516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 339516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 340516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 341516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 342516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 343516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 344516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 345516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 346516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 347516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 348516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 349516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 350516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 351516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 352516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 353516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 354516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 355516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 356516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 357516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 358516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 359516813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 360516813000.  Starting simulation...
-info: Entering event queue @ 362253097250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 362253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 363253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 364253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 365253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 366253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 367253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 368253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 369253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 370253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 371253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 372253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 373253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 374253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 375253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 376253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 377253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 378253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 379253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 380253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 381253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 382253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 383253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 384253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 385253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 386253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 387253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 388253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 389253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 390253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 391253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 392253100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 393253100000.  Starting simulation...
-info: Entering event queue @ 394989382250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 394989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 395989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 396989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 397989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 398989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 399989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 400989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 401989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 402989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 403989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 404989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 405989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 406989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 407989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 408989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 409989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 410989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 411989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 412989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 413989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 414989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 415989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 416989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 417989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 418989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 419989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 420989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 421989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 422989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 423989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 424989385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 425989385000.  Starting simulation...
-info: Entering event queue @ 427725666250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 427725669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 428725669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 429725669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 430725669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 431725669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 432725669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 433725669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 434725669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 435725669000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 435725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 436725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 437725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 438725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 439725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 440725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 441725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 442725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 443725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 444725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 445725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 446725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 447725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 448725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 449725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 450725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 451725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 452725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 453725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 454725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 455725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 456725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 457725676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 458725676500.  Starting simulation...
-info: Entering event queue @ 460461918250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 460461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 461461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 462461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 463461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 464461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 465461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 466461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 467461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 468461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 469461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 470461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 471461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 472461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 473461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 474461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 475461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 476461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 477461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 478461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 479461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 480461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 481461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 482461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 483461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 484461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 485461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 486461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 487461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 488461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 489461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 490461921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 491461921000.  Starting simulation...
-info: Entering event queue @ 493198202250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 493198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 494198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 495198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 496198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 497198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 498198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 499198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 500198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 501198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 502198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 503198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 504198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 505198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 506198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 507198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 508198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 509198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 510198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 511198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 512198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 513198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 514198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 515198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 516198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 517198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 518198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 519198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 520198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 521198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 522198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 523198205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 524198205000.  Starting simulation...
-info: Entering event queue @ 525934134250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 525934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 526934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 527934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 528934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 529934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 530934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 531934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 532934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 533934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 534934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 535934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 536934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 537934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 538934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 539934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 540934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 541934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 542934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 543934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 544934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 545934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 546934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 547934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 548934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 549934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 550934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 551934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 552934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 553934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 554934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 555934137000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 556934137000.  Starting simulation...
-info: Entering event queue @ 558670734250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 558670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 559670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 560670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 561670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 562670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 563670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 564670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 565670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 566670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 567670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 568670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 569670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 570670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 571670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 572670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 573670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 574670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 575670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 576670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 577670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 578670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 579670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 580670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 581670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 582670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 583670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 584670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 585670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 586670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 587670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 588670737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 589670737000.  Starting simulation...
-info: Entering event queue @ 591406706250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 591406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 592406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 593406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 594406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 595406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 596406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 597406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 598406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 599406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 600406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 601406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 602406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 603406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 604406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 605406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 606406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 607406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 608406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 609406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 610406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 611406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 612406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 613406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 614406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 615406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 616406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 617406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 618406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 619406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 620406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 621406709000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 622406709000.  Starting simulation...
-info: Entering event queue @ 624142997250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 624143000000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 625143000000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 626143000000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 627143000000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 628143000000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 629143000000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 630143000000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 631143000000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 632143000000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 633143000000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 634143000000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 635143000000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 636143000000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 636143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 637143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 638143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 639143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 640143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 641143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 642143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 643143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 644143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 645143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 646143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 647143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 648143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 649143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 650143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 651143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 652143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 653143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 654143007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 655143007500.  Starting simulation...
-info: Entering event queue @ 656879241250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 656879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 657879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 658879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 659879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 660879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 661879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 662879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 663879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 664879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 665879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 666879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 667879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 668879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 669879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 670879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 671879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 672879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 673879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 674879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 675879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 676879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 677879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 678879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 679879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 680879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 681879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 682879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 683879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 684879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 685879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 686879244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 687879244000.  Starting simulation...
-info: Entering event queue @ 689615526250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 689615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 690615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 691615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 692615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 693615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 694615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 695615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 696615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 697615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 698615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 699615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 700615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 701615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 702615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 703615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 704615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 705615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 706615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 707615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 708615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 709615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 710615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 711615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 712615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 713615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 714615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 715615529000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 716615529000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 716615536500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 717615536500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 718615536500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 719615536500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 720615536500.  Starting simulation...
-info: Entering event queue @ 722351817250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 722351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 723351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 724351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 725351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 726351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 727351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 728351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 729351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 730351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 731351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 732351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 733351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 734351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 735351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 736351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 737351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 738351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 739351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 740351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 741351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 742351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 743351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 744351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 745351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 746351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 747351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 748351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 749351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 750351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 751351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 752351820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 753351820000.  Starting simulation...
-info: Entering event queue @ 755088065250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 755088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 756088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 757088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 758088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 759088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 760088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 761088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 762088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 763088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 764088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 765088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 766088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 767088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 768088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 769088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 770088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 771088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 772088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 773088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 774088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 775088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 776088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 777088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 778088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 779088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 780088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 781088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 782088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 783088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 784088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 785088068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 786088068000.  Starting simulation...
-info: Entering event queue @ 787824349250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 787824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 788824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 789824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 790824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 791824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 792824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 793824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 794824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 795824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 796824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 797824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 798824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 799824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 800824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 801824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 802824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 803824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 804824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 805824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 806824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 807824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 808824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 809824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 810824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 811824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 812824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 813824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 814824352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 815824352000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 815824359500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 816824359500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 817824359500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 818824359500.  Starting simulation...
-info: Entering event queue @ 820560634250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 820560637000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 821560637000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 822560637000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 823560637000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 824560637000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 825560637000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 826560637000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 827560637000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 828560637000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 829560637000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 830560637000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 831560637000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 832560637000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 833560637000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 834560637000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 835560637000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 836560637000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 836560644500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 837560644500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 838560644500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 839560644500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 840560644500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 841560644500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 842560644500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 843560644500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 844560644500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 845560644500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 846560644500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 847560644500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 848560644500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 849560644500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 850560644500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 851560644500.  Starting simulation...
-info: Entering event queue @ 853296882250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 853296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 854296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 855296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 856296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 857296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 858296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 859296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 860296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 861296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 862296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 863296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 864296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 865296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 866296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 867296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 868296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 869296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 870296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 871296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 872296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 873296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 874296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 875296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 876296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 877296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 878296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 879296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 880296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 881296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 882296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 883296885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 884296885000.  Starting simulation...
-info: Entering event queue @ 886033170250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 886033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 887033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 888033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 889033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 890033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 891033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 892033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 893033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 894033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 895033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 896033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 897033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 898033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 899033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 900033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 901033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 902033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 903033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 904033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 905033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 906033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 907033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 908033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 909033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 910033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 911033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 912033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 913033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 914033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 915033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 916033173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 917033173000.  Starting simulation...
-info: Entering event queue @ 918769454250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 918769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 919769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 920769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 921769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 922769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 923769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 924769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 925769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 926769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 927769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 928769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 929769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 930769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 931769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 932769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 933769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 934769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 935769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 936769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 937769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 938769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 939769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 940769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 941769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 942769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 943769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 944769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 945769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 946769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 947769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 948769457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 949769457000.  Starting simulation...
-info: Entering event queue @ 951505745250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 951505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 952505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 953505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 954505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 955505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 956505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 957505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 958505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 959505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 960505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 961505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 962505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 963505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 964505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 965505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 966505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 967505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 968505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 969505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 970505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 971505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 972505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 973505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 974505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 975505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 976505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 977505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 978505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 979505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 980505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 981505748000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 982505748000.  Starting simulation...
-info: Entering event queue @ 984241990250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 984241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 985241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 986241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 987241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 988241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 989241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 990241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 991241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 992241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 993241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 994241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 995241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 996241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 997241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 998241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 999241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1000241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1001241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1002241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1003241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1004241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1005241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1006241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1007241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1008241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1009241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1010241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1011241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1012241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1013241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1014241993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1015241993000.  Starting simulation...
-info: Entering event queue @ 1016978277250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1016978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1017978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1018978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1019978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1020978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1021978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1022978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1023978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1024978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1025978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1026978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1027978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1028978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1029978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1030978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1031978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1032978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1033978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1034978280000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1035978280000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1035978287500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1036978287500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1037978287500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1038978287500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1039978287500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1040978287500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1041978287500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1042978287500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1043978287500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1044978287500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1045978287500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1046978287500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1047978287500.  Starting simulation...
-info: Entering event queue @ 1049714558250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1049714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1050714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1051714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1052714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1053714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1054714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1055714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1056714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1057714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1058714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1059714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1060714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1061714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1062714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1063714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1064714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1065714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1066714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1067714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1068714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1069714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1070714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1071714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1072714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1073714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1074714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1075714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1076714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1077714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1078714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1079714561000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1080714561000.  Starting simulation...
-info: Entering event queue @ 1082450813250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1082450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1083450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1084450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1085450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1086450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1087450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1088450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1089450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1090450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1091450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1092450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1093450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1094450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1095450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1096450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1097450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1098450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1099450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1100450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1101450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1102450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1103450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1104450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1105450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1106450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1107450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1108450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1109450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1110450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1111450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1112450816000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1113450816000.  Starting simulation...
-info: Entering event queue @ 1115187098250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1115187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1116187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1117187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1118187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1119187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1120187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1121187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1122187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1123187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1124187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1125187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1126187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1127187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1128187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1129187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1130187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1131187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1132187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1133187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1134187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1135187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1136187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1137187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1138187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1139187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1140187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1141187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1142187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1143187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1144187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1145187101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1146187101000.  Starting simulation...
-info: Entering event queue @ 1147923385250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1147923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1148923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1149923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1150923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1151923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1152923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1153923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1154923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1155923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1156923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1157923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1158923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1159923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1160923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1161923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1162923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1163923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1164923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1165923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1166923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1167923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1168923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1169923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1170923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1171923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1172923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1173923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1174923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1175923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1176923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1177923388000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1178923388000.  Starting simulation...
-info: Entering event queue @ 1180659666250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1180659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1181659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1182659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1183659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1184659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1185659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1186659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1187659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1188659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1189659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1190659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1191659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1192659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1193659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1194659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1195659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1196659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1197659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1198659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1199659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1200659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1201659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1202659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1203659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1204659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1205659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1206659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1207659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1208659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1209659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1210659669000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1211659669000.  Starting simulation...
-info: Entering event queue @ 1213395918250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1213395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1214395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1215395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1216395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1217395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1218395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1219395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1220395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1221395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1222395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1223395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1224395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1225395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1226395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1227395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1228395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1229395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1230395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1231395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1232395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1233395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1234395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1235395921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1236395921000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1236395928500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1237395928500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1238395928500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1239395928500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1240395928500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1241395928500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1242395928500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1243395928500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1244395928500.  Starting simulation...
-info: Entering event queue @ 1246132202250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1246132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1247132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1248132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1249132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1250132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1251132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1252132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1253132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1254132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1255132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1256132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1257132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1258132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1259132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1260132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1261132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1262132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1263132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1264132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1265132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1266132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1267132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1268132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1269132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1270132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1271132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1272132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1273132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1274132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1275132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1276132205000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1277132205000.  Starting simulation...
-info: Entering event queue @ 1278868486250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1278868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1279868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1280868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1281868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1282868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1283868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1284868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1285868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1286868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1287868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1288868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1289868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1290868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1291868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1292868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1293868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1294868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1295868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1296868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1297868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1298868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1299868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1300868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1301868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1302868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1303868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1304868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1305868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1306868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1307868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1308868489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1309868489000.  Starting simulation...
-info: Entering event queue @ 1311604734250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1311604737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1312604737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1313604737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1314604737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1315604737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1316604737000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1316604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1317604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1318604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1319604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1320604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1321604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1322604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1323604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1324604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1325604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1326604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1327604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1328604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1329604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1330604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1331604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1332604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1333604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1334604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1335604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1336604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1337604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1338604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1339604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1340604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1341604744500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1342604744500.  Starting simulation...
-info: Entering event queue @ 1344341022250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1344341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1345341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1346341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1347341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1348341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1349341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1350341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1351341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1352341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1353341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1354341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1355341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1356341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1357341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1358341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1359341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1360341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1361341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1362341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1363341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1364341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1365341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1366341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1367341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1368341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1369341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1370341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1371341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1372341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1373341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1374341025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1375341025000.  Starting simulation...
-info: Entering event queue @ 1377076990250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1377076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1378076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1379076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1380076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1381076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1382076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1383076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1384076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1385076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1386076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1387076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1388076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1389076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1390076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1391076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1392076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1393076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1394076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1395076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1396076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1397076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1398076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1399076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1400076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1401076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1402076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1403076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1404076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1405076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1406076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1407076993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1408076993000.  Starting simulation...
-info: Entering event queue @ 1409813242250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1409813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1410813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1411813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1412813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1413813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1414813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1415813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1416813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1417813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1418813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1419813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1420813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1421813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1422813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1423813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1424813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1425813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1426813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1427813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1428813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1429813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1430813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1431813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1432813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1433813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1434813245000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1435813245000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1435813252500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1436813252500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1437813252500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1438813252500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1439813252500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1440813252500.  Starting simulation...
-info: Entering event queue @ 1442549529250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1442549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1443549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1444549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1445549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1446549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1447549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1448549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1449549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1450549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1451549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1452549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1453549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1454549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1455549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1456549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1457549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1458549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1459549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1460549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1461549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1462549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1463549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1464549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1465549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1466549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1467549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1468549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1469549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1470549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1471549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1472549532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1473549532000.  Starting simulation...
-info: Entering event queue @ 1475285817250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1475285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1476285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1477285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1478285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1479285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1480285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1481285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1482285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1483285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1484285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1485285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1486285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1487285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1488285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1489285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1490285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1491285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1492285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1493285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1494285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1495285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1496285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1497285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1498285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1499285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1500285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1501285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1502285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1503285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1504285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1505285820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1506285820000.  Starting simulation...
-info: Entering event queue @ 1508022065250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1508022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1509022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1510022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1511022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1512022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1513022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1514022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1515022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1516022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1517022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1518022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1519022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1520022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1521022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1522022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1523022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1524022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1525022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1526022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1527022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1528022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1529022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1530022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1531022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1532022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1533022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1534022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1535022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1536022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1537022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1538022068000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1539022068000.  Starting simulation...
-info: Entering event queue @ 1540758349250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1540758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1541758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1542758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1543758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1544758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1545758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1546758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1547758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1548758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1549758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1550758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1551758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1552758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1553758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1554758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1555758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1556758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1557758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1558758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1559758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1560758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1561758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1562758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1563758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1564758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1565758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1566758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1567758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1568758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1569758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1570758352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1571758352000.  Starting simulation...
-info: Entering event queue @ 1573494637250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1573494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1574494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1575494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1576494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1577494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1578494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1579494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1580494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1581494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1582494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1583494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1584494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1585494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1586494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1587494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1588494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1589494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1590494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1591494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1592494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1593494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1594494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1595494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1596494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1597494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1598494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1599494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1600494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1601494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1602494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1603494640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1604494640000.  Starting simulation...
-info: Entering event queue @ 1606230882250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1606230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1607230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1608230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1609230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1610230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1611230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1612230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1613230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1614230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1615230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1616230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1617230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1618230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1619230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1620230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1621230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1622230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1623230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1624230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1625230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1626230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1627230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1628230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1629230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1630230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1631230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1632230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1633230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1634230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1635230885000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1636230885000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1636230892500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1637230892500.  Starting simulation...
-info: Entering event queue @ 1638967170250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1638967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1639967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1640967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1641967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1642967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1643967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1644967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1645967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1646967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1647967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1648967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1649967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1650967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1651967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1652967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1653967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1654967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1655967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1656967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1657967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1658967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1659967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1660967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1661967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1662967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1663967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1664967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1665967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1666967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1667967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1668967173000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1669967173000.  Starting simulation...
-info: Entering event queue @ 1671703454250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1671703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1672703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1673703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1674703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1675703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1676703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1677703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1678703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1679703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1680703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1681703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1682703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1683703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1684703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1685703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1686703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1687703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1688703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1689703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1690703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1691703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1692703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1693703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1694703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1695703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1696703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1697703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1698703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1699703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1700703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1701703457000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1702703457000.  Starting simulation...
-info: Entering event queue @ 1704439738250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1704439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1705439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1706439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1707439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1708439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1709439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1710439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1711439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1712439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1713439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1714439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1715439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1716439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1717439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1718439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1719439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1720439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1721439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1722439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1723439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1724439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1725439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1726439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1727439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1728439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1729439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1730439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1731439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1732439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1733439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1734439741000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1735439741000.  Starting simulation...
-info: Entering event queue @ 1737175990250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1737175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1738175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1739175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1740175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1741175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1742175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1743175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1744175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1745175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1746175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1747175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1748175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1749175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1750175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1751175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1752175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1753175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1754175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1755175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1756175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1757175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1758175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1759175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1760175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1761175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1762175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1763175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1764175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1765175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1766175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1767175993000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1768175993000.  Starting simulation...
-info: Entering event queue @ 1769912274250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1769912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1770912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1771912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1772912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1773912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1774912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1775912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1776912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1777912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1778912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1779912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1780912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1781912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1782912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1783912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1784912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1785912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1786912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1787912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1788912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1789912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1790912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1791912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1792912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1793912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1794912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1795912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1796912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1797912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1798912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1799912277000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1800912277000.  Starting simulation...
-info: Entering event queue @ 1802648565250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1802648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1803648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1804648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1805648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1806648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1807648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1808648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1809648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1810648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1811648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1812648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1813648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1814648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1815648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1816648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1817648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1818648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1819648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1820648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1821648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1822648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1823648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1824648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1825648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1826648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1827648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1828648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1829648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1830648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1831648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1832648568000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1833648568000.  Starting simulation...
-info: Entering event queue @ 1835384810250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1835384813000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1836384813000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1836384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1837384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1838384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1839384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1840384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1841384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1842384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1843384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1844384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1845384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1846384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1847384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1848384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1849384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1850384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1851384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1852384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1853384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1854384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1855384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1856384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1857384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1858384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1859384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1860384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1861384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1862384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1863384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1864384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1865384820500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1866384820500.  Starting simulation...
-info: Entering event queue @ 1868121097250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1868121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1869121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1870121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1871121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1872121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1873121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1874121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1875121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1876121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1877121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1878121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1879121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1880121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1881121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1882121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1883121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1884121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1885121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1886121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1887121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1888121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1889121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1890121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1891121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1892121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1893121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1894121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1895121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1896121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1897121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1898121100000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1899121100000.  Starting simulation...
-info: Entering event queue @ 1900857382250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1900857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1901857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1902857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1903857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1904857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1905857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1906857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1907857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1908857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1909857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1910857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1911857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1912857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1913857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1914857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1915857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1916857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1917857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1918857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1919857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1920857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1921857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1922857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1923857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1924857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1925857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1926857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1927857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1928857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1929857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1930857385000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1931857385000.  Starting simulation...
-info: Entering event queue @ 1933593673250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1933593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1934593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1935593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1936593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1937593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1938593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1939593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1940593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1941593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1942593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1943593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1944593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1945593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1946593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1947593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1948593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1949593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1950593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1951593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1952593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1953593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1954593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1955593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1956593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1957593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1958593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1959593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1960593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1961593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1962593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1963593676000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1964593676000.  Starting simulation...
-info: Entering event queue @ 1966329918250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1966329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1967329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1968329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1969329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1970329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1971329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1972329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1973329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1974329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1975329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1976329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1977329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1978329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1979329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1980329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1981329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1982329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1983329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1984329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1985329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1986329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1987329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1988329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1989329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1990329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1991329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1992329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1993329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1994329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1995329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1996329921000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1997329921000.  Starting simulation...
-info: Entering event queue @ 1999066205250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1999066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2000066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2001066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2002066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2003066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2004066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2005066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2006066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2007066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2008066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2009066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2010066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2011066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2012066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2013066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2014066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2015066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2016066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2017066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2018066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2019066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2020066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2021066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2022066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2023066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2024066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2025066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2026066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2027066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2028066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2029066208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2030066208000.  Starting simulation...
-info: Entering event queue @ 2031802486250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2031802489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2032802489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2033802489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2034802489000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2035802489000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2035802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2036802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2037802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2038802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2039802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2040802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2041802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2042802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2043802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2044802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2045802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2046802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2047802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2048802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2049802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2050802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2051802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2052802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2053802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2054802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2055802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2056802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2057802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2058802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2059802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2060802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2061802496500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2062802496500.  Starting simulation...
-info: Entering event queue @ 2064538734250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2064538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2065538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2066538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2067538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2068538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2069538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2070538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2071538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2072538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2073538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2074538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2075538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2076538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2077538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2078538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2079538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2080538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2081538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2082538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2083538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2084538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2085538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2086538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2087538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2088538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2089538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2090538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2091538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2092538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2093538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2094538737000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2095538737000.  Starting simulation...
-info: Entering event queue @ 2097275022250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2097275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2098275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2099275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2100275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2101275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2102275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2103275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2104275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2105275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2106275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2107275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2108275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2109275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2110275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2111275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2112275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2113275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2114275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2115275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2116275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2117275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2118275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2119275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2120275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2121275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2122275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2123275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2124275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2125275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2126275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2127275025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2128275025000.  Starting simulation...
-info: Entering event queue @ 2130011306250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2130011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2131011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2132011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2133011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2134011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2135011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2136011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2137011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2138011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2139011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2140011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2141011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2142011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2143011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2144011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2145011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2146011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2147011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2148011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2149011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2150011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2151011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2152011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2153011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2154011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2155011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2156011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2157011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2158011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2159011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2160011309000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2161011309000.  Starting simulation...
-info: Entering event queue @ 2162747241250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2162747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2163747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2164747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2165747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2166747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2167747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2168747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2169747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2170747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2171747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2172747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2173747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2174747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2175747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2176747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2177747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2178747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2179747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2180747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2181747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2182747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2183747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2184747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2185747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2186747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2187747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2188747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2189747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2190747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2191747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2192747244000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2193747244000.  Starting simulation...
-info: Entering event queue @ 2195483842250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2195483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2196483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2197483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2198483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2199483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2200483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2201483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2202483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2203483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2204483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2205483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2206483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2207483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2208483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2209483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2210483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2211483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2212483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2213483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2214483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2215483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2216483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2217483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2218483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2219483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2220483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2221483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2222483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2223483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2224483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2225483845000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2226483845000.  Starting simulation...
-info: Entering event queue @ 2228219817250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2228219820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2229219820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2230219820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2231219820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2232219820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2233219820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2234219820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2235219820000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2236219820000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2236219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2237219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2238219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2239219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2240219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2241219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2242219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2243219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2244219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2245219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2246219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2247219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2248219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2249219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2250219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2251219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2252219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2253219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2254219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2255219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2256219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2257219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2258219827500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2259219827500.  Starting simulation...
-info: Entering event queue @ 2260956062250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2260956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2261956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2262956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2263956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2264956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2265956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2266956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2267956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2268956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2269956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2270956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2271956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2272956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2273956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2274956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2275956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2276956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2277956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2278956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2279956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2280956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2281956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2282956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2283956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2284956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2285956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2286956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2287956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2288956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2289956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2290956065000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2291956065000.  Starting simulation...
-info: Entering event queue @ 2293692349250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2293692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2294692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2295692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2296692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2297692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2298692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2299692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2300692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2301692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2302692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2303692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2304692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2305692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2306692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2307692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2308692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2309692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2310692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2311692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2312692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2313692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2314692352000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2315692352000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2315692410000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2316692410000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2316692443000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2317692443000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2317692450500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2318692450500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2319692450500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2320692450500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2321692450500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2322692450500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2323692450500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2324692450500.  Starting simulation...
-info: Entering event queue @ 2326428637250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2326428640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2327428640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2328428640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2329428640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2330428640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2331428640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2332428640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2333428640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2334428640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2335428640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2336428640000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2337428640000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2337428647500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2338428647500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2338428655000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2339428655000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2339428750000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2340428750000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2340428757500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2341428757500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2341428765000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2342428765000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2342428793000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2343428793000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2343428910000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2344428910000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2344428917500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2345428917500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2345429049000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2346429049000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2346429169000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2347429169000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2348429169000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2348429176500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2349429176500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2349429190000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2350429190000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2350429305000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2351429305000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2351429312500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2352429312500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2352429345000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2353429345000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2353429366000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2354429366000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2354429463000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2355429463000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2355429586000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2356429586000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2356429633000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2357429633000.  Starting simulation...
-info: Entering event queue @ 2359165549250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2359165552000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2360165552000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2360165559500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2361165559500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2361165567000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2362165567000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2362165602000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2363165602000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2363165722000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2364165722000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2364165818000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2365165818000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2365165956000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2366165956000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2366166000000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2367166000000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2367166007500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2368166007500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2368166148000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2369166148000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2369166232000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2370166232000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2370166258000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2371166258000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2371166376000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2372166376000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2372166411000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2373166411000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2373166428000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2374166428000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2374166455000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2375166455000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2375166576000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2376166576000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2376166696000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2377166696000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2377166781000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2378166781000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2378166854000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2379166854000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2379166934000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2380166934000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2380167067000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2381167067000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2381167110000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2382167110000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2382167211000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2383167211000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2383167257000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2384167257000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2384167406000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2385167406000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2385167550000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2386167550000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2386167557500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2387167557500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2387167694000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2388167694000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2388167701500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2389167701500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2389167857000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2390167857000.  Starting simulation...
-info: Entering event queue @ 2391903793250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2391903869000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2392903869000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2392903975000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2393903975000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2393903982500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2394903982500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2394903990000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2395903990000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2395904067000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2396904067000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2396904208000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2397904208000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2397904284000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2398904284000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2398904291500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2399904291500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2399904429000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2400904429000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2400904566000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2401904566000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2401904685000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2402904685000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2402904751000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2403904751000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2403904799000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2404904799000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2404904899000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2405904899000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2405905038000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2406905038000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2406905047000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2407905047000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2407905061000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2408905061000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2408905068500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2409905068500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2409905214000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2410905214000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2410905221500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2411905221500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2411905292000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2412905292000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2412905313000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2413905313000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2413905320500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2414905320500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2414905328000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2415905328000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2415905341000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2416905341000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2416905490000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2417905490000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2417905532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2418905532000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2418905539500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2419905539500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2419905643000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2420905643000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2420905687000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2421905687000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2421905694500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2422905694500.  Starting simulation...
-info: Entering event queue @ 2424637770250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2424637773000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2425637773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2425637788000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2426637788000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2426637903000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2427637903000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2428637903000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2428638049000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2429638049000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2429638099000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2430638099000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2430638106500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2431638106500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2431638195000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2432638195000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2432638349000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2433638349000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2433638486000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2434638486000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2434638493500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2435638493500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2435638590000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2436638590000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2436638614000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2437638614000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2437638621500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2438638621500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2438638710000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2439638710000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2439638725000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2440638725000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2440638747000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2441638747000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2441638754500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2442638754500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2442638803000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2443638803000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2443638912000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2444638912000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2444639034000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2445639034000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2445639125000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2446639125000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2446639160000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2447639160000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2447639271000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2448639271000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2448639278500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2449639278500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2449639286000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2450639286000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2450639415000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2451639415000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2451639552000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2452639552000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2452639559500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2453639559500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2453639643000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2454639643000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2454639650500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2455639650500.  Starting simulation...
-info: Entering event queue @ 2457374369250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2457374372000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2458374372000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2458374511000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2459374511000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2459374526000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2460374526000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2460374533500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2461374533500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2461374550000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2462374550000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2462374597000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2463374597000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2463374619000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2464374619000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2464374710000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2465374710000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2465374766000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2466374766000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2466374797000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2467374797000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2467374945000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2468374945000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2468374967000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2469374967000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2469375044000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2470375044000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2470375126000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2471375126000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2471375215000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2472375215000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2472375222500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2473375222500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2473375265000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2474375265000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2474375295000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2475375295000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2475375442000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2476375442000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2476375449500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2477375449500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2477375520000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2478375520000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2478375603000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2479375603000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2479375656000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2480375656000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2480375751000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2481375751000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2481375870000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2482375870000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2482375877500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2483375877500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2483375900000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2484375900000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2484375923000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2485375923000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2485376001000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2486376001000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2486376008500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2487376008500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2487376146000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2488376146000.  Starting simulation...
-info: Entering event queue @ 2490110657250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2490110660000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2491110660000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2491110682000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2492110682000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2492110689500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2493110689500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2493110765000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2494110765000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2494110772500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2495110772500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2495110780000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2496110780000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2496110878000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2497110878000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2497111028000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2498111028000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2498111170000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2499111170000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2499111184000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2500111184000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2500111332000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2501111332000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2501111339500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2502111339500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2502111354000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2503111354000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2503111446000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2504111446000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2504111532000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2505111532000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2505111539500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2506111539500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2506111646000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2507111646000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2507111682000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2508111682000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2508111689500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2509111689500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2509111831000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2510111831000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2510111941000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2511111941000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2511111948500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2512111948500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2512111990000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2513111990000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2513112001000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2514112001000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2514112009000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2515112009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2515112016500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2516112016500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2516112091000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2517112091000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2517112172000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2518112172000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2518112317000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2519112317000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2519112324500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2520112324500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2520112394000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2521112394000.  Starting simulation...
-info: Entering event queue @ 2522846938250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2522846941000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2523846941000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2523846948500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2524846948500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2524847092000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2525847092000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2525847224000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2526847224000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2526847351000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2527847351000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2527847362000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2528847362000.  Starting simulation...
-info: Entering event queue @ 2528847390000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2528847597000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2529847597000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2529847604500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2530847604500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2530847667000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2531847667000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2531847805000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2532847805000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2532847812500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2533847812500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2533847917000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2534847917000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2534847924500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2535847924500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2535847932000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2536847932000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2536847958000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2537847958000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2537847987000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2538847987000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2538848125000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2539848125000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2539848132500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2540848132500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2540848144000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2541848144000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2541848249000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2542848249000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2542848256500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2543848256500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2543848264000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2544848264000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2544848271500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2545848271500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2545848283000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2546848283000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2546848427000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2547848427000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2547848471000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2548848471000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2549848471000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2549848567000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2550848567000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2550848594000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2551848594000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2551848739000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2552848739000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2552848772000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2553848772000.  Starting simulation...
-info: Entering event queue @ 2555582877250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2555582880000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2556582880000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2556582963000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2557582963000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2557582970500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2558582970500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2558583082000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2559583082000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2559583164000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2560583164000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2560583171500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2561583171500.  Starting simulation...
-info: Entering event queue @ 2561583230000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2561583429750.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2562583429750.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2562583496000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2563583496000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2563583643000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2564583643000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2564583650500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2565583650500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2565583710000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2566583710000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2566583851000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2567583851000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2567584002000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2568584002000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2568584009500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2569584009500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2569584017000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2570584017000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2570584089000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2571584089000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2571584096500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2572584096500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2572584190000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2573584190000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2573584197500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2574584197500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2574584350000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2575584350000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2575584357500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2576584357500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2576584365000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2577584365000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2577584454000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2578584454000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2578584461500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2579584461500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2579584495000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2580584495000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2580584642000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2581584642000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2581584673000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2582584673000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2582584799000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2583584799000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2583584838000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2584584838000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2584584958000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2585584958000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2585585101000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2586585101000.  Starting simulation...
-info: Entering event queue @ 2588319477250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2588319480000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2589319480000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2589319487500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2590319487500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2590319506000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2591319506000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2591319513500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2592319513500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2592319521000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2593319521000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2593319528500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2594319528500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2594319578000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2595319578000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2595319585500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2596319585500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2596319687000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2597319687000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2597319740000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2598319740000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2598319767000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2599319767000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2599319774500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2600319774500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2600319782000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2601319782000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2601319789500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2602319789500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2602319797000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2603319797000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2603319799500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2604319799500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2604319800000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2605319800000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2605319807500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2606319807500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2606319815000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2607319815000.  Starting simulation...
-info: Entering event queue @ 2607319822500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2607319825500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2608319825500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2608319833000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2609319833000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2609319840500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2610319840500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2610319848000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2611319848000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2611319855500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2612319855500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2612319863000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2613319863000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2613319870500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2614319870500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2614319871000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2615319871000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2615319878500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2616319878500.  Starting simulation...
-info: Entering event queue @ 2616319886000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2616319887000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2617319887000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2617319894500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2618319894500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2618319896500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2619319896500.  Starting simulation...
-info: Entering event queue @ 2621055410250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2621055413000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2622055413000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2622055452000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2623055452000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2623055459500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2624055459500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2624055612000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2625055612000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2625055673000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2626055673000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2626055680500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2627055680500.  Starting simulation...
-info: Entering event queue @ 2627055945000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2627055952500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2628055952500.  Starting simulation...
-info: Entering event queue @ 2628055960000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2628055963000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2629055963000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2629055970500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2630055970500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2630055978000.  Starting simulation...

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
index 98143dc..e79723b 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt

@@ -4,25 +4,15 @@
 sim_ticks                                2629717216500                       # Number of ticks simulated
 final_tick                               2629717216500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 340896                       # Simulator instruction rate (inst/s)
-host_op_rate                                   433786                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            14888327014                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 445372                       # Number of bytes of host memory used
-host_seconds                                   176.63                       # Real time elapsed on the host
+host_inst_rate                                 592417                       # Simulator instruction rate (inst/s)
+host_op_rate                                   753843                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            25873243563                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 401372                       # Number of bytes of host memory used
+host_seconds                                   101.64                       # Real time elapsed on the host
 sim_insts                                    60212334                       # Number of instructions simulated
 sim_ops                                      76619433                       # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    124256256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.inst           298016                       # Number of bytes read from this memory
@@ -509,6 +499,18 @@
 system.physmem.avgGap                       159351.16                       # Average gap between requests
 system.physmem.pageHitRate                      99.43                       # Row buffer hit rate, read and write combined
 system.physmem.prechargeAllPercent               2.39                       # Percentage of time for which DRAM has all the banks in precharge state
+system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
 system.membus.throughput                     54426353                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq            16743636                       # Transaction distribution
 system.membus.trans_dist::ReadResp           16743636                       # Transaction distribution
@@ -553,6 +555,7 @@
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 system.membus.respLayer2.occupancy        35075577250                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                    62046                       # number of replacements
 system.l2c.tags.tagsinuse                51605.865819                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    1699437                       # Total number of references to valid blocks.
@@ -574,6 +577,15 @@
 system.l2c.tags.occ_percent::cpu1.inst       0.065179                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.049955                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.787443                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        65383                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2132                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6483                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        56716                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.997665                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 17277508                       # Number of tag accesses
+system.l2c.tags.data_accesses                17277508                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.dtb.walker         9827                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.itb.walker         3607                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.inst             412393                       # number of ReadReq hits
@@ -1124,6 +1136,14 @@
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.424303                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::cpu1.inst     0.573457                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.997760                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          266                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses         62363171                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        62363171                       # Number of data accesses
 system.cpu0.icache.ReadReq_hits::cpu0.inst     30192721                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::cpu1.inst     30456964                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total       60649685                       # number of ReadReq hits
@@ -1246,6 +1266,13 @@
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.360927                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::cpu1.data     0.638834                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999760                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          330                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          109                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         97784680                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        97784680                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data      6519451                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::cpu1.data      6679636                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total       13199087                       # number of ReadReq hits
@@ -1503,6 +1530,8 @@
 system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
+system.iocache.tags.data_accesses                   0                       # Number of data accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
index c331380..04fd84f 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini

@@ -20,7 +20,7 @@
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=timing
 mem_ranges=0:134217727
@@ -211,6 +211,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.dcache.tags
@@ -227,6 +228,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.dtb]
@@ -259,6 +261,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=1024
 system=system
 tags=system.cpu.dtb_walker_cache.tags
@@ -275,6 +278,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=1024
 
 [system.cpu.fuPool]
@@ -599,6 +603,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.icache.tags
@@ -615,6 +620,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.interrupts]
@@ -663,6 +669,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=1024
 system=system
 tags=system.cpu.itb_walker_cache.tags
@@ -679,6 +686,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=1024
 
 [system.cpu.l2cache]
@@ -696,6 +704,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.cpu.l2cache.tags
@@ -712,6 +721,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.cpu.toL2Bus]
@@ -1178,6 +1188,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -1194,6 +1205,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.membus]
@@ -1523,7 +1535,7 @@
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1546,7 +1558,7 @@
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
index 96081bf..0067e63 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr

@@ -1,4 +1,3 @@
-warn: add_child('terminal'): child 'terminal' already has parent
 warn: Sockets disabled, not accepting terminal connections
 warn: Reading current count from inactive timer.
 warn: Sockets disabled, not accepting gdb connections
@@ -10,4 +9,3 @@
 warn: Tried to clear PCI interrupt 14
 warn: Unknown mouse command 0xe1.
 warn: instruction 'wbinvd' unimplemented
-hack: be nice to actually delete the event here

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
index b43511d..4c2ae21 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout

@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:57:32
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 22:15:55
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5149801602000 because m5_exit instruction encountered
+Exiting @ tick 5133933067000 because m5_exit instruction encountered

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
index f9f231b..467207c 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                5133933067000                       # Number of ticks simulated
 final_tick                               5133933067000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 121984                       # Simulator instruction rate (inst/s)
-host_op_rate                                   241126                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1535878817                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 781700                       # Number of bytes of host memory used
-host_seconds                                  3342.67                       # Real time elapsed on the host
+host_inst_rate                                 186687                       # Simulator instruction rate (inst/s)
+host_op_rate                                   369023                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2350538489                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 736008                       # Number of bytes of host memory used
+host_seconds                                  2184.15                       # Real time elapsed on the host
 sim_insts                                   407751929                       # Number of instructions simulated
 sim_ops                                     806002693                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::pc.south_bridge.ide      2437184                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker         3904                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
@@ -473,6 +475,11 @@
 system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.103980                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006499                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.006499                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               428679                       # Number of tag accesses
+system.iocache.tags.data_accesses              428679                       # Number of data accesses
 system.iocache.ReadReq_misses::pc.south_bridge.ide          911                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              911                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
@@ -670,6 +677,7 @@
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer2.occupancy             1642000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                85602749                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          85602749                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            882967                       # Number of conditional branches incorrect
@@ -679,6 +687,7 @@
 system.cpu.branchPred.BTBHitPct             97.955165                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                 1444593                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect             180696                       # Number of incorrect RAS predictions.
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.numCycles                        453810576                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -986,6 +995,13 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   509.254964                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.994639                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.994639                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          215                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          196                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses           9447804                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses          9447804                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst      7477774                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total         7477774                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst       7477774                       # number of demand (read+write) hits
@@ -1070,6 +1086,13 @@
 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.004704                       # Average occupied blocks per requestor
 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.375294                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_percent::total     0.375294                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses        70243                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        70243                       # Number of data accesses
 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        20415                       # number of ReadReq hits
 system.cpu.itb_walker_cache.ReadReq_hits::total        20415                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
@@ -1154,6 +1177,13 @@
 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    14.842846                       # Average occupied blocks per requestor
 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.927678                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_percent::total     0.927678                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dtb_walker_cache.tags.tag_accesses       390650                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses       390650                       # Number of data accesses
 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        91726                       # number of ReadReq hits
 system.cpu.dtb_walker_cache.ReadReq_hits::total        91726                       # number of ReadReq hits
 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        91726                       # number of demand (read+write) hits
@@ -1234,6 +1264,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.997280                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999995                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999995                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          188                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          309                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          87846935                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         87846935                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     10898836                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        10898836                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      8096443                       # number of WriteReq hits
@@ -1362,6 +1399,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.045815                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.167251                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.989141                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        63963                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          514                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3380                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5452                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54576                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.975998                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         34635418                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        34635418                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        64096                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         7642                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.inst       942107                       # number of ReadReq hits

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini
index f745e2f..1b99afe 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini

@@ -20,7 +20,7 @@
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9.smp
 load_addr_mask=18446744073709551615
 mem_mode=timing
 mem_ranges=0:134217727
@@ -968,7 +968,7 @@
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -991,7 +991,7 @@
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr
index 4291cf7..9a873dc 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr

@@ -1,4 +1,3 @@
-warn: add_child('terminal'): child 'terminal' already has parent
 warn: Sockets disabled, not accepting terminal connections
 warn: Reading current count from inactive timer.
 warn: Sockets disabled, not accepting gdb connections
@@ -10,4 +9,3 @@
 hack: Assuming logical destinations are 1 << id.
 warn: Tried to clear PCI interrupt 14
 warn: Unknown mouse command 0xe1.
-hack: be nice to actually delete the event here

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout
index ada852a..f1f8b95 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout

@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:55:52
-gem5 started Oct 16 2013 01:57:05
-gem5 executing on zizzer
-command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
+gem5 compiled Jan 22 2014 17:16:50
+gem5 started Jan 22 2014 22:26:32
+gem5 executing on u200540-lin
+command line: build/X86_MESI_Two_Level/gem5.opt -d build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level -re tests/run.py build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9.smp
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5304492233500 because m5_exit instruction encountered
+Exiting @ tick 5300435735500 because m5_exit instruction encountered

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
index 4656948..a38bc5b 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                5300435735500                       # Number of ticks simulated
 final_tick                               5300435735500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 127150                       # Simulator instruction rate (inst/s)
-host_op_rate                                   243807                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6308537728                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 832728                       # Number of bytes of host memory used
-host_seconds                                   840.20                       # Real time elapsed on the host
+host_inst_rate                                 165870                       # Simulator instruction rate (inst/s)
+host_op_rate                                   318050                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             8229583651                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 786300                       # Number of bytes of host memory used
+host_seconds                                   644.07                       # Real time elapsed on the host
 sim_insts                                   106831806                       # Number of instructions simulated
 sim_ops                                     204847037                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::pc.south_bridge.ide        35184                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker       121960                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker        61480                       # Number of bytes read from this memory
@@ -364,6 +366,7 @@
 system.piobus.respLayer3.utilization              0.0                       # Layer utilization (%)
 system.piobus.respLayer4.occupancy             151500                       # Layer occupancy (ticks)
 system.piobus.respLayer4.utilization              0.0                       # Layer utilization (%)
+system.ruby.clk_domain.clock                      500                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                  2                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                  19                       # delay histogram for all message
 system.ruby.delayHist::samples               10855755                       # delay histogram for all message
@@ -489,6 +492,7 @@
 system.ruby.network.routers2.msg_bytes.Writeback_Data::0     41308992                      
 system.ruby.network.routers2.msg_bytes.Writeback_Data::1        21888                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::0      8867440                      
+system.ruby.memctrl_clk_domain.clock             1500                       # Clock period in ticks
 system.ruby.dir_cntrl0.memBuffer.memReq        317877                       # Total number of memory requests
 system.ruby.dir_cntrl0.memBuffer.memRead       175365                       # Number of memory reads
 system.ruby.dir_cntrl0.memBuffer.memWrite       142512                       # Number of memory writes
@@ -566,6 +570,8 @@
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
 system.cpu0.numCycles                     10600871471                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
@@ -592,6 +598,7 @@
 system.cpu0.idle_fraction                    0.951851                       # Percentage of idle cycles
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
+system.cpu1.apic_clk_domain.clock                8000                       # Clock period in ticks
 system.cpu1.numCycles                     10598039537                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
index 4079b1a..42cb407 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini

@@ -20,7 +20,7 @@
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=atomic
 mem_ranges=0:134217727
@@ -144,6 +144,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.dcache.tags
@@ -160,6 +161,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.dtb]
@@ -192,6 +194,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.icache.tags
@@ -208,6 +211,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.interrupts]
@@ -1205,6 +1209,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -1221,6 +1226,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.l2c]
@@ -1238,6 +1244,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.l2c.tags
@@ -1254,6 +1261,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.membus]
@@ -1583,7 +1591,7 @@
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1606,7 +1614,7 @@
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
index 99453da..246bb0f 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr

@@ -1,9 +1,7 @@
-warn: add_child('terminal'): child 'terminal' already has parent
 warn: Sockets disabled, not accepting terminal connections
 warn: Reading current count from inactive timer.
 warn: Sockets disabled, not accepting gdb connections
 warn: Don't know what interrupt to clear for console.
-hack: be nice to actually delete the event here
 warn: x86 cpuid: unknown family 0xbacc
 warn: x86 cpuid: unknown family 0x8086
 warn: x86 cpuid: unknown family 0x8086

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
index 38a9026..860a4f6 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout

@@ -1,17178 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:38:05
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 22:25:31
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
-info: Entering event queue @ 0.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1000000000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2000000000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2000001000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3000001000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3000009000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4000009000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 5000009000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5000098000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 6000098000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 6000272500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 7000272500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 8000272500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 8000346000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 9000346000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 9000506500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 10000506500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 11000506500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 11000580000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 12000580000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 12000740500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 13000740500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 14000740500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 14000814000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 15000814000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 15000974500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 16000974500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 17000974500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 17001048000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 18001048000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 18001208500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 19001208500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 20001208500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 20001282000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 21001282000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 21001442500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 22001442500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 23001442500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 23001516000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 24001516000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 24001676500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 25001676500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 26001676500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 26001750000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 27001750000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 27001910500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 28001910500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 29001910500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 29001984000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 30001984000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 30002144500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 31002144500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 32002144500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 32002218000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 33002218000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 33002378500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 34002378500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 35002378500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 35002452000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 36002452000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 36002612500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 37002612500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 38002612500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 38002686000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 39002686000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 39002846500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 40002846500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 41002846500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 41002920000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 42002920000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 42003080500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 43003080500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 44003080500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 44003154000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 45003154000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 45003314500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 46003314500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 47003314500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 47003388000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 48003388000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 48003548500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 49003548500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 50003548500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 50003622000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 51003622000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 51003782500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 52003782500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 53003782500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 53003856000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 54003856000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 54004016500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 55004016500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 55004017500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 56004017500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 56004018000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 57004018000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 57004209500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 58004209500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 58004210500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 59004210500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 59004211000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 60004211000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 60004215000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 61004215000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 61004215500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 62004215500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 62004216000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 63004216000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 63004220000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 64004220000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 64004221500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 65004221500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 65004222000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 66004222000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 66004232000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 67004232000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 67004232500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 68004232500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 68004233000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 69004233000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 69004237000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 70004237000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 70004238500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 71004238500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 71004239000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 72004239000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 72004243000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 73004243000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 73004244500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 74004244500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 74004245000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 75004245000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 75004255000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 76004255000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 76004256500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 77004256500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 77004257000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 78004257000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 78004267000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 79004267000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 79004267500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 80004267500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 80004268000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 81004268000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 81004272000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 82004272000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 82004273500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 83004273500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 83004274000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 84004274000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 84004278000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 85004278000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 86004278000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 86004278500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 87004278500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 87004288500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 88004288500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 88004289000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 89004289000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 89004289500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 90004289500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 90004299500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 91004299500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 91004300000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 92004300000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 92004300500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 93004300500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 93004304500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 94004304500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 94004305000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 95004305000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 95004305500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 96004305500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 96004309500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 97004309500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 98004309500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 98004317000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 99004317000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 99004389500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 100004389500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 100004391000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 101004391000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 101004424000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 102004424000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 102004467500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 103004467500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 103004469000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 104004469000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 104004502000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 105004502000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 105004545500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 106004545500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 106004547000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 107004547000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 107004580000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 108004580000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 108004623500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 109004623500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 109004625000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 110004625000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 110004658000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 111004658000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 111004701500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 112004701500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 112004703000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 113004703000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 113004736000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 114004736000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 114004779500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 115004779500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 115004781000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 116004781000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 116004814000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 117004814000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 117004857500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 118004857500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 118004859000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 119004859000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 119004892000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 120004892000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 120004935500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 121004935500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 121004937000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 122004937000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 122004970000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 123004970000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 123005013500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 124005013500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 124005015000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 125005015000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 125005048000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 126005048000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 126005091500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 127005091500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 127005093000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 128005093000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 128005126000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 129005126000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 129005169500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 130005169500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 130005171000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 131005171000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 131005204000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 132005204000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 132005247500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 133005247500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 133005249000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 134005249000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 134005282000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 135005282000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 135005325500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 136005325500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 136005327000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 137005327000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 137005360000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 138005360000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 138005403500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 139005403500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 139005405000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 140005405000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 140005438000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 141005438000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 141005481500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 142005481500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 142005483000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 143005483000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 143005516000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 144005516000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 144005559500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 145005559500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 145005561000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 146005561000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 146005594000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 147005594000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 147005637500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 148005637500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 149005637500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 149005645000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 150005645000.  Starting simulation...
-info: Entering event queue @ 150005938000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 150005945500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 151005945500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 152005945500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 152005953000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 153005953000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 155405582000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 156405582000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 157405582000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 157405589500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 158405589500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 159405533500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 160405533500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 161405533500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 162405533500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 163405402000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 164405402000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 165405402000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 166405402000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 167405277500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 168405277500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 169405277500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 170405277500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 171405149500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 172405149500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 173405149500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 174405149500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 175405018000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 176405018000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 177405018000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 178405018000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 179404893500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 180404893500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 181404893500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 181404901000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 182404901000.  Starting simulation...
-info: Entering event queue @ 183404700500.  Starting simulation...
-info: Entering event queue @ 183404701500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 183404706000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 184404706000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 185404706000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 186404706000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 187404637500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 188404637500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 189404637500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 190404637500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 191404509500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 192404509500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 193404509500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 193404517000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 194404517000.  Starting simulation...
-info: Entering event queue @ 194405024000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 194405031500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 195405031500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 195405033000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 196405033000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 196405040500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 197405040500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 197405066000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 198405066000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 199405066000.  Starting simulation...
-info: Entering event queue @ 199405333000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 199405340500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 200405340500.  Starting simulation...
-info: Entering event queue @ 200405348500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 200405353000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 201405353000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 202405353000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 202405360500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 203405360500.  Starting simulation...
-info: Entering event queue @ 203405368000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 203405369000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 204405369000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 205405369000.  Starting simulation...
-info: Entering event queue @ 205405378500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 205405382000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 206405382000.  Starting simulation...
-info: Entering event queue @ 206405420000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 206405427500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 207405427500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 208405427500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 208405435000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 209405435000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 209405451000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 210405451000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 210405452000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 211405452000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 211405462500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 212405462500.  Starting simulation...
-info: Entering event queue @ 212405472000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 212405473000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 213405473000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 213405473500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 214405473500.  Starting simulation...
-info: Entering event queue @ 214405524000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 214405643750.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 215405643750.  Starting simulation...
-info: Entering event queue @ 215405728500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 215406099750.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 216406099750.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 217406099750.  Starting simulation...
-switching cpus
-info: Entering event queue @ 217406107250.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 218406107250.  Starting simulation...
-info: Entering event queue @ 218406116500.  Starting simulation...
-info: Entering event queue @ 218406122500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 218406127000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 219406127000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 219406127500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 220406127500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 220406135000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 221406135000.  Starting simulation...
-info: Entering event queue @ 221406151500.  Starting simulation...
-info: Entering event queue @ 221406161000.  Starting simulation...
-info: Entering event queue @ 221406165500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 221406166500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 222406166500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 223406166500.  Starting simulation...
-info: Entering event queue @ 223406175000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 223406178500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 224406178500.  Starting simulation...
-info: Entering event queue @ 224406203500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 224406209000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 225406209000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 225406210000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 226406210000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 226406217500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 227406217500.  Starting simulation...
-info: Entering event queue @ 227406280000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 227406429750.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 228406429750.  Starting simulation...
-switching cpus
-info: Entering event queue @ 228406430000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 229406430000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 229406437500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 230406437500.  Starting simulation...
-info: Entering event queue @ 231403229000.  Starting simulation...
-info: Entering event queue @ 231403230000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 231403234500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 232403234500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 233403234500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 233403242000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 234403242000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 235403101500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 236403101500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 237403101500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 237403109000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 238403109000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 239402973500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 240402973500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 241402973500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 241402981000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 242402981000.  Starting simulation...
-info: Entering event queue @ 243402845000.  Starting simulation...
-info: Entering event queue @ 243402846000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 243402850500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 244402850500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 245402850500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 246402850500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 247402717500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 248402717500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 249402717500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 250402717500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 251402589500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 252402589500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 253402589500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 253402597000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 254402597000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 255402461500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 256402461500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 257402461500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 258402461500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 259402333500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 260402333500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 261402333500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 262402333500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 263402205500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 264402205500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 265402205500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 266402205500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 267402077500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 268402077500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 269402077500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 269402085000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 270402085000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 271401949500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 272401949500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 273401949500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 274401949500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 275401821500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 276401821500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 277401821500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 278401821500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 279401693500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 280401693500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 281401693500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 282401693500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 283401565500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 284401565500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 285401565500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 285401573000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 286401573000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 287401437500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 288401437500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 289401437500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 290401437500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 291401309500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 292401309500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 293401309500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 294401309500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 295401181500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 296401181500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 297401181500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 298401181500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 299401053500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 300401053500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 301401053500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 302401053500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 303400925500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 304400925500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 305400925500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 306400925500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 307400797500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 308400797500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 309400797500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 310400797500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 311400669500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 312400669500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 313400669500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 314400669500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 315400541500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 316400541500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 317400541500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 317400549000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 318400549000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 319400413500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 320400413500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 321400413500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 322400413500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 323400285500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 324400285500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 325400285500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 326400285500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 327400157500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 328400157500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 329400157500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 330400157500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 331400029500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 332400029500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 333400029500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 333400037000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 334400037000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 335399901500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 336399901500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 337399901500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 338399901500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 339399773500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 340399773500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 341399773500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 342399773500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 343399645500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 344399645500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 345399645500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 346399645500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 347399517500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 348399517500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 349399517500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 349399525000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 350399525000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 351399389500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 352399389500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 353399389500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 354399389500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 355399261500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 356399261500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 357399261500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 358399261500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 359399133500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 360399133500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 361399133500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 362399133500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 363399005500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 364399005500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 365399005500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 366399005500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 367398877500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 368398877500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 369398877500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 370398877500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 371398749500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 372398749500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 373398749500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 374398749500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 375398621500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 376398621500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 377398621500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 378398621500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 379398493500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 380398493500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 381398493500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 382398493500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 383398365500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 384398365500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 385398365500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 386398365500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 387398237500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 388398237500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 389398237500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 390398237500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 391398109500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 392398109500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 393398109500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 394398109500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 395397981500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 396397981500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 397397981500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 398397981500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 399397853500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 400397853500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 401397853500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 402397853500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 403397725500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 404397725500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 405397725500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 406397725500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 407397597500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 408397597500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 409397597500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 410397597500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 411397469500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 412397469500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 413397469500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 413397477000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 414397477000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 415397341500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 416397341500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 417397341500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 418397341500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 419397213500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 420397213500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 421397213500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 422397213500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 423397085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 424397085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 425397085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 426397085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 427396957500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 428396957500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 429396957500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 429396965000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 430396965000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 431396829500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 432396829500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 433396829500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 434396829500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 435396701500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 436396701500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 437396701500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 438396701500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 439396573500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 440396573500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 441396573500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 442396573500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 443396445500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 444396445500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 445396445500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 445396453000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 446396453000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 447396317500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 448396317500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 449396317500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 450396317500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 451396189500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 452396189500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 453396189500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 454396189500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 455396061500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 456396061500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 457396061500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 458396061500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 459395933500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 460395933500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 461395933500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 461395941000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 462395941000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 463395805500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 464395805500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 465395805500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 466395805500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 467395677500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 468395677500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 469395677500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 470395677500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 471395549500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 472395549500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 473395549500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 474395549500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 475395421500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 476395421500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 477395421500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 477395429000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 478395429000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 479395293500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 480395293500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 481395293500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 482395293500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 483395165500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 484395165500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 485395165500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 486395165500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 487395037500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 488395037500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 489395037500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 490395037500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 491394909500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 492394909500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 493394909500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 493394917000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 494394917000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 495394781500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 496394781500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 497394781500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 498394781500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 499394653500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 500394653500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 501394653500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 502394653500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 503394525500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 504394525500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 505394525500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 506394525500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 507394397500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 508394397500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 509394397500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 509394405000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 510394405000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 511394269500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 512394269500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 513394269500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 514394269500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 515394141500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 516394141500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 517394141500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 518394141500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 519394013500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 520394013500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 521394013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 522394013500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 523393885500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 524393885500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 525393885500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 525393893000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 526393893000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 527393757500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 528393757500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 529393757500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 530393757500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 531393629500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 532393629500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 533393629500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 534393629500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 535393501500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 536393501500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 537393501500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 538393501500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 539393373500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 540393373500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 541393373500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 541393381000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 542393381000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 543393245500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 544393245500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 545393245500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 546393245500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 547393117500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 548393117500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 549393117500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 550393117500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 551392989500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 552392989500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 553392989500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 554392989500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 555392861500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 556392861500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 557392861500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 557392869000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 558392869000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 559392733500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 560392733500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 561392733500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 562392733500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 563392605500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 564392605500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 565392605500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 566392605500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 567392477500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 568392477500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 569392477500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 570392477500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 571392349500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 572392349500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 573392349500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 573392357000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 574392357000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 575392221500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 576392221500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 577392221500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 578392221500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 579392093500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 580392093500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 581392093500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 582392093500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 583391965500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 584391965500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 585391965500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 586391965500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 587391837500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 588391837500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 589391837500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 589391845000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 590391845000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 591391709500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 592391709500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 593391709500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 594391709500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 595391581500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 596391581500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 597391581500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 598391581500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 599391453500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 600391453500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 601391453500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 602391453500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 603391325500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 604391325500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 605391325500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 605391333000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 606391333000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 607391197500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 608391197500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 609391197500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 610391197500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 611391069500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 612391069500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 613391069500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 614391069500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 615390941500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 616390941500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 617390941500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 618390941500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 619390813500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 620390813500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 621390813500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 621390821000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 622390821000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 623390685500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 624390685500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 625390685500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 626390685500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 627390557500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 628390557500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 629390557500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 630390557500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 631390429500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 632390429500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 633390429500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 634390429500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 635390301500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 636390301500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 637390301500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 637390309000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 638390309000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 639390173500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 640390173500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 641390173500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 642390173500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 643390045500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 644390045500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 645390045500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 646390045500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 647389917500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 648389917500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 649389917500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 650389917500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 651389789500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 652389789500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 653389789500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 653389797000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 654389797000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 655389661500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 656389661500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 657389661500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 658389661500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 659389533500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 660389533500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 661389533500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 662389533500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 663389405500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 664389405500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 665389405500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 666389405500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 667389277500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 668389277500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 669389277500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 669389285000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 670389285000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 671389149500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 672389149500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 673389149500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 674389149500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 675389021500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 676389021500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 677389021500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 678389021500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 679388893500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 680388893500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 681388893500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 682388893500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 683388765500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 684388765500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 685388765500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 685388773000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 686388773000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 687388637500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 688388637500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 689388637500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 690388637500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 691388509500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 692388509500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 693388509500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 694388509500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 695388381500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 696388381500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 697388381500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 698388381500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 699388253500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 700388253500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 701388253500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 701388261000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 702388261000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 703388125500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 704388125500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 705388125500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 706388125500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 707387997500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 708387997500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 709387997500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 710387997500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 711387869500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 712387869500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 713387869500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 714387869500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 715387741500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 716387741500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 717387741500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 717387749000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 718387749000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 719387613500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 720387613500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 721387613500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 722387613500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 723387485500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 724387485500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 725387485500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 726387485500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 727387357500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 728387357500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 729387357500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 730387357500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 731387229500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 732387229500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 733387229500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 733387237000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 734387237000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 735387101500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 736387101500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 737387101500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 738387101500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 739386973500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 740386973500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 741386973500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 742386973500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 743386845500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 744386845500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 745386845500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 746386845500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 747386717500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 748386717500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 749386717500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 749386725000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 750386725000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 751386589500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 752386589500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 753386589500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 754386589500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 755386461500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 756386461500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 757386461500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 758386461500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 759386333500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 760386333500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 761386333500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 762386333500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 763386205500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 764386205500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 765386205500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 765386213000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 766386213000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 767386077500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 768386077500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 769386077500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 770386077500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 771385949500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 772385949500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 773385949500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 774385949500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 775385821500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 776385821500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 777385821500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 778385821500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 779385693500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 780385693500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 781385693500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 781385701000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 782385701000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 783385565500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 784385565500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 785385565500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 786385565500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 787385437500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 788385437500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 789385437500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 790385437500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 791385309500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 792385309500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 793385309500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 794385309500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 795385181500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 796385181500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 797385181500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 797385189000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 798385189000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 799385053500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 800385053500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 801385053500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 802385053500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 803384925500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 804384925500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 805384925500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 806384925500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 807384797500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 808384797500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 809384797500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 810384797500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 811384669500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 812384669500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 813384669500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 814384669500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 815384541500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 816384541500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 817384541500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 818384541500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 819384413500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 820384413500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 821384413500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 822384413500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 823384285500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 824384285500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 825384285500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 826384285500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 827384157500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 828384157500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 829384157500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 830384157500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 831384029500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 832384029500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 833384029500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 834384029500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 835383901500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 836383901500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 837383901500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 838383901500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 839383773500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 840383773500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 841383773500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 842383773500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 843383645500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 844383645500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 845383645500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 845383653000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 846383653000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 847383517500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 848383517500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 849383517500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 850383517500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 851383389500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 852383389500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 853383389500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 854383389500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 855383261500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 856383261500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 857383261500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 858383261500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 859383133500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 860383133500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 861383133500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 861383141000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 862383141000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 863383005500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 864383005500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 865383005500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 866383005500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 867382877500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 868382877500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 869382877500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 870382877500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 871382749500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 872382749500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 873382749500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 874382749500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 875382621500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 876382621500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 877382621500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 877382629000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 878382629000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 879382493500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 880382493500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 881382493500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 882382493500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 883382365500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 884382365500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 885382365500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 886382365500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 887382237500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 888382237500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 889382237500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 890382237500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 891382109500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 892382109500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 893382109500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 893382117000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 894382117000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 895381981500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 896381981500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 897381981500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 898381981500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 899381853500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 900381853500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 901381853500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 902381853500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 903381725500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 904381725500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 905381725500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 906381725500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 907381597500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 908381597500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 909381597500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 909381605000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 910381605000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 911381469500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 912381469500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 913381469500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 914381469500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 915381341500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 916381341500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 917381341500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 918381341500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 919381213500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 920381213500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 921381213500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 922381213500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 923381085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 924381085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 925381085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 925381093000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 926381093000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 927380957500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 928380957500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 929380957500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 930380957500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 931380829500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 932380829500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 933380829500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 934380829500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 935380701500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 936380701500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 937380701500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 938380701500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 939380573500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 940380573500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 941380573500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 941380581000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 942380581000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 943380445500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 944380445500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 945380445500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 946380445500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 947380317500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 948380317500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 949380317500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 950380317500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 951380189500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 952380189500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 953380189500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 954380189500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 955380061500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 956380061500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 957380061500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 957380069000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 958380069000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 959379933500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 960379933500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 961379933500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 962379933500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 963379805500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 964379805500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 965379805500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 966379805500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 967379677500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 968379677500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 969379677500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 970379677500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 971379549500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 972379549500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 973379549500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 973379557000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 974379557000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 975379421500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 976379421500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 977379421500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 978379421500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 979379293500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 980379293500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 981379293500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 982379293500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 983379165500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 984379165500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 985379165500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 986379165500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 987379037500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 988379037500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 989379037500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 989379045000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 990379045000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 991378909500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 992378909500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 993378909500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 994378909500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 995378781500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 996378781500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 997378781500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 998378781500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 999378653500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1000378653500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1001378653500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1002378653500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1003378525500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1004378525500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1005378525500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1005378533000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1006378533000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1007378397500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1008378397500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1009378397500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1010378397500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1011378269500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1012378269500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1013378269500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1014378269500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1015378141500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1016378141500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1017378141500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1018378141500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1019378013500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1020378013500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1021378013500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1021378021000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1022378021000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1023377885500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1024377885500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1025377885500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1026377885500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1027377757500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1028377757500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1029377757500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1030377757500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1031377629500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1032377629500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1033377629500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1034377629500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1035377501500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1036377501500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1037377501500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1037377509000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1038377509000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1039377373500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1040377373500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1041377373500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1042377373500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1043377245500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1044377245500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1045377245500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1046377245500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1047377117500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1048377117500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1049377117500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1050377117500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1051376989500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1052376989500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1053376989500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1053376997000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1054376997000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1055376861500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1056376861500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1057376861500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1058376861500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1059376733500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1060376733500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1061376733500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1062376733500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1063376605500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1064376605500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1065376605500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1066376605500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1067376477500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1068376477500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1069376477500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1069376485000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1070376485000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1071376349500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1072376349500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1073376349500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1074376349500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1075376221500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1076376221500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1077376221500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1078376221500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1079376093500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1080376093500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1081376093500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1082376093500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1083375965500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1084375965500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1085375965500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1085375973000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1086375973000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1087375837500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1088375837500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1089375837500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1089375845000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1090375845000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1091375709500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1092375709500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1093375709500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1094375709500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1095375581500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1096375581500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1097375581500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1098375581500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1099375453500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1100375453500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1101375453500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1101375461000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1102375461000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1103375325500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1104375325500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1105375325500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1106375325500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1107375197500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1108375197500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1109375197500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1110375197500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1111375069500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1112375069500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1113375069500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1114375069500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1115374941500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1116374941500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1117374941500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1117374949000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1118374949000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1119374813500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1120374813500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1121374813500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1122374813500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1123374685500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1124374685500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1125374685500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1126374685500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1127374557500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1128374557500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1129374557500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1130374557500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1131374429500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1132374429500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1133374429500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1133374437000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1134374437000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1135374301500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1136374301500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1137374301500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1138374301500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1139374173500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1140374173500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1141374173500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1142374173500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1143374045500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1144374045500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1145374045500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1146374045500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1147373917500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1148373917500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1149373917500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1149373925000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1150373925000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1151373789500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1152373789500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1153373789500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1154373789500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1155373661500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1156373661500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1157373661500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1158373661500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1159373533500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1160373533500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1161373533500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1162373533500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1163373405500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1164373405500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1165373405500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1165373413000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1166373413000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1167373277500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1168373277500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1169373277500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1170373277500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1171373149500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1172373149500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1173373149500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1174373149500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1175373021500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1176373021500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1177373021500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1178373021500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1179372893500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1180372893500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1181372893500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1181372901000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1182372901000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1183372765500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1184372765500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1185372765500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1186372765500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1187372637500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1188372637500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1189372637500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1190372637500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1191372509500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1192372509500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1193372509500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1194372509500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1195372381500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1196372381500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1197372381500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1197372389000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1198372389000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1199372253500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1200372253500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1201372253500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1202372253500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1203372125500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1204372125500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1205372125500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1206372125500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1207371997500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1208371997500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1209371997500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1210371997500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1211371869500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1212371869500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1213371869500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1213371877000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1214371877000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1215371741500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1216371741500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1217371741500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1218371741500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1219371613500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1220371613500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1221371613500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1222371613500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1223371485500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1224371485500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1225371485500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1226371485500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1227371357500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1228371357500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1229371357500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1230371357500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1231371229500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1232371229500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1233371229500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1234371229500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1235371101500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1236371101500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1237371101500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1238371101500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1239370973500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1240370973500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1241370973500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1242370973500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1243370845500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1244370845500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1245370845500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1246370845500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1247370717500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1248370717500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1249370717500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1250370717500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1251370589500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1252370589500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1253370589500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1254370589500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1255370461500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1256370461500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1257370461500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1258370461500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1259370333500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1260370333500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1261370333500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1262370333500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1263370205500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1264370205500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1265370205500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1266370205500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1267370077500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1268370077500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1269370077500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1270370077500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1271369949500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1272369949500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1273369949500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1274369949500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1275369821500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1276369821500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1277369821500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1278369821500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1279369693500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1280369693500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1281369693500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1282369693500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1283369565500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1284369565500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1285369565500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1286369565500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1287369437500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1288369437500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1289369437500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1290369437500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1291369309500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1292369309500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1293369309500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1294369309500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1295369181500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1296369181500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1297369181500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1298369181500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1299369053500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1300369053500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1301369053500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1302369053500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1303368925500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1304368925500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1305368925500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1306368925500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1307368797500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1308368797500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1309368797500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1310368797500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1311368669500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1312368669500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1313368669500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1314368669500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1315368541500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1316368541500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1317368541500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1318368541500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1319368413500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1320368413500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1321368413500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1322368413500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1323368285500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1324368285500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1325368285500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1326368285500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1327368157500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1328368157500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1329368157500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1330368157500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1331368029500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1332368029500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1333368029500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1334368029500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1335367901500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1336367901500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1337367901500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1338367901500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1339367773500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1340367773500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1341367773500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1342367773500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1343367645500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1344367645500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1345367645500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1346367645500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1347367517500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1348367517500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1349367517500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1350367517500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1351367389500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1352367389500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1353367389500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1354367389500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1355367261500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1356367261500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1357367261500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1358367261500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1359367133500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1360367133500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1361367133500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1362367133500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1363367005500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1364367005500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1365367005500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1366367005500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1367366877500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1368366877500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1369366877500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1370366877500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1371366749500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1372366749500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1373366749500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1374366749500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1375366621500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1376366621500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1377366621500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1378366621500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1379366493500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1380366493500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1381366493500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1382366493500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1383366365500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1384366365500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1385366365500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1386366365500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1387366237500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1388366237500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1389366237500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1390366237500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1391366109500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1392366109500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1393366109500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1394366109500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1395365981500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1396365981500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1397365981500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1398365981500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1399365853500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1400365853500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1401365853500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1402365853500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1403365725500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1404365725500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1405365725500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1406365725500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1407365597500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1408365597500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1409365597500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1410365597500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1411365469500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1412365469500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1413365469500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1414365469500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1415365341500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1416365341500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1417365341500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1418365341500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1419365213500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1420365213500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1421365213500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1422365213500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1423365085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1424365085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1425365085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1426365085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1427364957500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1428364957500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1429364957500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1430364957500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1431364829500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1432364829500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1433364829500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1434364829500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1435364701500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1436364701500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1437364701500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1438364701500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1439364573500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1440364573500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1441364573500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1442364573500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1443364445500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1444364445500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1445364445500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1446364445500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1447364317500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1448364317500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1449364317500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1450364317500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1451364189500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1452364189500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1453364189500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1454364189500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1455364061500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1456364061500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1457364061500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1458364061500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1459363933500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1460363933500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1461363933500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1462363933500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1463363805500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1464363805500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1465363805500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1466363805500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1467363677500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1468363677500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1469363677500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1470363677500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1471363549500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1472363549500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1473363549500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1474363549500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1475363421500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1476363421500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1477363421500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1478363421500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1479363293500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1480363293500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1481363293500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1482363293500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1483363165500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1484363165500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1485363165500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1486363165500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1487363037500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1488363037500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1489363037500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1490363037500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1491362909500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1492362909500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1493362909500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1494362909500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1495362781500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1496362781500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1497362781500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1498362781500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1499362653500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1500362653500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1501362653500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1502362653500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1503362525500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1504362525500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1505362525500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1506362525500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1507362397500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1508362397500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1509362397500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1510362397500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1511362269500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1512362269500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1513362269500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1514362269500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1515362141500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1516362141500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1517362141500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1518362141500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1519362013500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1520362013500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1521362013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1522362013500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1523361885500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1524361885500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1525361885500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1526361885500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1527361757500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1528361757500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1529361757500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1530361757500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1531361629500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1532361629500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1533361629500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1534361629500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1535361501500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1536361501500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1537361501500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1538361501500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1539361373500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1540361373500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1541361373500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1542361373500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1543361245500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1544361245500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1545361245500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1546361245500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1547361117500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1548361117500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1549361117500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1550361117500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1551360989500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1552360989500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1553360989500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1554360989500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1555360861500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1556360861500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1557360861500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1558360861500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1559360733500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1560360733500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1561360733500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1562360733500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1563360605500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1564360605500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1565360605500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1566360605500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1567360477500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1568360477500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1569360477500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1570360477500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1571360349500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1572360349500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1573360349500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1574360349500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1575360221500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1576360221500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1577360221500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1578360221500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1579360093500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1580360093500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1581360093500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1582360093500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1583359965500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1584359965500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1585359965500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1586359965500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1587359837500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1588359837500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1589359837500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1590359837500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1591359709500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1592359709500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1593359709500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1594359709500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1595359581500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1596359581500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1597359581500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1598359581500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1599359453500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1600359453500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1601359453500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1602359453500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1603359325500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1604359325500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1605359325500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1606359325500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1607359197500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1608359197500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1609359197500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1610359197500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1611359069500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1612359069500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1613359069500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1614359069500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1615358941500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1616358941500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1617358941500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1618358941500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1619358813500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1620358813500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1621358813500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1622358813500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1623358685500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1624358685500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1625358685500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1626358685500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1627358557500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1628358557500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1629358557500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1630358557500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1631358429500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1632358429500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1633358429500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1634358429500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1635358301500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1636358301500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1637358301500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1638358301500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1639358173500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1640358173500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1641358173500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1642358173500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1643358045500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1644358045500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1645358045500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1646358045500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1647357917500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1648357917500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1649357917500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1650357917500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1651357789500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1652357789500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1653357789500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1654357789500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1655357661500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1656357661500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1657357661500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1658357661500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1659357533500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1660357533500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1661357533500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1662357533500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1663357405500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1664357405500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1665357405500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1666357405500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1667357277500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1668357277500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1669357277500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1670357277500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1671357149500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1672357149500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1673357149500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1674357149500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1675357021500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1676357021500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1677357021500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1678357021500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1679356893500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1680356893500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1681356893500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1682356893500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1683356765500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1684356765500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1685356765500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1686356765500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1687356637500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1688356637500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1689356637500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1690356637500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1691356509500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1692356509500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1693356509500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1694356509500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1695356381500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1696356381500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1697356381500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1698356381500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1699356253500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1700356253500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1701356253500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1702356253500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1703356125500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1704356125500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1705356125500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1706356125500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1707355997500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1708355997500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1709355997500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1710355997500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1711355869500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1712355869500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1713355869500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1714355869500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1715355741500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1716355741500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1717355741500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1718355741500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1719355613500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1720355613500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1721355613500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1722355613500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1723355485500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1724355485500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1725355485500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1726355485500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1727355357500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1728355357500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1729355357500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1730355357500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1731355229500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1732355229500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1733355229500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1734355229500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1735355101500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1736355101500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1737355101500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1738355101500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1739354973500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1740354973500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1741354973500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1742354973500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1743354845500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1744354845500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1745354845500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1746354845500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1747354717500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1748354717500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1749354717500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1750354717500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1751354589500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1752354589500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1753354589500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1754354589500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1755354461500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1756354461500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1757354461500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1758354461500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1759354333500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1760354333500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1761354333500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1762354333500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1763354205500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1764354205500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1765354205500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1766354205500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1767354077500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1768354077500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1769354077500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1770354077500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1771353949500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1772353949500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1773353949500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1774353949500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1775353821500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1776353821500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1777353821500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1778353821500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1779353693500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1780353693500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1781353693500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1782353693500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1783353565500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1784353565500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1785353565500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1786353565500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1787353437500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1788353437500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1789353437500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1790353437500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1791353309500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1792353309500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1793353309500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1794353309500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1795353181500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1796353181500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1797353181500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1798353181500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1799353053500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1800353053500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1801353053500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1802353053500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1803352925500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1804352925500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1805352925500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1806352925500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1807352797500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1808352797500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1809352797500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1810352797500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1811352669500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1812352669500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1813352669500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1814352669500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1815352541500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1816352541500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1817352541500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1818352541500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1819352413500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1820352413500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1821352413500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1822352413500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1823352285500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1824352285500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1825352285500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1826352285500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1827352157500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1828352157500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1829352157500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1830352157500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1831352029500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1832352029500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1833352029500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1834352029500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1835351901500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1836351901500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1837351901500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1838351901500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1839351773500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1840351773500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1841351773500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1842351773500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1843351645500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1844351645500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1845351645500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1846351645500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1847351517500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1848351517500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1849351517500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1850351517500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1851351389500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1852351389500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1853351389500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1854351389500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1855351261500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1856351261500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1857351261500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1858351261500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1859351133500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1860351133500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1861351133500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1862351133500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1863351005500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1864351005500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1865351005500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1866351005500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1867350877500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1868350877500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1869350877500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1870350877500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1871350749500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1872350749500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1873350749500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1874350749500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1875350621500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1876350621500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1877350621500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1878350621500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1879350493500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1880350493500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1881350493500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1882350493500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1883350365500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1884350365500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1885350365500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1886350365500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1887350237500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1888350237500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1889350237500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1890350237500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1891350109500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1892350109500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1893350109500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1894350109500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1895349981500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1896349981500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1897349981500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1898349981500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1899349853500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1900349853500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1901349853500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1902349853500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1903349725500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1904349725500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1905349725500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1906349725500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1907349597500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1908349597500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1909349597500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1910349597500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1911349469500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1912349469500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 1913349469500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1913349477000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1914349477000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1915349341500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1916349341500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1917349341500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1918349341500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1919349213500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1920349213500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1921349213500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1922349213500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1923349085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1924349085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1925349085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1926349085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1927348957500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1928348957500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1929348957500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1930348957500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1931348829500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1932348829500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1933348829500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1934348829500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1935348701500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1936348701500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1937348701500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1938348701500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1939348573500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1940348573500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1941348573500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1942348573500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1943348445500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1944348445500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1945348445500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1946348445500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1947348317500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1948348317500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1949348317500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1950348317500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1951348189500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1952348189500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1953348189500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1954348189500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1955348061500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1956348061500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1957348061500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1958348061500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1959347933500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1960347933500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1961347933500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1962347933500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1963347805500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1964347805500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1965347805500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1966347805500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1967347677500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1968347677500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1969347677500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1970347677500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1971347549500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1972347549500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1973347549500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1974347549500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1975347421500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1976347421500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1977347421500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1978347421500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1979347293500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1980347293500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1981347293500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1982347293500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1983347165500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1984347165500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1985347165500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1986347165500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1987347037500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1988347037500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1989347037500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1990347037500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1991346909500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1992346909500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1993346909500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1994346909500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1995346781500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 1996346781500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 1997346781500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1998346781500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 1999346653500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2000346653500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2001346653500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2002346653500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2003346525500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2004346525500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2005346525500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2006346525500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2007346397500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2008346397500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2009346397500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2010346397500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2011346269500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2012346269500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2013346269500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2014346269500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2015346141500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2016346141500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2017346141500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2018346141500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2019346013500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2020346013500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2021346013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2022346013500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2023345885500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2024345885500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2025345885500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2026345885500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2027345757500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2028345757500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2029345757500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2030345757500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2031345629500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2032345629500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2033345629500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2034345629500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2035345501500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2036345501500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2037345501500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2038345501500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2039345373500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2040345373500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2041345373500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2042345373500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2043345245500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2044345245500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2045345245500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2046345245500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2047345117500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2048345117500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2049345117500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2050345117500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2051344989500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2052344989500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2053344989500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2054344989500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2055344861500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2056344861500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2057344861500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2058344861500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2059344733500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2060344733500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2061344733500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2062344733500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2063344605500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2064344605500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2065344605500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2066344605500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2067344477500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2068344477500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2069344477500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2070344477500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2071344349500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2072344349500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2073344349500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2074344349500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2075344221500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2076344221500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2077344221500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2078344221500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2079344093500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2080344093500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2081344093500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2082344093500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2083343965500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2084343965500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2085343965500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2086343965500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2087343837500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2088343837500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2089343837500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2090343837500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2091343709500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2092343709500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2093343709500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2094343709500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2095343581500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2096343581500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2097343581500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2098343581500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2099343453500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2100343453500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2101343453500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2102343453500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2103343325500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2104343325500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2105343325500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2106343325500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2107343197500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2108343197500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2109343197500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2110343197500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2111343069500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2112343069500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2113343069500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2114343069500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2115342941500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2116342941500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2117342941500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2118342941500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2119342813500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2120342813500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2121342813500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2122342813500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2123342685500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2124342685500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2125342685500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2126342685500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2127342557500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2128342557500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2129342557500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2130342557500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2131342429500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2132342429500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2133342429500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2134342429500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2135342301500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2136342301500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2137342301500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2138342301500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2139342173500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2140342173500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2141342173500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2142342173500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2143342045500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2144342045500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2145342045500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2146342045500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2147341917500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2148341917500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2149341917500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2150341917500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2151341789500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2152341789500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2153341789500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2154341789500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2155341661500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2156341661500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2157341661500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2158341661500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2159341533500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2160341533500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2161341533500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2162341533500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2163341405500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2164341405500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2165341405500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2166341405500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2167341277500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2168341277500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2169341277500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2170341277500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2171341149500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2172341149500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2173341149500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2174341149500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2175341021500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2176341021500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2177341021500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2178341021500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2179340893500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2180340893500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2181340893500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2182340893500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2183340765500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2184340765500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2185340765500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2186340765500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2187340637500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2188340637500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2189340637500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2190340637500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2191340509500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2192340509500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2193340509500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2194340509500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2195340381500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2196340381500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2197340381500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2198340381500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2199340253500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2200340253500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2201340253500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2202340253500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2203340125500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2204340125500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2205340125500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2206340125500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2207339997500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2208339997500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2209339997500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2210339997500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2211339869500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2212339869500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2213339869500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2214339869500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2215339741500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2216339741500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2217339741500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2218339741500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2219339613500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2220339613500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2221339613500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2222339613500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2223339485500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2224339485500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2225339485500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2226339485500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2227339357500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2228339357500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2229339357500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2230339357500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2231339229500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2232339229500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2233339229500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2234339229500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2235339101500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2236339101500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2237339101500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2238339101500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2239338973500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2240338973500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2241338973500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2242338973500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2243338845500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2244338845500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2245338845500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2246338845500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2247338717500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2248338717500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2249338717500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2250338717500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2251338589500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2252338589500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2253338589500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2254338589500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2255338461500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2256338461500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2257338461500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2258338461500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2259338333500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2260338333500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2261338333500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2262338333500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2263338205500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2264338205500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2265338205500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2266338205500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2267338077500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2268338077500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2269338077500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2270338077500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2271337949500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2272337949500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2273337949500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2274337949500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2275337821500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2276337821500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2277337821500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2278337821500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2279337693500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2280337693500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2281337693500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2282337693500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2283337565500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2284337565500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2285337565500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2286337565500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2287337437500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2288337437500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2289337437500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2290337437500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2291337309500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2292337309500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2293337309500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2294337309500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2295337181500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2296337181500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2297337181500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2298337181500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2299337053500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2300337053500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2301337053500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2302337053500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2303336925500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2304336925500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2305336925500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2306336925500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2307336797500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2308336797500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2309336797500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2310336797500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2311336669500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2312336669500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2313336669500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2314336669500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2315336541500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2316336541500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2317336541500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2318336541500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2319336413500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2320336413500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2321336413500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2322336413500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2323336285500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2324336285500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2325336285500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2326336285500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2327336157500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2328336157500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2329336157500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2330336157500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2331336029500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2332336029500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2333336029500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2334336029500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2335335901500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2336335901500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2337335901500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2338335901500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2339335773500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2340335773500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2341335773500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2342335773500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2343335645500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2344335645500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2345335645500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2346335645500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2347335517500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2348335517500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2349335517500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2350335517500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2351335389500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2352335389500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2353335389500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2354335389500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2355335261500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2356335261500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2357335261500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2358335261500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2359335133500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2360335133500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2361335133500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2362335133500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2363335005500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2364335005500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2365335005500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2366335005500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2367334877500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2368334877500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2369334877500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2370334877500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2371334749500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2372334749500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2373334749500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2374334749500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2375334621500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2376334621500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2377334621500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2378334621500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2379334493500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2380334493500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2381334493500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2382334493500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2383334365500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2384334365500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2385334365500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2386334365500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2387334237500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2388334237500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2389334237500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2390334237500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2391334109500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2392334109500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2393334109500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2394334109500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2395333981500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2396333981500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2397333981500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2398333981500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2399333853500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2400333853500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2401333853500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2402333853500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2403333725500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2404333725500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2405333725500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2406333725500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2407333597500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2408333597500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2409333597500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2410333597500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2411333469500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2412333469500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2413333469500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2414333469500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2415333341500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2416333341500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2417333341500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2418333341500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2419333213500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2420333213500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2421333213500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2422333213500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2423333085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2424333085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2425333085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2426333085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2427332957500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2428332957500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2429332957500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2430332957500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2431332829500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2432332829500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2433332829500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2434332829500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2435332701500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2436332701500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2437332701500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2438332701500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2439332573500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2440332573500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2441332573500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2442332573500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2443332445500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2444332445500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2445332445500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2446332445500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2447332317500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2448332317500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2449332317500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2450332317500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2451332189500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2452332189500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2453332189500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2454332189500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2455332061500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2456332061500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2457332061500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2458332061500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2459331933500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2460331933500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2461331933500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2462331933500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2463331805500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2464331805500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2465331805500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2466331805500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2467331677500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2468331677500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2469331677500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2470331677500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2471331549500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2472331549500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2473331549500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2474331549500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2475331421500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2476331421500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2477331421500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2478331421500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2479331293500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2480331293500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2481331293500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2482331293500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2483331165500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2484331165500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2485331165500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2486331165500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2487331037500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2488331037500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2489331037500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2490331037500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2491330909500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2492330909500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2493330909500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2494330909500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2495330781500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2496330781500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2497330781500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2498330781500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2499330653500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2500330653500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2501330653500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2502330653500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2503330525500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2504330525500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2505330525500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2506330525500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2507330397500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2508330397500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2509330397500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2510330397500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2511330269500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2512330269500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2513330269500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2514330269500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2515330141500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2516330141500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2517330141500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2518330141500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2519330013500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2520330013500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2521330013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2522330013500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2523329885500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2524329885500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2525329885500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2526329885500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2527329757500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2528329757500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2529329757500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2530329757500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2531329629500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2532329629500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2533329629500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2534329629500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2535329501500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2536329501500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2537329501500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2538329501500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2539329373500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2540329373500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2541329373500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2542329373500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2543329245500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2544329245500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2545329245500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2546329245500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2547329117500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2548329117500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2549329117500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2550329117500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2551328989500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2552328989500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2553328989500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2554328989500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2555328861500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2556328861500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2557328861500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2558328861500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2559328733500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2560328733500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2561328733500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2562328733500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2563328605500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2564328605500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2565328605500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2566328605500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2567328477500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2568328477500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2569328477500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2570328477500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2571328349500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2572328349500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2573328349500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2574328349500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2575328221500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2576328221500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2577328221500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2578328221500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2579328093500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2580328093500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2581328093500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2582328093500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2583327965500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2584327965500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2585327965500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2586327965500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2587327837500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2588327837500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2589327837500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2590327837500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2591327709500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2592327709500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2593327709500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2594327709500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2595327581500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2596327581500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2597327581500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2598327581500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2599327453500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2600327453500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2601327453500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2602327453500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2603327325500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2604327325500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2605327325500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2606327325500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2607327197500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2608327197500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2608327199000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2609327199000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2610327199000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2611327069500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2612327069500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2613327069500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2614327069500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2615326941500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2616326941500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2617326941500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2618326941500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2619326813500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2620326813500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2621326813500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2622326813500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2623326685500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2624326685500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2625326685500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2626326685500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2627326557500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2628326557500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2629326557500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2630326557500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2631326429500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2632326429500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2633326429500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2634326429500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2635326301500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2636326301500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2637326301500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2638326301500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2639326173500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2640326173500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2641326173500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2642326173500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2643326045500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2644326045500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2645326045500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2646326045500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2647325917500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2648325917500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2649325917500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2650325917500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2651325789500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2652325789500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2653325789500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2654325789500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2655325661500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2656325661500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2657325661500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2658325661500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2659325533500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2660325533500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2661325533500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2662325533500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2663325405500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2664325405500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2665325405500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2666325405500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2667325277500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2668325277500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2669325277500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2670325277500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2671325149500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2672325149500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2673325149500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2674325149500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2675325021500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2676325021500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2677325021500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2678325021500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2679324893500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2680324893500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2681324893500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2682324893500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2683324765500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2684324765500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2685324765500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2686324765500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2687324637500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2688324637500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2689324637500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2690324637500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2691324509500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2692324509500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2693324509500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2694324509500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2695324381500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2696324381500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2697324381500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2698324381500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2699324253500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2700324253500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2701324253500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2702324253500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2703324125500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2704324125500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2705324125500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2706324125500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2707323997500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2708323997500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2709323997500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2710323997500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2711323869500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2712323869500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2713323869500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2714323869500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2715323741500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2716323741500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2717323741500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2718323741500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2719323613500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2720323613500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2721323613500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2722323613500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2723323485500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2724323485500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2725323485500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2726323485500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2727323357500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2728323357500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2729323357500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2730323357500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2731323229500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2732323229500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2733323229500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2734323229500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2735323101500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2736323101500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2737323101500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2738323101500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2739322973500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2740322973500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2741322973500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2742322973500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2743322845500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2744322845500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2745322845500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2746322845500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2747322717500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2748322717500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2749322717500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2750322717500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2751322589500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2752322589500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2753322589500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2754322589500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2755322461500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2756322461500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2757322461500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2758322461500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2759322333500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2760322333500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2761322333500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2762322333500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2763322205500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2764322205500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2765322205500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2766322205500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2767322077500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2768322077500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2769322077500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2770322077500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2771321949500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2772321949500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2773321949500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2774321949500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2775321821500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2776321821500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2777321821500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2778321821500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2779321693500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2780321693500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2781321693500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2782321693500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2783321565500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2784321565500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2785321565500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2786321565500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2787321437500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2788321437500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2789321437500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2790321437500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2791321309500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2792321309500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2793321309500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2794321309500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2795321181500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2796321181500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2797321181500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2798321181500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2799321053500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2800321053500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2801321053500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2802321053500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2803320925500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2804320925500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2805320925500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2806320925500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2807320797500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2808320797500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2809320797500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2810320797500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2811320669500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2812320669500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2813320669500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2814320669500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2815320541500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2816320541500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2817320541500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2818320541500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2819320413500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2820320413500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2821320413500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2822320413500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2823320285500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2824320285500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2825320285500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2826320285500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2827320157500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2828320157500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2829320157500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2830320157500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2831320029500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2832320029500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2833320029500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2834320029500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2835319901500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2836319901500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2837319901500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2838319901500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2839319773500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2840319773500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2841319773500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2842319773500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2843319645500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2844319645500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2845319645500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2846319645500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2847319517500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2848319517500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2849319517500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2850319517500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2851319389500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2852319389500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2853319389500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2854319389500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2855319261500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2856319261500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2857319261500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2858319261500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2859319133500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2860319133500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2861319133500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2862319133500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2863319005500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2864319005500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2865319005500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2866319005500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2867318877500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2868318877500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2869318877500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2870318877500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2871318749500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2872318749500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2873318749500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2874318749500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2875318621500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2876318621500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2877318621500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2878318621500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2879318493500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2880318493500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2881318493500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2882318493500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2883318365500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2884318365500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2885318365500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2886318365500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2887318237500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2888318237500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2889318237500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2890318237500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2891318109500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2892318109500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2893318109500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2894318109500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2895317981500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2896317981500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2897317981500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2898317981500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2899317853500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2900317853500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2901317853500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2902317853500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2903317725500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2904317725500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2905317725500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2906317725500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2907317597500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2908317597500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2909317597500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2910317597500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2911317469500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2912317469500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2913317469500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2914317469500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2915317341500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2916317341500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2917317341500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2918317341500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2919317213500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2920317213500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2921317213500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2922317213500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2923317085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2924317085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2925317085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2926317085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2927316957500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2928316957500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2929316957500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2930316957500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2931316829500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2932316829500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2933316829500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2934316829500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2935316701500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2936316701500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2937316701500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2938316701500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2939316573500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2940316573500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2941316573500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2942316573500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2943316445500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2944316445500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2945316445500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2946316445500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2947316317500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2948316317500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2949316317500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2950316317500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2951316189500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2952316189500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2953316189500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2954316189500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2955316061500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2956316061500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2957316061500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2958316061500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2959315933500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2960315933500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2961315933500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2962315933500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2963315805500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2964315805500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2965315805500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2966315805500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2967315677500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2968315677500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2969315677500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2970315677500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2971315549500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2972315549500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2973315549500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2974315549500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2975315421500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2976315421500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2977315421500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2978315421500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2979315293500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2980315293500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2981315293500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2982315293500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2983315165500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2984315165500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2985315165500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2986315165500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2987315037500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2988315037500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2989315037500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2990315037500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2991314909500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2992314909500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2993314909500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2994314909500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2995314781500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 2996314781500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 2997314781500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2998314781500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2999314653500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3000314653500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3001314653500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3002314653500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3003314525500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3004314525500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3005314525500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3006314525500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3007314397500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3008314397500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3009314397500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3010314397500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3011314269500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3012314269500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3013314269500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3014314269500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3015314141500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3016314141500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3017314141500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3018314141500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3019314013500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3020314013500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3021314013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3022314013500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3023313885500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3024313885500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3025313885500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3026313885500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3027313757500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3028313757500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3029313757500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3030313757500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3031313629500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3032313629500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3033313629500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3034313629500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3035313501500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3036313501500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3037313501500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3038313501500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3039313373500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3040313373500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3041313373500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3042313373500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3043313245500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3044313245500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3045313245500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3046313245500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3047313117500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3048313117500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3049313117500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3050313117500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3051312989500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3052312989500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3053312989500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3054312989500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3055312861500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3056312861500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3057312861500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3058312861500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3059312733500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3060312733500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3061312733500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3062312733500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3063312605500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3064312605500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3065312605500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3066312605500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3067312477500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3068312477500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3069312477500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3070312477500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3071312349500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3072312349500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3073312349500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3074312349500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3075312221500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3076312221500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3077312221500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3078312221500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3079312093500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3080312093500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3081312093500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3082312093500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3083311965500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3084311965500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3085311965500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3086311965500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3087311837500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3088311837500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3089311837500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3090311837500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3091311709500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3092311709500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3093311709500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3094311709500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3095311581500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3096311581500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3097311581500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3098311581500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3099311453500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3100311453500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3101311453500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3102311453500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3103311325500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3104311325500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3105311325500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3106311325500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3107311197500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3108311197500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3109311197500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3110311197500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3111311069500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3112311069500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3113311069500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3114311069500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3115310941500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3116310941500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3117310941500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3118310941500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3119310813500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3120310813500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3121310813500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3122310813500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3123310685500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3124310685500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3125310685500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3126310685500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3127310557500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3128310557500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3129310557500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3130310557500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3131310429500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3132310429500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3133310429500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3134310429500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3135310301500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3136310301500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3137310301500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3138310301500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3139310173500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3140310173500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3141310173500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3142310173500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3143310045500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3144310045500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3145310045500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3146310045500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3147309917500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3148309917500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3149309917500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3150309917500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3151309789500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3152309789500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3153309789500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3154309789500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3155309661500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3156309661500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3157309661500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3158309661500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3159309533500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3160309533500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3161309533500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3162309533500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3163309405500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3164309405500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3165309405500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3166309405500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3167309277500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3168309277500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3169309277500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3170309277500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3171309149500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3172309149500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3173309149500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3174309149500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3175309021500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3176309021500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3177309021500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3178309021500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3179308893500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3180308893500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3181308893500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3182308893500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3183308765500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3184308765500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3185308765500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3186308765500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3187308637500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3188308637500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3189308637500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3190308637500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3191308509500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3192308509500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3193308509500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3194308509500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3195308381500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3196308381500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3197308381500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3198308381500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3199308253500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3200308253500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3201308253500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3202308253500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3203308125500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3204308125500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3205308125500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3206308125500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3207307997500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3208307997500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3209307997500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3210307997500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3211307869500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3212307869500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3213307869500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3214307869500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3215307741500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3216307741500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3217307741500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3218307741500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3219307613500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3220307613500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3221307613500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3222307613500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3223307485500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3224307485500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3225307485500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3226307485500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3227307357500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3228307357500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3229307357500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3230307357500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3231307229500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3232307229500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3233307229500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3234307229500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3235307101500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3236307101500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3237307101500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3238307101500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3239306973500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 3240306973500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3240306974000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 3241306974000.  Starting simulation...
-info: Entering event queue @ 3241306981500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3241306982500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3242306982500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3242306992000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3243306992000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 3244306992000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3244306999500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3245306999500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3245307007000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3246307007000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 3247307007000.  Starting simulation...
-info: Entering event queue @ 3247307019000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3247307021500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3248307021500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3248307029000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 3249307029000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3249307029500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 3250307029500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3250307030000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3251307030000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3251307037500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3252307037500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3253307037500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3254307037500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3255306461500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3256306461500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3257306461500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3258306461500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3259306333500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3260306333500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3261306333500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3262306333500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3263306205500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3264306205500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3265306205500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3266306205500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3267306077500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3268306077500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3269306077500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3270306077500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3271305949500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3272305949500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3273305949500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3274305949500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3275305821500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3276305821500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3277305821500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3278305821500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3279305693500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3280305693500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3281305693500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3282305693500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3283305565500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3284305565500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3285305565500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3286305565500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3287305437500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3288305437500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3289305437500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3290305437500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3291305309500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3292305309500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3293305309500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3294305309500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3295305181500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3296305181500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3297305181500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3298305181500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3299305053500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3300305053500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3301305053500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3302305053500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3303304925500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3304304925500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3305304925500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3306304925500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3307304797500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3308304797500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3309304797500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3310304797500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3311304669500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3312304669500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3313304669500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3314304669500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3315304541500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3316304541500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3317304541500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3318304541500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3319304413500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3320304413500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3321304413500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3322304413500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3323304285500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3324304285500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3325304285500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3326304285500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3327304157500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3328304157500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3329304157500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3330304157500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3331304029500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3332304029500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3333304029500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3334304029500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3335303901500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3336303901500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3337303901500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3338303901500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3339303773500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3340303773500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3341303773500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3342303773500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3343303645500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3344303645500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3345303645500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3346303645500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3347303517500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3348303517500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3349303517500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3350303517500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3351303389500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3352303389500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3353303389500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3354303389500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3355303261500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3356303261500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3357303261500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3358303261500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3359303133500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3360303133500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3361303133500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3362303133500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3363303005500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3364303005500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3365303005500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3366303005500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3367302877500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3368302877500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3369302877500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3370302877500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3371302749500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3372302749500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3373302749500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3374302749500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3375302621500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3376302621500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3377302621500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3378302621500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3379302493500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3380302493500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3381302493500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3382302493500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3383302365500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3384302365500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3385302365500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3386302365500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3387302237500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3388302237500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3389302237500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3390302237500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3391302109500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3392302109500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3393302109500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3394302109500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3395301981500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3396301981500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3397301981500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3398301981500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3399301853500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3400301853500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3401301853500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3402301853500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3403301725500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3404301725500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3405301725500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3406301725500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3407301597500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3408301597500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3409301597500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3410301597500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3411301469500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3412301469500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3413301469500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3414301469500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3415301341500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3416301341500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3417301341500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3418301341500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3419301213500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3420301213500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3421301213500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3422301213500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3423301085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3424301085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3425301085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3426301085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3427300957500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3428300957500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3429300957500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3430300957500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3431300829500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3432300829500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3433300829500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3434300829500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3435300701500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3436300701500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3437300701500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3438300701500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3439300573500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3440300573500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3441300573500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3442300573500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3443300445500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3444300445500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3445300445500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3446300445500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3447300317500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3448300317500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3449300317500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3450300317500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3451300189500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3452300189500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3453300189500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3454300189500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3455300061500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3456300061500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3457300061500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3458300061500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3459299933500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3460299933500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3461299933500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3462299933500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3463299805500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3464299805500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3465299805500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3466299805500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3467299677500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3468299677500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3469299677500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3470299677500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3471299549500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3472299549500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3473299549500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3474299549500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3475299421500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3476299421500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3477299421500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3478299421500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3479299293500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3480299293500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3481299293500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3482299293500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3483299165500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3484299165500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3485299165500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3486299165500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3487299037500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3488299037500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3489299037500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3490299037500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3491298909500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3492298909500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3493298909500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3494298909500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3495298781500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3496298781500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3497298781500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3498298781500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3499298653500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3500298653500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3501298653500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3502298653500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3503298525500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3504298525500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3505298525500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3506298525500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3507298397500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3508298397500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3509298397500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3510298397500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3511298269500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3512298269500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3513298269500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3514298269500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3515298141500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3516298141500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3517298141500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3518298141500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3519298013500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3520298013500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3521298013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3522298013500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3523297885500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3524297885500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3525297885500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3526297885500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3527297757500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3528297757500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3529297757500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3530297757500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3531297629500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3532297629500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3533297629500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3534297629500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3535297501500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3536297501500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3537297501500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3538297501500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3539297373500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3540297373500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3541297373500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3542297373500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3543297245500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3544297245500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3545297245500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3546297245500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3547297117500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3548297117500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3549297117500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3550297117500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3551296989500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3552296989500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3553296989500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3554296989500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3555296861500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3556296861500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3557296861500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3558296861500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3559296733500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3560296733500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3561296733500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3562296733500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3563296605500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3564296605500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3565296605500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3566296605500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3567296477500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3568296477500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3569296477500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3570296477500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3571296349500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3572296349500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3573296349500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3574296349500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3575296221500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3576296221500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3577296221500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3578296221500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3579296093500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3580296093500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3581296093500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3582296093500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3583295965500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3584295965500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3585295965500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3586295965500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3587295837500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3588295837500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3589295837500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3590295837500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3591295709500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3592295709500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3593295709500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3594295709500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3595295581500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3596295581500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3597295581500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3598295581500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3599295453500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3600295453500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3601295453500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3602295453500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3603295325500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3604295325500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3605295325500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3606295325500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3607295197500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3608295197500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3609295197500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3610295197500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3611295069500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3612295069500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3613295069500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3614295069500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3615294941500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3616294941500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3617294941500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3618294941500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3619294813500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3620294813500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3621294813500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3622294813500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3623294685500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3624294685500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3625294685500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3626294685500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3627294557500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3628294557500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3629294557500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3630294557500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3631294429500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3632294429500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3633294429500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3634294429500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3635294301500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3636294301500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3637294301500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3638294301500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3639294173500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3640294173500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3641294173500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3642294173500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3643294045500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3644294045500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3645294045500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3646294045500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3647293917500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3648293917500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3649293917500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3650293917500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3651293789500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3652293789500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3653293789500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3654293789500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3655293661500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3656293661500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3657293661500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3658293661500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3659293533500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3660293533500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3661293533500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3662293533500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3663293405500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3664293405500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3665293405500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3666293405500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3667293277500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3668293277500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3669293277500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3670293277500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3671293149500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3672293149500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3673293149500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3674293149500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3675293021500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3676293021500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3677293021500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3678293021500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3679292893500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3680292893500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3681292893500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3682292893500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3683292765500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3684292765500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3685292765500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3686292765500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3687292637500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3688292637500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3689292637500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3690292637500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3691292509500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3692292509500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3693292509500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3694292509500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3695292381500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3696292381500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3697292381500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3698292381500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3699292253500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3700292253500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3701292253500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3702292253500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3703292125500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3704292125500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3705292125500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3706292125500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3707291997500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3708291997500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3709291997500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3710291997500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3711291869500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3712291869500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3713291869500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3714291869500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3715291741500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3716291741500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3717291741500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3718291741500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3719291613500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3720291613500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3721291613500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3722291613500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3723291485500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3724291485500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3725291485500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3726291485500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3727291357500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3728291357500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3729291357500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3730291357500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3731291229500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3732291229500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3733291229500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3734291229500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3735291101500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3736291101500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3737291101500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3738291101500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3739290973500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3740290973500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3741290973500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3742290973500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3743290845500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3744290845500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3745290845500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3746290845500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3747290717500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3748290717500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3749290717500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3750290717500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3751290589500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3752290589500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3753290589500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3754290589500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3755290461500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3756290461500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3757290461500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3758290461500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3759290333500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3760290333500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3761290333500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3762290333500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3763290205500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3764290205500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3765290205500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3766290205500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3767290077500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3768290077500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3769290077500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3770290077500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3771289949500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3772289949500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3773289949500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3774289949500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3775289821500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3776289821500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3777289821500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3778289821500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3779289693500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3780289693500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3781289693500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3782289693500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3783289565500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3784289565500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3785289565500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3786289565500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3787289437500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3788289437500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3789289437500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3790289437500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3791289309500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3792289309500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3793289309500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3794289309500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3795289181500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3796289181500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3797289181500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3798289181500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3799289053500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3800289053500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3801289053500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3802289053500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3803288925500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3804288925500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3805288925500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3806288925500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3807288797500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3808288797500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3809288797500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3810288797500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3811288669500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3812288669500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3813288669500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3814288669500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3815288541500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3816288541500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3817288541500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3818288541500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3819288413500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3820288413500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3821288413500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3822288413500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3823288285500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3824288285500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3825288285500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3826288285500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3827288157500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3828288157500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3829288157500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3830288157500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3831288029500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3832288029500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3833288029500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3834288029500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3835287901500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3836287901500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3837287901500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3838287901500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3839287773500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3840287773500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3841287773500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3842287773500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3843287645500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3844287645500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3845287645500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3846287645500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3847287517500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3848287517500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3849287517500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3850287517500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3851287389500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3852287389500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3853287389500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3854287389500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3855287261500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3856287261500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3857287261500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3858287261500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3859287133500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3860287133500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3861287133500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3862287133500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3863287005500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 3864287005500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3864287006000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 3865287006000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3865287013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3866287013500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3866287017500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3867287017500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 3868287017500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3868287018500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3869287018500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3869287022500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 3870287022500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3870287023500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 3871287023500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3871287024000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3872287024000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3872287031500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 3873287031500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3873287032500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3874287032500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3875287032500.  Starting simulation...
-info: Entering event queue @ 3875287061250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3875287068750.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3876287068750.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3877287068750.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3878287068750.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3879286493500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3880286493500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3881286493500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3882286493500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3883286365500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3884286365500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3885286365500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3886286365500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3887286237500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3888286237500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3889286237500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3890286237500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3891286109500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3892286109500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3893286109500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3894286109500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3895285981500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3896285981500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3897285981500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3898285981500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3899285853500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3900285853500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3901285853500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3902285853500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3903285725500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3904285725500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3905285725500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3906285725500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3907285597500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3908285597500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3909285597500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3910285597500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3911285469500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3912285469500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3913285469500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3914285469500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3915285341500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3916285341500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3917285341500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3918285341500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3919285213500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3920285213500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3921285213500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3922285213500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3923285085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3924285085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3925285085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3926285085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3927284957500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3928284957500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3929284957500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3930284957500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3931284829500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3932284829500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3933284829500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3934284829500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3935284701500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3936284701500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3937284701500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3938284701500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3939284573500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3940284573500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3941284573500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3942284573500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3943284445500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3944284445500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3945284445500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3946284445500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3947284317500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3948284317500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3949284317500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3950284317500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3951284189500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3952284189500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3953284189500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3954284189500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3955284061500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3956284061500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3957284061500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3958284061500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3959283933500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3960283933500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3961283933500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3962283933500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3963283805500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3964283805500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3965283805500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3966283805500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3967283677500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3968283677500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3969283677500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3970283677500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3971283549500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3972283549500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3973283549500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3974283549500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3975283421500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3976283421500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3977283421500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3978283421500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3979283293500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3980283293500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3981283293500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3982283293500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3983283165500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3984283165500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3985283165500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3986283165500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3987283037500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3988283037500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3989283037500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3990283037500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3991282909500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3992282909500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3993282909500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3994282909500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3995282781500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 3996282781500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 3997282781500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3998282781500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 3999282653500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4000282653500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4001282653500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4002282653500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4003282525500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4004282525500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4005282525500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4006282525500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4007282397500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4008282397500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4009282397500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4010282397500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4011282269500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4012282269500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4013282269500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4014282269500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4015282141500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4016282141500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4017282141500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4018282141500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4019282013500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4020282013500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4021282013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4022282013500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4023281885500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4024281885500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4025281885500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4026281885500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4027281757500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4028281757500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4029281757500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4030281757500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4031281629500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4032281629500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4033281629500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4034281629500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4035281501500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4036281501500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4037281501500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4038281501500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4039281373500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4040281373500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4041281373500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4042281373500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4043281245500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4044281245500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4045281245500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4046281245500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4047281117500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4048281117500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4049281117500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4050281117500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4051280989500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4052280989500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4053280989500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4054280989500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4055280861500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4056280861500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4057280861500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4058280861500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4059280733500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4060280733500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4061280733500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4062280733500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4063280605500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4064280605500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4065280605500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4066280605500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4067280477500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4068280477500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4069280477500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4070280477500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4071280349500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4072280349500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4073280349500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4074280349500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4075280221500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4076280221500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4077280221500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4078280221500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4079280093500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4080280093500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4081280093500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4082280093500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4083279965500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4084279965500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4085279965500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4086279965500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4087279837500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4088279837500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4089279837500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4090279837500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4091279709500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4092279709500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4093279709500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4094279709500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4095279581500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4096279581500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4097279581500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4098279581500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4099279453500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4100279453500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4101279453500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4102279453500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4103279325500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4104279325500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4105279325500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4106279325500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4107279197500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4108279197500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4109279197500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4110279197500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4111279069500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4112279069500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4113279069500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4114279069500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4115278941500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4116278941500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4117278941500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4118278941500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4119278813500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4120278813500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4121278813500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4122278813500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4123278685500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4124278685500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4125278685500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4126278685500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4127278557500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4128278557500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4129278557500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4130278557500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4131278429500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4132278429500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4133278429500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4134278429500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4135278301500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4136278301500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4137278301500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4138278301500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4139278173500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4140278173500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4141278173500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4142278173500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4143278045500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4144278045500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4145278045500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4146278045500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4147277917500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4148277917500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4149277917500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4150277917500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4151277789500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4152277789500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4153277789500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4154277789500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4155277661500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4156277661500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4157277661500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4158277661500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4159277533500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4160277533500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4161277533500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4162277533500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4163277405500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4164277405500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4165277405500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4166277405500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4167277277500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4168277277500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4169277277500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4170277277500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4171277149500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4172277149500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4173277149500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4174277149500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4175277021500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4176277021500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4177277021500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4178277021500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4179276893500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4180276893500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4181276893500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4182276893500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4183276765500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4184276765500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4185276765500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4186276765500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4187276637500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4188276637500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4189276637500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4190276637500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4191276509500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4192276509500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4193276509500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4194276509500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4195276381500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4196276381500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4197276381500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4198276381500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4199276253500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4200276253500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4201276253500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4202276253500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4203276125500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4204276125500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4205276125500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4206276125500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4207275997500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4208275997500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4209275997500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4210275997500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4211275869500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4212275869500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4213275869500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4214275869500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4215275741500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4216275741500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4217275741500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4218275741500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4219275613500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4220275613500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4221275613500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4222275613500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4223275485500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4224275485500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4225275485500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4226275485500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4227275357500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4228275357500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4229275357500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4230275357500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4231275229500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4232275229500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4233275229500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4234275229500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4235275101500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4236275101500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4237275101500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4238275101500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4239274973500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4240274973500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4241274973500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4242274973500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4243274845500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4244274845500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4245274845500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4246274845500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4247274717500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4248274717500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4249274717500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4250274717500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4251274589500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4252274589500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4253274589500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4254274589500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4255274461500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4256274461500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4257274461500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4258274461500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4259274333500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4260274333500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4261274333500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4262274333500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4263274205500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4264274205500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4265274205500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4266274205500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4267274077500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4268274077500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4269274077500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4270274077500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4271273949500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4272273949500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4273273949500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4274273949500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4275273821500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4276273821500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4277273821500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4278273821500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4279273693500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4280273693500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4281273693500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4282273693500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4283273565500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4284273565500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4285273565500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4286273565500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4287273437500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4288273437500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4289273437500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4290273437500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4291273309500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4292273309500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4293273309500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4294273309500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4295273181500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4296273181500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4297273181500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4298273181500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4299273053500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4300273053500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4301273053500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4302273053500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4303272925500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4304272925500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4305272925500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4306272925500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4307272797500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4308272797500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4309272797500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4310272797500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4311272669500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4312272669500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4313272669500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4314272669500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4315272541500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4316272541500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4317272541500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4318272541500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4319272413500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4320272413500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4321272413500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4322272413500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4323272285500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4324272285500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4325272285500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4326272285500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4327272157500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4328272157500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4329272157500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4330272157500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4331272029500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4332272029500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4333272029500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4334272029500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4335271901500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4336271901500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4337271901500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4338271901500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4339271773500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4340271773500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4341271773500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4342271773500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4343271645500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4344271645500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4345271645500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4346271645500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4347271517500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4348271517500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4349271517500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4350271517500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4351271389500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4352271389500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4353271389500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4354271389500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4355271261500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4356271261500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4357271261500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4358271261500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4359271133500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4360271133500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4361271133500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4362271133500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4363271005500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4364271005500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4365271005500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4366271005500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4367270877500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4368270877500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4369270877500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4370270877500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4371270749500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4372270749500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4373270749500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4374270749500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4375270621500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4376270621500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4377270621500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4378270621500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4379270493500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4380270493500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4381270493500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4382270493500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4383270365500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4384270365500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4385270365500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4386270365500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4387270237500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4388270237500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4389270237500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4390270237500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4391270109500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4392270109500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4393270109500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4394270109500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4395269981500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4396269981500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4397269981500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4398269981500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4399269853500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4400269853500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4401269853500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4402269853500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4403269725500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4404269725500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4405269725500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4406269725500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4407269597500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4408269597500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4409269597500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4410269597500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4411269469500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4412269469500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4413269469500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4414269469500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4415269341500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4416269341500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4417269341500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4418269341500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4419269213500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4420269213500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4421269213500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4422269213500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4423269085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4424269085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4425269085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4426269085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4427268957500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4428268957500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4429268957500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4430268957500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4431268829500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4432268829500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 4433268829500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4433268830000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4434268830000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4434268834000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4435268834000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 4436268834000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4436268835000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4437268835000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4437268839000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4438268839000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 4439268839000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4439268840500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4440268840500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4440268844500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4441268844500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4442268844500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4443268844500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4443268849000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4444268849000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4445268849000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4446268849000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4447268317500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4448268317500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4449268317500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4450268317500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4451268189500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4452268189500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4453268189500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4454268189500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4455268061500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4456268061500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4457268061500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4458268061500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4459267933500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4460267933500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4461267933500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4462267933500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4463267805500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4464267805500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4465267805500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4466267805500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4467267677500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4468267677500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4469267677500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4470267677500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4471267549500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4472267549500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4473267549500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4474267549500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4475267421500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4476267421500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4477267421500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4478267421500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4479267293500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4480267293500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4481267293500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4482267293500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4483267165500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4484267165500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4485267165500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4486267165500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4487267037500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4488267037500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4489267037500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4490267037500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4491266909500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4492266909500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4493266909500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4494266909500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4495266781500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4496266781500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4497266781500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4498266781500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4499266653500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4500266653500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4501266653500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4502266653500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4503266525500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4504266525500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4505266525500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4506266525500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4507266397500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4508266397500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4509266397500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4510266397500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4511266269500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4512266269500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4513266269500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4514266269500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4515266141500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4516266141500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4517266141500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4518266141500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4519266013500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4520266013500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4521266013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4522266013500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4523265885500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4524265885500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4525265885500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4526265885500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4527265757500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4528265757500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4529265757500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4530265757500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4531265629500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4532265629500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4533265629500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4534265629500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4535265501500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4536265501500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4537265501500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4538265501500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4539265373500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4540265373500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4541265373500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4542265373500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4543265245500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4544265245500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4545265245500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4546265245500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4547265117500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4548265117500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4549265117500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4550265117500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4551264989500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4552264989500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4553264989500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4554264989500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4555264861500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4556264861500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4557264861500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4558264861500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4559264733500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4560264733500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4561264733500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4562264733500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4563264605500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4564264605500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4565264605500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4566264605500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4567264477500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4568264477500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4569264477500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4570264477500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4571264349500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4572264349500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4573264349500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4574264349500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4575264221500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4576264221500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4577264221500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4578264221500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4579264093500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4580264093500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4581264093500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4582264093500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4583263965500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4584263965500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4585263965500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4586263965500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4587263837500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4588263837500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4589263837500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4590263837500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4591263709500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4592263709500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4593263709500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4594263709500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4595263581500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4596263581500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4597263581500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4598263581500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4599263453500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4600263453500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4601263453500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4602263453500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4603263325500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4604263325500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4605263325500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4606263325500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4607263197500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4608263197500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4609263197500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4610263197500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4611263069500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4612263069500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4613263069500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4614263069500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4615262941500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4616262941500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4617262941500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4618262941500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4619262813500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4620262813500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4621262813500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4622262813500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4623262685500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4624262685500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4625262685500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4626262685500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4627262557500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4628262557500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4629262557500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4630262557500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4631262429500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4632262429500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4633262429500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4634262429500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4635262301500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4636262301500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4637262301500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4638262301500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4639262173500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4640262173500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4641262173500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4642262173500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4643262045500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4644262045500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4645262045500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4646262045500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4647261917500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4648261917500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4649261917500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4650261917500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4651261789500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4652261789500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4653261789500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4654261789500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4655261661500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4656261661500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4657261661500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4658261661500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4659261533500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4660261533500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4661261533500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4662261533500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4663261405500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4664261405500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4665261405500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4666261405500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4667261277500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4668261277500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4669261277500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4670261277500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4671261149500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4672261149500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4673261149500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4674261149500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4675261021500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4676261021500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4677261021500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4678261021500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4679260893500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4680260893500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4681260893500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4682260893500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4683260765500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4684260765500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4685260765500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4686260765500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4687260637500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4688260637500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4689260637500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4690260637500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4691260509500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4692260509500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4693260509500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4694260509500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4695260381500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4696260381500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4697260381500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4698260381500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4699260253500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4700260253500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4701260253500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4702260253500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4703260125500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4704260125500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4705260125500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4706260125500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4707259997500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4708259997500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4709259997500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4710259997500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4711259869500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4712259869500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4713259869500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4714259869500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4715259741500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4716259741500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4717259741500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4718259741500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4719259613500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4720259613500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4721259613500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4722259613500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4723259485500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4724259485500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4725259485500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4726259485500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4727259357500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4728259357500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4729259357500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4730259357500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4731259229500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4732259229500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4733259229500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4734259229500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4735259101500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4736259101500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4737259101500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4738259101500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4739258973500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4740258973500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4741258973500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4742258973500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4743258845500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4744258845500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4745258845500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4746258845500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4747258717500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4748258717500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4749258717500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4750258717500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4751258589500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4752258589500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4753258589500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4754258589500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4755258461500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4756258461500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4757258461500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4758258461500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4759258333500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4760258333500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4761258333500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4762258333500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4763258205500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4764258205500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4765258205500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4766258205500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4767258077500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4768258077500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4769258077500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4770258077500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4771257949500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4772257949500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4773257949500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4774257949500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4775257821500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4776257821500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4777257821500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4778257821500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4779257693500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4780257693500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4781257693500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4782257693500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4783257565500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4784257565500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4785257565500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4786257565500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4787257437500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4788257437500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4789257437500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4790257437500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4791257309500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4792257309500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4793257309500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4794257309500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4795257181500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4796257181500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4797257181500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4798257181500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4799257053500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4800257053500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4801257053500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4802257053500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4803256925500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4804256925500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4805256925500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4806256925500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4807256797500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4808256797500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4809256797500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4810256797500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4811256669500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4812256669500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4813256669500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4814256669500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4815256541500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4816256541500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4817256541500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4818256541500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4819256413500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4820256413500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4821256413500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4822256413500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4823256285500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4824256285500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4825256285500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4826256285500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4827256157500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4828256157500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4829256157500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4830256157500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4831256029500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4832256029500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4833256029500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4834256029500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4835255901500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4836255901500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4837255901500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4838255901500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4839255773500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4840255773500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4841255773500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4842255773500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4843255645500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4844255645500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4845255645500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4846255645500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4847255517500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4848255517500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4849255517500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4850255517500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4851255389500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4852255389500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4853255389500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4854255389500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4855255261500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4856255261500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4857255261500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4858255261500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4859255133500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4860255133500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4861255133500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4862255133500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4863255005500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4864255005500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4865255005500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4866255005500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4867254877500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4868254877500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4869254877500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4870254877500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4871254749500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4872254749500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4873254749500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4874254749500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4875254621500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4876254621500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4877254621500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4878254621500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4879254493500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4880254493500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4881254493500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4882254493500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4883254365500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4884254365500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4885254365500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4886254365500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4887254237500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4888254237500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4889254237500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4890254237500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4891254109500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4892254109500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4893254109500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4894254109500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4895253981500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4896253981500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4897253981500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4898253981500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4899253853500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4900253853500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4901253853500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4902253853500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4903253725500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4904253725500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4905253725500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4906253725500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4907253597500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4908253597500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4909253597500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4910253597500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4911253469500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4912253469500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4913253469500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4914253469500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4915253341500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4916253341500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4917253341500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4918253341500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4919253213500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4920253213500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4921253213500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4922253213500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4923253085500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4924253085500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4925253085500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4926253085500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4927252957500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4928252957500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4929252957500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4930252957500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4931252829500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4932252829500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4933252829500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4934252829500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4935252701500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4936252701500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4937252701500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4938252701500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4939252573500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4940252573500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4941252573500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4942252573500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4943252445500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4944252445500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4945252445500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4946252445500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4947252317500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4948252317500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4949252317500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4950252317500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4951252189500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4952252189500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4953252189500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4954252189500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4955252061500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4956252061500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4957252061500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4958252061500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4959251933500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4960251933500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4961251933500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4962251933500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4963251805500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4964251805500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4965251805500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4966251805500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4967251677500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4968251677500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4969251677500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4970251677500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4971251549500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4972251549500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4973251549500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4974251549500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4975251421500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4976251421500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4977251421500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4978251421500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4979251293500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4980251293500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4981251293500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4982251293500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4983251165500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4984251165500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4985251165500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4986251165500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4987251037500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4988251037500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4989251037500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4990251037500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4991250909500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4992250909500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4993250909500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4994250909500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4995250781500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 4996250781500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 4997250781500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 4998250781500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 4999250653500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5000250653500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 5001250653500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5001250661000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5002250661000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5002250670500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 5003250670500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5003250671000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 5004250671000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5004250678500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5005250678500.  Starting simulation...
-info: Entering event queue @ 5007250332500.  Starting simulation...
-info: Entering event queue @ 5007250333500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5007250338000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5008250338000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5009250338000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5010250338000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5011250269500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5012250269500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5013250269500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5014250269500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5015250141500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5016250141500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5017250141500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5018250141500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5019250013500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5020250013500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5021250013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5022250013500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5023249885500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5024249885500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5025249885500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5026249885500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5027249757500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5028249757500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5029249757500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5030249757500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5031249629500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5032249629500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5033249629500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5034249629500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5035249501500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5036249501500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5037249501500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5038249501500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5039249373500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5040249373500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5041249373500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5042249373500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5043249245500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5044249245500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5045249245500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5046249245500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5047249117500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5048249117500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5049249117500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5050249117500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5051248989500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5052248989500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5053248989500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5054248989500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5055248861500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5056248861500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5057248861500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5058248861500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5059248733500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5060248733500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5061248733500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5062248733500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5063248605500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5064248605500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5065248605500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5066248605500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5067248477500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5068248477500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5069248477500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5070248477500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5071248349500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5072248349500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5073248349500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5074248349500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5075248221500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5076248221500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5077248221500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5078248221500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5079248093500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5080248093500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5081248093500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5082248093500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5083247965500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5084247965500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5085247965500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5086247965500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5087247837500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5088247837500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5089247837500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5090247837500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5091247709500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5092247709500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5093247709500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5094247709500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5095247581500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5096247581500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5097247581500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5098247581500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5099247453500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5100247453500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5101247453500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5102247453500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5103247325500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5104247325500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-switching cpus
-info: Entering event queue @ 5105247325500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5106247325500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5107247197500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5108247197500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 5109247197500.  Starting simulation...
-info: Entering event queue @ 5109247212000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5109247571250.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5110247571250.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5110247578750.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 5111247578750.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5111247579000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 5112247579000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5112247586500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5113247586500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5113247604500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5114247604500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 5115247604500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5115247621000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5116247621000.  Starting simulation...
-info: Entering event queue @ 5119246748500.  Starting simulation...
-info: Entering event queue @ 5119246749500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5119246754000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-switching cpus
-info: Entering event queue @ 5120246754000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 5121246754000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5121246761500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5122246761500.  Starting simulation...
-info: Entering event queue @ 5123246620500.  Starting simulation...
-info: Entering event queue @ 5123246621500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5123246626000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 5124246626000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5124246627000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 5125246627000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5125246634500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5126246634500.  Starting simulation...
-info: Entering event queue @ 5127246915000.  Starting simulation...
-info: Entering event queue @ 5127246916000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5127246920500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 5128246920500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5128246922000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 5129246922000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5129246929500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5130246929500.  Starting simulation...
-info: Entering event queue @ 5131246364500.  Starting simulation...
-info: Entering event queue @ 5131246365500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5131246370000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 5132246370000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5132246371000.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 5133246371000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5133246378500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 5134246378500.  Starting simulation...
-info: Entering event queue @ 5135246236500.  Starting simulation...
-info: Entering event queue @ 5135246237500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5135246242000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 5136246242000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5136246243500.  Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 5137246243500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 5137246251000.  Starting simulation...

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
index 2b6efde..e293193 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                5137456264000                       # Number of ticks simulated
 final_tick                               5137456264000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 176189                       # Simulator instruction rate (inst/s)
-host_op_rate                                   350219                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3709429360                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1030148                       # Number of bytes of host memory used
-host_seconds                                  1384.97                       # Real time elapsed on the host
+host_inst_rate                                 293296                       # Simulator instruction rate (inst/s)
+host_op_rate                                   582999                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6174974039                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 983548                       # Number of bytes of host memory used
+host_seconds                                   831.98                       # Real time elapsed on the host
 sim_insts                                   244016231                       # Number of instructions simulated
 sim_ops                                     485043652                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::pc.south_bridge.ide      2422400                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.inst           383808                       # Number of bytes read from this memory
@@ -444,6 +446,7 @@
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.membus.respLayer4.occupancy          223775499                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                   103968                       # number of replacements
 system.l2c.tags.tagsinuse                64819.095791                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    3669692                       # Total number of references to valid blocks.
@@ -471,6 +474,15 @@
 system.l2c.tags.occ_percent::cpu2.inst       0.020633                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu2.data       0.071328                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.989061                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        64275                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3733                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         7385                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        52859                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.980759                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 33713228                       # Number of tag accesses
+system.l2c.tags.data_accesses                33713228                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.dtb.walker        21716                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.itb.walker        11486                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.inst             326601                       # number of ReadReq hits
@@ -855,6 +867,11 @@
 system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.092731                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005796                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.005796                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               428661                       # Number of tag accesses
+system.iocache.tags.data_accesses              428661                       # Number of data accesses
 system.iocache.ReadReq_misses::pc.south_bridge.ide          909                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              909                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
@@ -1070,6 +1087,7 @@
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer2.occupancy              957000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
+system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
 system.cpu0.numCycles                      1152461068                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
@@ -1109,6 +1127,13 @@
 system.cpu0.icache.tags.occ_percent::cpu1.inst     0.263409                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::cpu2.inst     0.140938                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.997689                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          138                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          295                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses        130343050                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       130343050                       # Number of data accesses
 system.cpu0.icache.ReadReq_hits::cpu0.inst     87032678                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::cpu1.inst     38704601                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::cpu2.inst      2869740                       # number of ReadReq hits
@@ -1239,6 +1264,13 @@
 system.cpu0.dcache.tags.occ_percent::cpu1.data     0.594149                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::cpu2.data     0.013563                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          226                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          259                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           27                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         88202622                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        88202622                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data      5007486                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::cpu1.data      2456211                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::cpu2.data      4066814                       # number of ReadReq hits

diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index ab0c1f3..09e0d3e 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini

@@ -159,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -514,6 +516,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -530,6 +533,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,9 +632,9 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/dist/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100

diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
index f7ab26f..88b2666 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 01:59:02
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:37:28
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -23,4 +23,4 @@
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 26877484000 because target called exit()
+Exiting @ tick 26911413000 because target called exit()

diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index a6e3b7d..f2d38a4 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                 26911413000                       # Number of ticks simulated
 final_tick                                26911413000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 116759                       # Simulator instruction rate (inst/s)
-host_op_rate                                   117598                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               34685583                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 427272                       # Number of bytes of host memory used
-host_seconds                                   775.87                       # Real time elapsed on the host
+host_inst_rate                                 180996                       # Simulator instruction rate (inst/s)
+host_op_rate                                   182296                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               53768206                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 381936                       # Number of bytes of host memory used
+host_seconds                                   500.51                       # Real time elapsed on the host
 sim_insts                                    90589798                       # Number of instructions simulated
 sim_ops                                      91240351                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             45440                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            947712                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               993152                       # Number of bytes read from this memory
@@ -303,6 +305,7 @@
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.respLayer1.occupancy          145189999                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                26686306                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          22003847                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            843168                       # Number of conditional branches incorrect
@@ -648,6 +651,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   632.612747                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.308893                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.308893                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          732                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          676                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.357422                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          27691521                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         27691521                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     13844401                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        13844401                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      13844401                       # number of demand (read+write) hits
@@ -736,6 +747,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.018879                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.007075                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.327483                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15501                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          513                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1300                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13618                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.473053                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         15189018                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15189018                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst           24                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       903618                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         903642                       # number of ReadReq hits
@@ -893,6 +913,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  3671.733270                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.896419                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.896419                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          448                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3128                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          520                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          59988680                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         59988680                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     23603772                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        23603772                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      4532846                       # number of WriteReq hits

diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
index e8dafca..8155e41 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -75,21 +80,25 @@
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -108,18 +117,21 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -129,9 +141,10 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -143,11 +156,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -160,6 +175,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -169,5 +185,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
index a5dbe98..35b926d 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:18:17
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:39:34
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
index 397354d..be3e030 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                 54240661000                       # Number of ticks simulated
 final_tick                                54240661000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2267620                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2283902                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1357548360                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 366572                       # Number of bytes of host memory used
-host_seconds                                    39.95                       # Real time elapsed on the host
+host_inst_rate                                2327254                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2343964                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1393249116                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 371180                       # Number of bytes of host memory used
+host_seconds                                    38.93                       # Real time elapsed on the host
 sim_insts                                    90602407                       # Number of instructions simulated
 sim_ops                                      91252960                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         431323080                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          90016598                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            521339678                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                   9960199711                       # Throughput (bytes/s)
 system.membus.data_through_bus              540247816                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits

diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
index 08fdda1..f9a7d69 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,18 +100,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -115,6 +126,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -123,6 +135,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -137,14 +150,18 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -163,12 +180,14 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -179,6 +198,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -187,6 +207,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -201,12 +222,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -216,6 +240,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -225,9 +250,10 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -239,11 +265,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -256,6 +284,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -265,5 +294,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
index c84bc1d..92da3b7 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 09:24:43
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:40:24
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
index e75e7c0..f99edcc 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                147135976000                       # Number of ticks simulated
 final_tick                               147135976000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 529408                       # Simulator instruction rate (inst/s)
-host_op_rate                                   533204                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              859987474                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 373720                       # Number of bytes of host memory used
-host_seconds                                   171.09                       # Real time elapsed on the host
+host_inst_rate                                1334589                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1344158                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2167949307                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 379884                       # Number of bytes of host memory used
+host_seconds                                    67.87                       # Real time elapsed on the host
 sim_insts                                    90576861                       # Number of instructions simulated
 sim_ops                                      91226312                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             36992                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            944768                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               981760                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy          138060000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -116,6 +119,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   510.071144                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.249058                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.249058                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          597                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          552                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.291504                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         215662141                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        215662141                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    107830172                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       107830172                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     107830172                       # number of demand (read+write) hits
@@ -198,6 +209,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.015110                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.005897                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.291909                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15323                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2           95                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1478                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13704                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.467621                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         15179780                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15179780                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst           21                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       899975                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         899996                       # number of ReadReq hits
@@ -330,6 +350,14 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  3565.217259                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.870414                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.870414                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1322                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2583                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           63                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          55531122                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         55531122                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     21649218                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        21649218                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      4688372                       # number of WriteReq hits

diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index de11b33..6f2d20a 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,25 @@
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,9 +107,10 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+eventq_index=0
+executable=/dist/cpu2000/binaries/sparc/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -111,11 +122,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +141,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +151,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
index 7edd901..1a4f967 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr

@@ -1,3 +1 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
index db2db18..a8897be 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:07:55
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:41:52
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
index 9196a12..c49cf6b 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                122215823500                       # Number of ticks simulated
 final_tick                               122215823500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2226348                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2226440                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1115942635                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 357000                       # Number of bytes of host memory used
-host_seconds                                   109.52                       # Real time elapsed on the host
+host_inst_rate                                3086610                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3086737                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1547143112                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 361240                       # Number of bytes of host memory used
+host_seconds                                    78.99                       # Real time elapsed on the host
 sim_insts                                   243825150                       # Number of instructions simulated
 sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         977685992                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         328674008                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           1306360000                       # Number of bytes read from this memory
@@ -38,6 +40,7 @@
 system.membus.throughput                  11438757576                       # Throughput (bytes/s)
 system.membus.data_through_bus             1397997177                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  443                       # Number of system calls
 system.cpu.numCycles                        244431648                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started

diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
index 8822738..95a36ae 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.l2cache]
@@ -147,6 +164,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +173,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +188,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +206,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,9 +216,10 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+eventq_index=0
+executable=/dist/cpu2000/binaries/sparc/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -207,11 +231,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +250,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +260,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
index 1e103dc..009ef70 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:07:47
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:43:22
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 7e2d4c7..a787dee 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                361488530000                       # Number of ticks simulated
 final_tick                               361488530000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 810264                       # Simulator instruction rate (inst/s)
-host_op_rate                                   810297                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1201274596                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 365008                       # Number of bytes of host memory used
-host_seconds                                   300.92                       # Real time elapsed on the host
+host_inst_rate                                1454320                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1454380                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2156135283                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 371132                       # Number of bytes of host memory used
+host_seconds                                   167.66                       # Real time elapsed on the host
 sim_insts                                   243825150                       # Number of instructions simulated
 sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             56256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            942336                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               998592                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy          140427000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  443                       # Number of system calls
 system.cpu.numCycles                        722977060                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -74,6 +77,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   725.412977                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.354206                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.354206                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          857                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          781                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.418457                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         488843880                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        488843880                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    244420617                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       244420617                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     244420617                       # number of demand (read+write) hits
@@ -156,6 +167,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.022541                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.004404                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.296955                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15586                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          150                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1385                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13986                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.475647                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         15068052                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15068052                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       892700                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         892703                       # number of ReadReq hits
@@ -288,6 +308,14 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  3562.469056                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.869743                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.869743                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          119                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1418                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2513                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           46                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         211192111                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        211192111                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     81327576                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        81327576                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     22855241                       # number of WriteReq hits

diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index a7b21f1..0b4c31c 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini

@@ -165,6 +165,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -181,6 +182,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -520,6 +522,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -536,6 +539,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,9 +632,9 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/dist/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100

diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
index 0a86dbd..c033cc0 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:42:09
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 19:53:01
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -16,12 +16,12 @@
 nodes                      : 500
 active arcs                : 1905
 simplex iterations         : 1502
+info: Increasing stack size by one page.
 flow value                 : 4990014995
 new implicit arcs          : 23867
 active arcs                : 25772
 simplex iterations         : 2663
-info: Increasing stack size by one page.
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 65497052500 because target called exit()
+Exiting @ tick 65613727000 because target called exit()

diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 999935d..167e490 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                 65613727000                       # Number of ticks simulated
 final_tick                                65613727000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  72100                       # Simulator instruction rate (inst/s)
-host_op_rate                                   126957                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               29943715                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 436724                       # Number of bytes of host memory used
-host_seconds                                  2191.24                       # Real time elapsed on the host
+host_inst_rate                                 111661                       # Simulator instruction rate (inst/s)
+host_op_rate                                   196618                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               46373693                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 390932                       # Number of bytes of host memory used
+host_seconds                                  1414.89                       # Real time elapsed on the host
 sim_insts                                   157988547                       # Number of instructions simulated
 sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             63616                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           1883136                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              1946752                       # Number of bytes read from this memory
@@ -300,6 +302,7 @@
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.respLayer1.occupancy          284209000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                33859770                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          33859770                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            774913                       # Number of conditional branches incorrect
@@ -309,6 +312,7 @@
 system.cpu.branchPred.BTBHitPct             99.461636                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                 5016745                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect               5399                       # Number of incorrect RAS predictions.
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
 system.cpu.numCycles                        131227460                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -599,6 +603,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   819.642194                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.400216                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.400216                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          954                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          867                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.465820                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          51151797                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         51151797                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     25574088                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        25574088                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      25574088                       # number of demand (read+write) hits
@@ -687,6 +699,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020463                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.007473                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.634964                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29922                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          773                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1381                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27646                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.913147                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         33268796                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        33268796                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst           17                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      1993866                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1993883                       # number of ReadReq hits
@@ -821,6 +842,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4069.513707                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.993534                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.993534                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          593                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3349                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          154                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         150351466                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        150351466                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     40071930                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        40071930                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     31341693                       # number of WriteReq hits

diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
index 433f51b..6769a8e 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -76,16 +81,19 @@
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[4]
@@ -93,6 +101,7 @@
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -103,22 +112,26 @@
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -128,9 +141,10 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+eventq_index=0
+executable=/dist/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -142,11 +156,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -159,6 +175,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -168,5 +185,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
index 98402c2..ea41249 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:43:36
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 20:16:46
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
index d28c1e1..17feba7 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                168950040000                       # Number of ticks simulated
 final_tick                               168950040000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1229454                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2164871                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1314755229                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 378084                       # Number of bytes of host memory used
-host_seconds                                   128.50                       # Real time elapsed on the host
+host_inst_rate                                1603557                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2823605                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1714813271                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 379092                       # Number of bytes of host memory used
+host_seconds                                    98.52                       # Real time elapsed on the host
 sim_insts                                   157988548                       # Number of instructions simulated
 sim_ops                                     278192465                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        1741569312                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         717246013                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           2458815325                       # Number of bytes read from this memory
@@ -36,6 +38,8 @@
 system.membus.throughput                  15992825110                       # Throughput (bytes/s)
 system.membus.data_through_bus             2701988442                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
 system.cpu.numCycles                        337900081                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started

diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
index ffd9b2f..9efa1f6 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -69,6 +74,7 @@
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dcache]
 type=BaseCache
@@ -76,6 +82,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -84,6 +91,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -98,18 +106,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
@@ -120,6 +132,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -128,6 +141,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -142,12 +156,15 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -158,16 +175,19 @@
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
@@ -178,6 +198,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -186,6 +207,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -200,12 +222,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -215,6 +240,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -224,9 +250,10 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
+eventq_index=0
+executable=/dist/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -238,11 +265,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -255,6 +284,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -264,5 +294,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
index 0339108..42e3e20 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:48:06
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 20:18:36
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index fa71cbd..ba75a74 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                365989065000                       # Number of ticks simulated
 final_tick                               365989065000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 746941                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1315244                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1730329772                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 386536                       # Number of bytes of host memory used
-host_seconds                                   211.51                       # Real time elapsed on the host
+host_inst_rate                                 696180                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1225861                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1612738645                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 388852                       # Number of bytes of host memory used
+host_seconds                                   226.94                       # Real time elapsed on the host
 sim_insts                                   157988548                       # Number of instructions simulated
 sim_ops                                     278192465                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             51392                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           1871744                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              1923136                       # Number of bytes read from this memory
@@ -52,6 +54,8 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy          270472000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
 system.cpu.numCycles                        731978130                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -86,6 +90,13 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   665.632508                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.325016                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.325016                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          784                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           23                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          715                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.382812                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         435393138                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        435393138                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    217695357                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       217695357                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     217695357                       # number of demand (read+write) hits
@@ -168,6 +179,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.017018                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.004697                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.611630                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29708                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2           78                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1693                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27875                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.906616                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         33177103                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        33177103                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            5                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      1960498                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1960503                       # number of ReadReq hits
@@ -302,6 +322,14 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4076.488619                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.995236                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.995236                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          116                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1796                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2178                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         246505227                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        246505227                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     88818727                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        88818727                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     31333643                       # number of WriteReq hits

diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index 34784c9..d70753e 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini

@@ -159,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -514,6 +516,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -530,6 +533,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,9 +632,9 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/dist/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100

diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
index b4d96e4..5d8946e 100755
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr

@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
index cb7300a..0f922bc 100755
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:08:48
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:41:42
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -67,4 +67,4 @@
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 202349747500 because target called exit()
+Exiting @ tick 202741893000 because target called exit()

diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 3188dad..3185557 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                202741893000                       # Number of ticks simulated
 final_tick                               202741893000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  95210                       # Simulator instruction rate (inst/s)
-host_op_rate                                   107343                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               38205910                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 298452                       # Number of bytes of host memory used
-host_seconds                                  5306.56                       # Real time elapsed on the host
+host_inst_rate                                 148118                       # Simulator instruction rate (inst/s)
+host_op_rate                                   166994                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               59436990                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253144                       # Number of bytes of host memory used
+host_seconds                                  3411.04                       # Real time elapsed on the host
 sim_insts                                   505237723                       # Number of instructions simulated
 sim_ops                                     569624283                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            215232                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           9270080                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              9485312                       # Number of bytes read from this memory
@@ -287,6 +289,7 @@
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         1398080741                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups               182821881                       # Number of BP lookups
 system.cpu.branchPred.condPredicted         143128941                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           7267602                       # Number of conditional branches incorrect
@@ -631,6 +634,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1095.413038                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.534870                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.534870                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1849                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           55                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           82                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          293                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1382                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.902832                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         229105594                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        229105594                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    114523215                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       114523215                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     114523215                       # number of demand (read+write) hits
@@ -719,6 +731,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.011015                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.113503                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.826713                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31255                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2194                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7669                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21321                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.953827                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         19093617                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        19093617                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        13491                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       804384                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         817875                       # number of ReadReq hits
@@ -878,6 +899,14 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4057.514955                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.990604                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.990604                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           34                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2352                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1684                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         391502938                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        391502938                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    136235473                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       136235473                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     50988251                       # number of WriteReq hits

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
index 7b35bd3..3b7a89f 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -75,21 +80,25 @@
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -108,18 +117,21 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -129,9 +141,10 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -143,11 +156,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -160,6 +175,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -169,5 +185,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
index b9241b5..edefc99 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 09:00:02
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:44:24
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
index 14e1e1e..d2cbe9f 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                290498967000                       # Number of ticks simulated
 final_tick                               290498967000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1591705                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1794011                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              912762441                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 237748                       # Number of bytes of host memory used
-host_seconds                                   318.26                       # Real time elapsed on the host
+host_inst_rate                                2346027                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2644207                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1345327991                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 241300                       # Number of bytes of host memory used
+host_seconds                                   215.93                       # Real time elapsed on the host
 sim_insts                                   506581607                       # Number of instructions simulated
 sim_ops                                     570968167                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        2066445500                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         422852701                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           2489298201                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                   9312824252                       # Throughput (bytes/s)
 system.membus.data_through_bus             2705365825                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
index d125ef0..cc298b9 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,18 +100,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -115,6 +126,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -123,6 +135,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -137,14 +150,18 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -163,12 +180,14 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -179,6 +198,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -187,6 +207,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -201,12 +222,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -216,6 +240,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -225,9 +250,10 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/parser
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -239,11 +265,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -256,6 +284,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -265,5 +294,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
index 0a37362..13fa82e 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:48:54
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:45:59
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index 3138d40..feaf610 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                717366012000                       # Number of ticks simulated
 final_tick                               717366012000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1130634                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1274033                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1606137434                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 243872                       # Number of bytes of host memory used
-host_seconds                                   446.64                       # Real time elapsed on the host
+host_inst_rate                                1243497                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1401211                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1766466230                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251064                       # Number of bytes of host memory used
+host_seconds                                   406.10                       # Real time elapsed on the host
 sim_insts                                   504986853                       # Number of instructions simulated
 sim_ops                                     569034839                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            177280                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           8952256                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              9129536                       # Number of bytes read from this memory
@@ -50,6 +52,7 @@
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         1283841000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -124,6 +127,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   982.663229                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.479816                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.479816                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1733                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           22                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          257                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1403                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.846191                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        1033234273                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1033234273                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    516599855                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       516599855                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     516599855                       # number of demand (read+write) hits
@@ -206,6 +218,14 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.008785                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.109054                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.831396                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31177                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          283                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3656                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27181                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.951447                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         18220084                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        18220084                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         8751                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       743573                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         752324                       # number of ReadReq hits
@@ -340,6 +360,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4065.297446                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.992504                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.992504                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          343                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3546                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4          165                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         363052326                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        363052326                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    122957658                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       122957658                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     53883046                       # number of WriteReq hits

diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
index 6c434f4..e184df0 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini

@@ -165,6 +165,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -181,6 +182,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -520,6 +522,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -536,6 +539,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,9 +632,9 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/dist/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100

diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
index 5d75453..185610e 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout

@@ -1,28 +1,15 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 02:08:50
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 20:22:33
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
  Reading the dictionary files: *********info: Increasing stack size by one page.
-**********************************info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-******
+****************************************
  58924 words stored in 3784810 bytes
 
 
@@ -34,8 +21,18 @@
 
 Echoing of input sentence turned on.
 * as had expected the party to be a success , it was a success 
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
 * do you know where John 's 
 * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor 
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
 * how fast the program is it 
 * I am wondering whether to invite to the party 
 * I gave him for his birthday it 
@@ -75,9 +72,11 @@
   the man with whom I play tennis is here 
   there is a dog in the park 
   this is not the man we know and love 
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
   we like to eat at restaurants , usually on weekends 
   what did John say he thought you should do 
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 458276279000 because target called exit()
+Exiting @ tick 459105675500 because target called exit()

diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index d5a6aea..2e6ae08 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

@@ -1,106 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.459341                       # Number of seconds simulated
-sim_ticks                                459340600000                       # Number of ticks simulated
-final_tick                               459340600000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.459106                       # Number of seconds simulated
+sim_ticks                                459105675500                       # Number of ticks simulated
+final_tick                               459105675500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  64463                       # Simulator instruction rate (inst/s)
-host_op_rate                                   119200                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               35810129                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 391936                       # Number of bytes of host memory used
-host_seconds                                 12827.11                       # Real time elapsed on the host
+host_inst_rate                                  97287                       # Simulator instruction rate (inst/s)
+host_op_rate                                   179895                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               54016738                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 345252                       # Number of bytes of host memory used
+host_seconds                                  8499.32                       # Real time elapsed on the host
 sim_insts                                   826877109                       # Number of instructions simulated
 sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            203008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24478016                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24681024                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       203008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          203008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18788608                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18788608                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3172                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             382469                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                385641                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          293572                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               293572                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               441955                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             53289468                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                53731423                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          441955                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             441955                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          40903434                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               40903434                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          40903434                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              441955                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            53289468                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               94634857                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        385641                       # Number of read requests accepted
-system.physmem.writeReqs                       293572                       # Number of write requests accepted
-system.physmem.readBursts                      385641                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     293572                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24669632                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     11392                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18788480                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24681024                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18788608                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      178                       # Number of DRAM read bursts serviced by the write queue
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.bytes_read::cpu.inst            202240                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24471936                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24674176                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       202240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          202240                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18788544                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18788544                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3160                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             382374                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                385534                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          293571                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               293571                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               440509                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             53303493                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                53744001                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          440509                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             440509                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          40924225                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               40924225                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          40924225                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              440509                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            53303493                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               94668226                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        385534                       # Number of read requests accepted
+system.physmem.writeReqs                       293571                       # Number of write requests accepted
+system.physmem.readBursts                      385534                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     293571                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24663936                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     10240                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18787328                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24674176                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18788544                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      160                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         135253                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               24057                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               26446                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               24658                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24494                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               23239                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23672                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24412                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24201                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23613                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23828                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24822                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24051                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23218                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              22963                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              23780                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              24009                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18526                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               19824                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               18930                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18895                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18030                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         133980                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               24056                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               26412                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               24662                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24490                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               23228                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23668                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24406                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24200                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23616                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23822                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24814                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24049                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23223                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              22960                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              23777                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              23991                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18528                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               19813                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               18933                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18904                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18032                       # Per bank write bursts
 system.physmem.perBankWrBursts::5               18409                       # Per bank write bursts
 system.physmem.perBankWrBursts::6               18982                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               18942                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18537                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               18120                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18829                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              17702                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              17342                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              16954                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17718                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              17830                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               18937                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18536                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               18110                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18825                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              17714                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              17347                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              16962                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17712                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              17808                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    459340574000                       # Total gap between requests
+system.physmem.totGap                    459105568000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  385641                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  385534                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 293572                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    380895                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4253                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       284                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 293571                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    380726                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4314                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       297                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -127,31 +129,31 @@
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                     13203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                     13289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                     13319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                     13330                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                     13323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                     13318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                     13380                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                     13367                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                     13383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                     13400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                     13202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                     13293                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                     13312                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                     13323                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                     13320                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                     13319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                     13374                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                     13373                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                     13375                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                     13406                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::10                    13420                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                    13351                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                    13361                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                    13365                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                    13348                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    13319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                    13359                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                    13363                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                    13367                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                    13343                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    13321                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::16                    13314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    13314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    13324                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    13314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    13479                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    13297                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    13309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    13330                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    13311                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    13494                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    13282                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                        5                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::25                        3                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::26                        6                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::27                        3                       # What write queue length does an incoming req see
@@ -159,292 +161,295 @@
 system.physmem.wrQLenPdf::29                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        3                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       147621                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      294.388468                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     155.710774                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     443.499186                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64             63823     43.23%     43.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128            27954     18.94%     62.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192            12395      8.40%     70.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256             7134      4.83%     75.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320             4845      3.28%     78.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384             3604      2.44%     81.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448             2701      1.83%     82.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512             2191      1.48%     84.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576             1897      1.29%     85.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640             1561      1.06%     86.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704             2008      1.36%     88.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768             1215      0.82%     88.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832             1176      0.80%     89.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896             1069      0.72%     90.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960              885      0.60%     91.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024             912      0.62%     91.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088            1043      0.71%     92.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152            1161      0.79%     93.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216            1134      0.77%     93.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280             871      0.59%     94.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344             771      0.52%     95.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408            5235      3.55%     98.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472             297      0.20%     98.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536             223      0.15%     98.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600             174      0.12%     99.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664             140      0.09%     99.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728              99      0.07%     99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792             107      0.07%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856              67      0.05%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920              49      0.03%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984              50      0.03%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048              49      0.03%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112              40      0.03%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176              28      0.02%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240              31      0.02%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304              21      0.01%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368              22      0.01%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432              31      0.02%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496              30      0.02%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560              18      0.01%     99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624              24      0.02%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688              16      0.01%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752              18      0.01%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816              20      0.01%     99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880              17      0.01%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944              18      0.01%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008              17      0.01%     99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072              21      0.01%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136              13      0.01%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200              13      0.01%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264              16      0.01%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328              15      0.01%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392               9      0.01%     99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456              14      0.01%     99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520              12      0.01%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584              17      0.01%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648              16      0.01%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712               8      0.01%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776              10      0.01%     99.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840               9      0.01%     99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904              11      0.01%     99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968               6      0.00%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032              17      0.01%     99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096               7      0.00%     99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160              17      0.01%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224              18      0.01%     99.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288              37      0.03%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352               5      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416               5      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480               6      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544               5      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608               4      0.00%     99.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples       147523                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      294.532839                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     155.815987                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     442.359788                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64             63790     43.24%     43.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128            27848     18.88%     62.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192            12415      8.42%     70.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256             7114      4.82%     75.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320             4845      3.28%     78.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384             3608      2.45%     81.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448             2677      1.81%     82.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512             2233      1.51%     84.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576             1891      1.28%     85.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640             1571      1.06%     86.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704             1991      1.35%     88.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768             1204      0.82%     88.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832             1205      0.82%     89.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896             1076      0.73%     90.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960              955      0.65%     91.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024             927      0.63%     91.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088            1004      0.68%     92.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152            1138      0.77%     93.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216            1120      0.76%     93.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280             845      0.57%     94.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344             784      0.53%     95.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408            5236      3.55%     98.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472             318      0.22%     98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536             229      0.16%     98.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600             157      0.11%     99.09% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1728             103      0.07%     99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792              91      0.06%     99.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856              87      0.06%     99.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920              53      0.04%     99.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984              53      0.04%     99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048              37      0.03%     99.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112              48      0.03%     99.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176              24      0.02%     99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240              28      0.02%     99.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304              24      0.02%     99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368              28      0.02%     99.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432              24      0.02%     99.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496              15      0.01%     99.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560              23      0.02%     99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624              31      0.02%     99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688              20      0.01%     99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752              27      0.02%     99.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816              23      0.02%     99.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880              23      0.02%     99.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944              20      0.01%     99.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008              23      0.02%     99.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072              23      0.02%     99.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136              19      0.01%     99.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200              14      0.01%     99.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264              18      0.01%     99.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328              16      0.01%     99.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392               9      0.01%     99.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456              13      0.01%     99.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520              16      0.01%     99.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584              16      0.01%     99.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648              15      0.01%     99.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712               8      0.01%     99.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776              10      0.01%     99.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840               5      0.00%     99.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904              11      0.01%     99.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968               8      0.01%     99.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032              10      0.01%     99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096               6      0.00%     99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160              14      0.01%     99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224              17      0.01%     99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288              34      0.02%     99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352               3      0.00%     99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416               7      0.00%     99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480               2      0.00%     99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544               6      0.00%     99.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608               2      0.00%     99.92% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::4672               3      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736               4      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800               1      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864               3      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928               5      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992               2      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056               8      0.01%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120               4      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184               3      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248               3      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312               6      0.00%     99.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4736               5      0.00%     99.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4800               6      0.00%     99.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864               1      0.00%     99.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928               6      0.00%     99.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992               5      0.00%     99.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056               6      0.00%     99.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120               5      0.00%     99.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5184               2      0.00%     99.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5248               2      0.00%     99.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312               4      0.00%     99.95% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::5376               3      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440               5      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504               5      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568               4      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632               1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696               4      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760               1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824               2      0.00%     99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5440               6      0.00%     99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5504               3      0.00%     99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5568               1      0.00%     99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632               3      0.00%     99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5696               2      0.00%     99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5760               4      0.00%     99.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5824               4      0.00%     99.97% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::5888               6      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952               3      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016              14      0.01%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080               3      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144               2      0.00%     99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5952               4      0.00%     99.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6016               7      0.00%     99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6080               4      0.00%     99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144               1      0.00%     99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6208               2      0.00%     99.98% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::6272              19      0.01%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336               3      0.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6336               2      0.00%    100.00% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::6528               1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552               1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         147621                       # Bytes accessed per row activation
-system.physmem.totQLat                     3824316500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               12085472750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1927315000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  6333841250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        9921.36                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    16431.77                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::7104               1      0.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         147523                       # Bytes accessed per row activation
+system.physmem.totQLat                     3823508500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               12080026000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1926870000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  6329647500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        9921.55                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    16424.69                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31353.13                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          53.71                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          40.90                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       53.73                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       40.90                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31346.24                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          53.72                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          40.92                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       53.74                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       40.92                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.74                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.42                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.32                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         0.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         9.23                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     326993                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    204419                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.83                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  69.63                       # Row buffer hit rate for writes
-system.physmem.avgGap                       676283.54                       # Average gap between requests
-system.physmem.pageHitRate                      78.26                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               5.85                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     94634857                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              178796                       # Transaction distribution
-system.membus.trans_dist::ReadResp             178796                       # Transaction distribution
-system.membus.trans_dist::Writeback            293572                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           135253                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          135253                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206845                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206845                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1335360                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1335360                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1335360                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43469632                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     43469632                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            43469632                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               43469632                       # Total data (bytes)
+system.physmem.avgWrQLen                         9.75                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     326967                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    204436                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   84.84                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  69.64                       # Row buffer hit rate for writes
+system.physmem.avgGap                       676045.04                       # Average gap between requests
+system.physmem.pageHitRate                      78.27                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               5.78                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                     94668226                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              178706                       # Transaction distribution
+system.membus.trans_dist::ReadResp             178706                       # Transaction distribution
+system.membus.trans_dist::Writeback            293571                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           133980                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          133980                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206828                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206828                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1332599                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1332599                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1332599                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43462720                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     43462720                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            43462720                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               43462720                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          3391724500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          3389205500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3901051256                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3898787780                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.8                       # Layer utilization (%)
-system.cpu.branchPred.lookups               205617807                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         205617807                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           9908418                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            117215133                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               114724662                       # Number of BTB hits
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.branchPred.lookups               205604659                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         205604659                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           9906655                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            117175952                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               114700451                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.875299                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                25059559                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1805276                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.887364                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                25061463                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1805826                       # Number of incorrect RAS predictions.
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        918840117                       # number of cpu cycles simulated
+system.cpu.numCycles                        918372988                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          167454161                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1131890109                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   205617807                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          139784221                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     352321921                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                71123589                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              305412308                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                47848                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        248697                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           51                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 162055223                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2523762                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          886447009                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.375660                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.323512                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          167405307                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1131731622                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   205604659                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          139761914                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     352276692                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                71095438                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              305025706                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                47339                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        248116                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           42                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 162029256                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2531741                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          885941657                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.376715                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.323883                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                538196407     60.71%     60.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 23398337      2.64%     63.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 25267875      2.85%     66.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 27893164      3.15%     69.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 17745237      2.00%     71.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 22915160      2.59%     73.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 29437572      3.32%     77.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 26645476      3.01%     80.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                174947781     19.74%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                537736172     60.70%     60.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 23397075      2.64%     63.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 25259789      2.85%     66.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 27891024      3.15%     69.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 17747651      2.00%     71.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 22912562      2.59%     73.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 29424314      3.32%     77.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 26642726      3.01%     80.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                174930344     19.75%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            886447009                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.223780                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.231868                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                222604172                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             260544811                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 295377211                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              46958792                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               60962023                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2071584997                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                     1                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               60962023                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                256124443                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               115849529                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          18111                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 306710232                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             146782671                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2035392094                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 19900                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               24933273                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents             106586441                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2138335278                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5151319538                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3273897775                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             39701                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            885941657                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.223879                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.232322                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                222573687                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             260132185                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 295357990                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              46939340                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               60938455                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2071381091                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                     5                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               60938455                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                256079146                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               115670707                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          18358                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 306659021                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             146575970                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2035220367                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 19921                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               24919931                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             106353414                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2138170371                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5150798156                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3273538468                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             41295                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                524294424                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1242                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1171                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 346564705                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            495938130                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           194456766                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         195343621                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         54992684                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1975627132                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               13244                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1772183771                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            484863                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       441729805                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    735457697                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          12692                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     886447009                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.999199                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.882883                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                524129517                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1246                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1179                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 346542949                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            495881862                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           194416479                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         195473768                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         54732552                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1975446731                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               13521                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1772053501                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            482535                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       441556981                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    735252947                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          12969                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     885941657                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.000192                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.883038                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           269548828     30.41%     30.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           152175288     17.17%     47.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           137113127     15.47%     63.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           132050060     14.90%     77.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            91550725     10.33%     88.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            55998430      6.32%     94.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            34403840      3.88%     98.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            11839729      1.34%     99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1766982      0.20%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           269231258     30.39%     30.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           151900240     17.15%     47.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           137366514     15.51%     63.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           131748871     14.87%     77.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            91701810     10.35%     88.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            55961984      6.32%     94.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            34425337      3.89%     98.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            11840706      1.34%     99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1764937      0.20%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       886447009                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       885941657                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 4936288     32.45%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.45% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                7665302     50.39%     82.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2609145     17.15%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 4931859     32.39%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                7680982     50.45%     82.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2612006     17.16%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2622898      0.15%      0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1165798232     65.78%     65.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               353842      0.02%     65.95% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               3880856      0.22%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2622482      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1165712605     65.78%     65.93% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               353084      0.02%     65.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               3880807      0.22%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   5      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.17% # Type of FU issued
@@ -471,84 +476,84 @@
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            429305841     24.22%     90.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           170222097      9.61%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            429261253     24.22%     90.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           170223265      9.61%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1772183771                       # Type of FU issued
-system.cpu.iq.rate                           1.928718                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    15210735                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.008583                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4446495646                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2417577635                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1744952561                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               14503                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              50594                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses         3428                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1784764794                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                    6814                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        172654482                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1772053501                       # Type of FU issued
+system.cpu.iq.rate                           1.929558                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    15224847                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.008592                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4445741046                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2417220510                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1744818779                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               14995                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              52000                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         3560                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1784648801                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    7065                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        172668148                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    111836934                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       389891                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       330016                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     45296580                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    111780722                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       387016                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       326982                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     45256293                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        14646                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads        15018                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked           570                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               60962023                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                68066484                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               7196875                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1975640376                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            789853                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             495939091                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            194456766                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               3282                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                4474777                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 82775                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         330016                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        5907886                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      4422310                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             10330196                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1753064930                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             424170565                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          19118841                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               60938455                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                67998417                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               7163340                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1975460252                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            795198                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             495882879                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            194416479                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               3400                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                4461902                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 83950                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         326982                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        5904539                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      4423611                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             10328150                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1752928715                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             424128579                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          19124786                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    590955910                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                167475793                       # Number of branches executed
-system.cpu.iew.exec_stores                  166785345                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.907911                       # Inst execution rate
-system.cpu.iew.wb_sent                     1749812928                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1744955989                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1325071537                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1945900521                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    590915769                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                167467646                       # Number of branches executed
+system.cpu.iew.exec_stores                  166787190                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.908733                       # Inst execution rate
+system.cpu.iew.wb_sent                     1749675549                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1744822339                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1324948168                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1945614075                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.899086                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.680955                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.899906                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.680992                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       446680078                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       446501460                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           9936737                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    825484986                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.852231                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.435254                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           9934679                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    825003202                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.853312                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.435859                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    333347760     40.38%     40.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    193315332     23.42%     63.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     63291763      7.67%     71.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     92551196     11.21%     82.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     24974559      3.03%     85.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     27516320      3.33%     89.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      9293108      1.13%     90.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     11361813      1.38%     91.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     69833135      8.46%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    333018307     40.37%     40.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    193164035     23.41%     63.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     63275385      7.67%     71.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     92552193     11.22%     82.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     24927805      3.02%     85.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     27507260      3.33%     89.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      9364368      1.14%     90.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     11367203      1.38%     91.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     69826646      8.46%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    825484986                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    825003202                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
 system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -559,228 +564,245 @@
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1526605509                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             17673145                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              69833135                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              69826646                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2731320630                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4012461124                       # The number of ROB writes
-system.cpu.timesIdled                         3340699                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        32393108                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   2730666717                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4012080782                       # The number of ROB writes
+system.cpu.timesIdled                         3354849                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        32431331                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
 system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             826877109                       # Number of Instructions Simulated
-system.cpu.cpi                               1.111217                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.111217                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.899914                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.899914                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2716389897                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1420532102                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      3421                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       19                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 597244921                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                405448259                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               964724023                       # number of misc regfile reads
+system.cpu.cpi                               1.110652                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.110652                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.900372                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.900372                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2716202384                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1420402354                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      3547                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       23                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 597198676                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                405403172                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               964659775                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               697845146                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1906044                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1906043                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2330771                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq       136656                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp       136656                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       771758                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       771758                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       150484                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7672451                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7822935                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       439424                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311357120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      311796544                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         311796544                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus      8752064                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     4906973310                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput               697995780                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        1904573                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1904572                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2330749                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq       135378                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp       135378                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       771770                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       771770                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       149099                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7669617                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7818716                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       435968                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311347520                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      311783488                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         311783488                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus      8670336                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     4905098758                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     215891495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     213898487                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3953569925                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3952694158                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              5335                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1037.583647                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           161907582                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              6916                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          23410.581550                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              5304                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1036.579952                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           161882998                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              6874                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          23550.043352                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1037.583647                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.506633                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.506633                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    161909622                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       161909622                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     161909622                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        161909622                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    161909622                       # number of overall hits
-system.cpu.icache.overall_hits::total       161909622                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       145600                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        145600                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       145600                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         145600                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       145600                       # number of overall misses
-system.cpu.icache.overall_misses::total        145600                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    941474740                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    941474740                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    941474740                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    941474740                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    941474740                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    941474740                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    162055222                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    162055222                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    162055222                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    162055222                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    162055222                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    162055222                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000898                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000898                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000898                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000898                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000898                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000898                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6466.172665                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  6466.172665                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  6466.172665                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  6466.172665                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  6466.172665                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  6466.172665                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          250                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          170                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 6                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    41.666667                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          170                       # average number of cycles each access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1036.579952                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.506143                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.506143                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1570                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           44                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          248                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1211                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.766602                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         324200798                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        324200798                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    161884991                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       161884991                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     161884991                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        161884991                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    161884991                       # number of overall hits
+system.cpu.icache.overall_hits::total       161884991                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       144265                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        144265                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       144265                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         144265                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       144265                       # number of overall misses
+system.cpu.icache.overall_misses::total        144265                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    939571727                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    939571727                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    939571727                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    939571727                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    939571727                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    939571727                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    162029256                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    162029256                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    162029256                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    162029256                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    162029256                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    162029256                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000890                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000890                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000890                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000890                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000890                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000890                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6512.818265                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  6512.818265                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  6512.818265                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  6512.818265                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  6512.818265                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  6512.818265                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          329                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 8                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    41.125000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1982                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1982                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1982                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1982                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1982                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1982                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       143618                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       143618                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       143618                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       143618                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       143618                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       143618                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    562974254                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    562974254                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    562974254                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    562974254                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    562974254                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    562974254                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000886                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000886                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000886                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000886                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000886                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000886                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3919.942166                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3919.942166                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3919.942166                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  3919.942166                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3919.942166                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  3919.942166                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1978                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1978                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1978                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1978                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1978                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1978                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       142287                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       142287                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       142287                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       142287                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       142287                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       142287                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    558890013                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    558890013                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    558890013                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    558890013                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    558890013                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    558890013                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000878                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000878                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000878                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000878                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000878                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000878                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3927.906365                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3927.906365                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3927.906365                       # average overall mshr miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::total  3927.906365                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           352959                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29669.713018                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3697218                       # Total number of references to valid blocks.
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 system.cpu.l2cache.tags.warmup_cycle     199249645000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21121.996968                       # Average occupied blocks per requestor
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-system.cpu.l2cache.Writeback_hits::writebacks      2330771                       # number of Writeback hits
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 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -789,168 +811,176 @@
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
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-system.cpu.l2cache.overall_mshr_miss_latency::total  23677770979                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.462065                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099649                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.101056                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.989558                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.989558                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268049                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268049                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.462065                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150933                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.151774                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.462065                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150933                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.151774                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63884.966908                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62384.793394                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62411.416047                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.547789                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.547789                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60515.577607                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60515.577607                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63884.966908                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61373.839466                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61394.499331                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63884.966908                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61373.839466                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61394.499331                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks       293571                       # number of writebacks
+system.cpu.l2cache.writebacks::total           293571                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3161                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       175546                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       178707                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       133955                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total       133955                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206853                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206853                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3161                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       382399                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       385560                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3161                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       382399                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       385560                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    201970750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  10947076960                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  11149047710                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   1342825429                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   1342825429                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12520595025                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12520595025                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    201970750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  23467671985                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  23669642735                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    201970750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  23467671985                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  23669642735                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.463966                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099613                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.101016                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.989489                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.989489                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268024                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268024                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.463966                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150904                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.151743                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.463966                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150904                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.151743                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63894.574502                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62360.161781                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62387.302736                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.451711                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.451711                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60528.950632                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60528.950632                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63894.574502                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61369.595593                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61390.296543                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63894.574502                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61369.595593                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61390.296543                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           2530088                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4088.247279                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           395994774                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2534184                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            156.261256                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           2529960                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4088.243311                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           395939715                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2534056                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            156.247421                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        1794365000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4088.247279                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998107                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998107                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    247245006                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       247245006                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148235012                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148235012                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     395480018                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        395480018                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    395480018                       # number of overall hits
-system.cpu.dcache.overall_hits::total       395480018                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2882280                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2882280                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       925190                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       925190                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3807470                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3807470                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3807470                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3807470                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  58083545125                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  58083545125                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  26852968678                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  26852968678                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  84936513803                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  84936513803                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  84936513803                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  84936513803                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    250127286                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    250127286                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data  4088.243311                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998106                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998106                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          739                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3316                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         801001196                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        801001196                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    247190433                       # number of ReadReq hits
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+system.cpu.dcache.WriteReq_misses::cpu.data       923912                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       923912                       # number of WriteReq misses
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+system.cpu.dcache.demand_misses::total        3806847                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3806847                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3806847                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  58045368359                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  58045368359                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  26823619163                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  26823619163                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  84868987522                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  84868987522                       # number of demand (read+write) miss cycles
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+system.cpu.dcache.overall_miss_latency::total  84868987522                       # number of overall miss cycles
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 system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    399287488                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    399287488                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    399287488                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    399287488                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011523                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.011523                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006203                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.006203                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009536                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009536                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009536                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009536                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20151.943991                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 20151.943991                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29024.274666                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29024.274666                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22307.861599                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22307.861599                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22307.861599                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22307.861599                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         5821                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    399233570                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    399233570                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    399233570                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    399233570                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011528                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.011528                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006194                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.006194                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009535                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009535                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009535                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009535                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20134.123162                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 20134.123162                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29032.655884                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29032.655884                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22293.774224                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22293.774224                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22293.774224                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22293.774224                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         6982                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               669                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               660                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     8.701046                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.578788                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2330771                       # number of writebacks
-system.cpu.dcache.writebacks::total           2330771                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1119584                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1119584                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        17046                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        17046                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1136630                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1136630                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1136630                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1136630                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1762696                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1762696                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       908144                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       908144                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2670840                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2670840                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2670840                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2670840                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30862153254                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  30862153254                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  24727931821                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  24727931821                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  55590085075                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  55590085075                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  55590085075                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  55590085075                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007047                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007047                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006088                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006088                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006689                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006689                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006689                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006689                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17508.494519                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17508.494519                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27229.086820                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27229.086820                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20813.708449                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20813.708449                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20813.708449                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20813.708449                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2330749                       # number of writebacks
+system.cpu.dcache.writebacks::total           2330749                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1120394                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1120394                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        17019                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        17019                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1137413                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1137413                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1137413                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1137413                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1762541                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1762541                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       906893                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       906893                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2669434                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2669434                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2669434                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2669434                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30851541255                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  30851541255                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  24700633087                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  24700633087                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  55552174342                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  55552174342                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  55552174342                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  55552174342                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007048                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007048                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006080                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006080                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006686                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006686                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006686                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006686                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.013385                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.013385                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27236.546193                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27236.546193                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20810.469314                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20810.469314                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20810.469314                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20810.469314                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------

diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
index 397d5a3..bcd42cf 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -76,16 +81,19 @@
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[4]
@@ -93,6 +101,7 @@
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -103,22 +112,26 @@
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -128,9 +141,10 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+eventq_index=0
+executable=/dist/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -142,11 +156,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -159,6 +175,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -168,5 +185,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
index abce0a0..cbb107c 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:44:23
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 20:48:32
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
index 87dac48..4df869d 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                885229328000                       # Number of ticks simulated
 final_tick                               885229328000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1293065                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2391022                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1384315331                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 251216                       # Number of bytes of host memory used
-host_seconds                                   639.47                       # Real time elapsed on the host
+host_inst_rate                                1633857                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3021184                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1749156833                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 252248                       # Number of bytes of host memory used
+host_seconds                                   506.09                       # Real time elapsed on the host
 sim_insts                                   826877110                       # Number of instructions simulated
 sim_ops                                    1528988702                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        8546776520                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data        2285655658                       # Number of bytes read from this memory
 system.physmem.bytes_read::total          10832432178                       # Number of bytes read from this memory
@@ -36,6 +38,8 @@
 system.membus.throughput                  13357308966                       # Throughput (bytes/s)
 system.membus.data_through_bus            11824281640                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
 system.cpu.numCycles                       1770458657                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started

diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
index 3a3bc32..bd4e435 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -69,6 +74,7 @@
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dcache]
 type=BaseCache
@@ -76,6 +82,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -84,6 +91,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -98,18 +106,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
@@ -120,6 +132,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -128,6 +141,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -142,12 +156,15 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -158,16 +175,19 @@
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
@@ -178,6 +198,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -186,6 +207,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -200,12 +222,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -215,6 +240,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -224,9 +250,10 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/parser
+eventq_index=0
+executable=/dist/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -238,11 +265,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -255,6 +284,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -264,5 +294,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
index 59b399b..530ac97 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:41:23
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 20:57:08
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index 43f2a75..c65900a 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                1647872849000                       # Number of ticks simulated
 final_tick                               1647872849000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 788676                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1458350                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1571742015                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 258676                       # Number of bytes of host memory used
-host_seconds                                  1048.44                       # Real time elapsed on the host
+host_inst_rate                                 782951                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1447764                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1560332529                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 260992                       # Number of bytes of host memory used
+host_seconds                                  1056.10                       # Real time elapsed on the host
 sim_insts                                   826877110                       # Number of instructions simulated
 sim_ops                                    1528988702                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            120704                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          24272448                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             24393152                       # Number of bytes read from this memory
@@ -52,6 +54,8 @@
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         3430300500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
 system.cpu.numCycles                       3295745698                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -86,6 +90,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   881.356491                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.430350                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.430350                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1561                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            7                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            8                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1507                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.762207                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        2136696946                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       2136696946                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst   1068344252                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1068344252                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1068344252                       # number of demand (read+write) hits
@@ -168,6 +181,14 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004265                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.247355                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.893750                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32355                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         8220                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        24069                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987396                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         39930218                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        39930218                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst          928                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      1554848                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1555776                       # number of ReadReq hits
@@ -302,6 +323,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4086.415783                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997660                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997660                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           29                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         4038                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1069043234                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1069043234                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    382374772                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       382374772                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    148369158                       # number of WriteReq hits

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
index a921310..c27165d 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -56,6 +60,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fetchBuffSize=4
 function_trace=false
 function_trace_start=0
@@ -90,6 +95,7 @@
 RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
+eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
 instShiftAmt=2
@@ -105,6 +111,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -113,6 +120,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -127,11 +135,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -140,6 +151,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -148,6 +160,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -162,17 +175,23 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -181,6 +200,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -189,6 +209,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -203,12 +224,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -218,6 +242,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -227,7 +252,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -241,11 +267,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -265,6 +293,7 @@
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -276,17 +305,21 @@
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr
index 860580e..abe1622 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr

@@ -49,4 +49,3 @@
 13  8  14
 14  8  14
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
index 3f1389d..8e65391 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 09:53:14
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:48:27
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -11,4 +11,4 @@
 Eon, Version 1.1
 info: Increasing stack size by one page.
 OO-style eon Time= 0.133333
-Exiting @ tick 139916242500 because target called exit()
+Exiting @ tick 139926186500 because target called exit()

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
index 0feb1e3..eb59952 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                139926186500                       # Number of ticks simulated
 final_tick                               139926186500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 122800                       # Simulator instruction rate (inst/s)
-host_op_rate                                   122800                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               43101138                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 261428                       # Number of bytes of host memory used
-host_seconds                                  3246.46                       # Real time elapsed on the host
+host_inst_rate                                 138827                       # Simulator instruction rate (inst/s)
+host_op_rate                                   138827                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               48726388                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236592                       # Number of bytes of host memory used
+host_seconds                                  2871.67                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            214976                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            254016                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               468992                       # Number of bytes read from this memory
@@ -257,6 +259,7 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           68145750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                53489673                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          30685396                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          15149659                       # Number of conditional branches incorrect
@@ -368,6 +371,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1830.939408                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.894013                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.894013                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1928                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          135                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          322                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1366                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.941406                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          97226551                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         97226551                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     48606790                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        48606790                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      48606790                       # number of demand (read+write) hits
@@ -476,6 +488,14 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.088768                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.019152                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.119227                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4717                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          102                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          564                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3928                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.143951                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            77554                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           77554                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst          544                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data          123                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total            667                       # number of ReadReq hits
@@ -608,6 +628,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  3284.890275                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.801975                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.801975                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3388                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          216                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         3109                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.827148                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         336554588                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        336554588                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     94753181                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        94753181                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     73501074                       # number of WriteReq hits

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 427d7de..0f18e6f 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini

@@ -159,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -504,6 +506,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -520,6 +523,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -529,6 +533,7 @@
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -550,6 +555,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -566,6 +572,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -592,7 +599,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/dist/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
index 860580e..abe1622 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr

@@ -49,4 +49,3 @@
 13  8  14
 14  8  14
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
index 58c019f..987d9ef 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 16 2013 01:34:33
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:48:27
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -11,4 +11,4 @@
 Eon, Version 1.1
 info: Increasing stack size by one page.
 OO-style eon Time= 0.066667
-Exiting @ tick 77521581000 because target called exit()
+Exiting @ tick 77516381000 because target called exit()

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 68636d5..39e558e 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                 77516381000                       # Number of ticks simulated
 final_tick                                77516381000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 154118                       # Simulator instruction rate (inst/s)
-host_op_rate                                   154118                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               31808931                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 282024                       # Number of bytes of host memory used
-host_seconds                                  2436.94                       # Real time elapsed on the host
+host_inst_rate                                 222910                       # Simulator instruction rate (inst/s)
+host_op_rate                                   222910                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               46007212                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236600                       # Number of bytes of host memory used
+host_seconds                                  1684.87                       # Real time elapsed on the host
 sim_insts                                   375574808                       # Number of instructions simulated
 sim_ops                                     375574808                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            221184                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            255424                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               476608                       # Number of bytes read from this memory
@@ -250,6 +252,7 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           69562000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                50307155                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          29267262                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           1212205                       # Number of conditional branches incorrect
@@ -582,6 +585,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1831.580097                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.894326                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.894326                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1928                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          133                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          336                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1334                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.941406                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         100598535                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        100598535                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     50291612                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        50291612                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      50291612                       # number of demand (read+write) hits
@@ -670,6 +681,14 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.090728                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.020184                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.122275                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4855                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          149                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           96                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          579                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4031                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148163                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            79325                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           79325                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst          613                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data          131                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total            744                       # number of ReadReq hits
@@ -802,6 +821,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  3295.992263                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.804686                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.804686                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3402                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          215                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         3117                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.830566                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         320069754                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        320069754                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     86510267                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        86510267                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     73500882                       # number of WriteReq hits

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index 9894abc..edbb4f9 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,26 @@
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +108,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +123,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +142,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +152,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
index 28eb112..abe1622 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr

@@ -1,4 +1,3 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
@@ -50,4 +49,3 @@
 13  8  14
 14  8  14
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
index b09a553..e4df237 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 09:53:14
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:48:27
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
index 721e957..2fdd2b1 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                199332411500                       # Number of ticks simulated
 final_tick                               199332411500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1715563                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1715563                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              857781835                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222488                       # Number of bytes of host memory used
-host_seconds                                   232.38                       # Real time elapsed on the host
+host_inst_rate                                3310187                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3310187                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1655094150                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226700                       # Number of bytes of host memory used
+host_seconds                                   120.44                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        1594658604                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         662449271                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           2257107875                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                  13793364824                       # Throughput (bytes/s)
 system.membus.data_through_bus             2749464673                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
index 17feee0..b264a59 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,23 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -147,6 +165,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +174,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +189,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +207,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +217,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +232,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +251,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +261,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
index 860580e..abe1622 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr

@@ -49,4 +49,3 @@
 13  8  14
 14  8  14
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
index b94ac73..ab67caf 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 09:53:14
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:48:27
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
index 3ed6163..143a0b3 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                567335093000                       # Number of ticks simulated
 final_tick                               567335093000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1598767                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1598767                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2275187152                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229960                       # Number of bytes of host memory used
-host_seconds                                   249.36                       # Real time elapsed on the host
+host_inst_rate                                1478735                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1478735                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2104370306                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 235572                       # Number of bytes of host memory used
+host_seconds                                   269.60                       # Real time elapsed on the host
 sim_insts                                   398664609                       # Number of instructions simulated
 sim_ops                                     398664609                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            205120                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            254016                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               459136                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           64566000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -106,6 +109,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1795.138964                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.876533                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.876533                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1904                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          142                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           85                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          251                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1375                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.929688                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         797333005                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        797333005                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    398660993                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       398660993                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     398660993                       # number of demand (read+write) hits
@@ -188,6 +200,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.084548                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.019241                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.115127                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4566                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          135                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2           75                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          497                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3787                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.139343                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            75560                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           75560                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst          468                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data          123                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total            591                       # number of ReadReq hits
@@ -320,6 +341,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  3288.930576                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.802962                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.802962                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3388                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          210                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         3112                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.827148                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         336554592                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        336554592                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     94753540                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        94753540                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     73517528                       # number of WriteReq hits

diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index 8cc45b2..9e26a82 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini

@@ -159,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -514,6 +516,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -530,6 +533,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,7 +632,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/dist/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
index e8096c4..cce4a65 100755
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr

@@ -46,4 +46,3 @@
 12  8  14
 13  8  14
 14  8  14
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
index d3e872f..704a645 100755
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:05:47
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:48:11
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -13,4 +13,4 @@
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 OO-style eon Time= 0.060000
-Exiting @ tick 68375005500 because target called exit()
+Exiting @ tick 68509635500 because target called exit()

diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 356503e..d1e8937 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                 68509635500                       # Number of ticks simulated
 final_tick                                68509635500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 105106                       # Simulator instruction rate (inst/s)
-host_op_rate                                   134373                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               26372946                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303620                       # Number of bytes of host memory used
-host_seconds                                  2597.72                       # Real time elapsed on the host
+host_inst_rate                                 157844                       # Simulator instruction rate (inst/s)
+host_op_rate                                   201796                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               39605771                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257252                       # Number of bytes of host memory used
+host_seconds                                  1729.79                       # Real time elapsed on the host
 sim_insts                                   273036725                       # Number of instructions simulated
 sim_ops                                     349064449                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            194560                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            272384                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               466944                       # Number of bytes read from this memory
@@ -257,6 +259,7 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           67899498                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                35425567                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          21222314                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           1660593                       # Number of conditional branches incorrect
@@ -602,6 +605,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1848.251388                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.902466                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.902466                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1890                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           95                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          206                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1526                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.922852                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          75234453                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         75234453                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     37591948                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        37591948                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      37591948                       # number of demand (read+write) hits
@@ -690,6 +702,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.085036                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.023692                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.120294                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         5394                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1235                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4014                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.164612                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           180292                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          180292                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        12803                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data          301                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total          13104                       # number of ReadReq hits
@@ -845,6 +866,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  3102.941006                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.757554                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.757554                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3197                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          684                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2446                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.780518                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         342019754                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        342019754                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     88929043                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        88929043                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     82031381                       # number of WriteReq hits

diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
index 1c8f49c..098c10a 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -75,21 +80,25 @@
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -108,18 +117,21 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -129,7 +141,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -143,11 +156,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -160,6 +175,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -169,5 +185,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr
index bf930ad..a251961 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr

@@ -45,4 +45,3 @@
 12  8  14
 13  8  14
 14  8  14
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
index 9c8ccea..b3ebb4d 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 09:21:07
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:52:31
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
index 590c33f..02fd510 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                212344043000                       # Number of ticks simulated
 final_tick                               212344043000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1381175                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1765765                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1074152891                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 241892                       # Number of bytes of host memory used
-host_seconds                                   197.69                       # Real time elapsed on the host
+host_inst_rate                                1679583                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2147266                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1306228104                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 246496                       # Number of bytes of host memory used
+host_seconds                                   162.56                       # Real time elapsed on the host
 sim_insts                                   273037663                       # Number of instructions simulated
 sim_ops                                     349065399                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        1394641404                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         480709268                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           1875350672                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                  10715621794                       # Throughput (bytes/s)
 system.membus.data_through_bus             2275398455                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits

diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
index f3f7cd9..aa53807 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,18 +100,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -115,6 +126,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -123,6 +135,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -137,14 +150,18 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -163,12 +180,14 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -179,6 +198,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -187,6 +207,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -201,12 +222,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -216,6 +240,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -225,7 +250,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/eon
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -239,11 +265,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -256,6 +284,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -265,5 +294,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
index bf930ad..a251961 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr

@@ -45,4 +45,3 @@
 12  8  14
 13  8  14
 14  8  14
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
index b54aa45..32b55c3 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:19:15
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:52:55
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index 3139883..5bfa927 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                525834342000                       # Number of ticks simulated
 final_tick                               525834342000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 414348                       # Simulator instruction rate (inst/s)
-host_op_rate                                   529728                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              798851724                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 248008                       # Number of bytes of host memory used
-host_seconds                                   658.24                       # Real time elapsed on the host
+host_inst_rate                                 870200                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1112519                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1677723175                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 255236                       # Number of bytes of host memory used
+host_seconds                                   313.42                       # Real time elapsed on the host
 sim_insts                                   272739283                       # Number of instructions simulated
 sim_ops                                     348687122                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            166976                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            270272                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               437248                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           61488000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -116,6 +119,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1765.993223                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.862301                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.862301                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1807                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          161                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1524                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.882324                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         697336303                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        697336303                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    348644747                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       348644747                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     348644747                       # number of demand (read+write) hits
@@ -198,6 +210,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073499                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.022513                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.106437                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4882                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           46                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1232                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3543                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148987                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           176386                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          176386                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        12994                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data          239                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total          13233                       # number of ReadReq hits
@@ -330,6 +351,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  3078.412981                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.751566                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.751566                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3146                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           11                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          677                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2428                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.768066                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         353296632                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        353296632                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     94570004                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        94570004                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     82049805                       # number of WriteReq hits

diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index 3613fc1..328cf1d 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini

@@ -159,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -504,6 +506,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -520,6 +523,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -529,6 +533,7 @@
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -550,6 +555,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -566,6 +572,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -592,7 +599,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/dist/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
index ca52b45..b38cab2 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr

@@ -4,4 +4,3 @@
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(0, 1, ...)
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index 091ca3b..722b9bf 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 15 2013 18:56:50
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:50:38
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -1387,4 +1385,4 @@
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 631883288500 because target called exit()
+Exiting @ tick 631518097500 because target called exit()

diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 2a6478f..130b228 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                631518097500                       # Number of ticks simulated
 final_tick                               631518097500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 116160                       # Simulator instruction rate (inst/s)
-host_op_rate                                   116160                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               40238771                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 286040                       # Number of bytes of host memory used
-host_seconds                                 15694.27                       # Real time elapsed on the host
+host_inst_rate                                 171044                       # Simulator instruction rate (inst/s)
+host_op_rate                                   171044                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               59250964                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 240608                       # Number of bytes of host memory used
+host_seconds                                 10658.36                       # Real time elapsed on the host
 sim_insts                                  1823043370                       # Number of instructions simulated
 sim_ops                                    1823043370                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            176128                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          30295488                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             30471616                       # Number of bytes read from this memory
@@ -314,6 +316,7 @@
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         4488013500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups               388926557                       # Number of BP lookups
 system.cpu.branchPred.condPredicted         255987580                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          25808786                       # Number of conditional branches incorrect
@@ -646,6 +649,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1658.001589                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.809571                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.809571                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1713                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1567                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.836426                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         789856696                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        789856696                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    394910393                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       394910393                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     394910393                       # number of demand (read+write) hits
@@ -734,6 +745,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001074                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.955840                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.997589                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32736                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          188                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          505                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5021                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26866                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999023                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         13650820                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13650820                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         7273                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      1053738                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1061011                       # number of ReadReq hits
@@ -868,6 +888,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4094.588575                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999655                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999655                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           86                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          284                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          969                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         2365                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4          392                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1343398986                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1343398986                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    458212871                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       458212871                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    209732941                       # number of WriteReq hits

diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index d4071b6..3b24ee7 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,26 @@
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +108,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +123,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +142,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +152,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
index 1c6544a..b38cab2 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr

@@ -1,8 +1,6 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(0, 1, ...)
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
index 0011f9c..385d897 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 09:53:14
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:53:08
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
index e663824..65e5434 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                1004710587000                       # Number of ticks simulated
 final_tick                               1004710587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3493388                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3493388                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1747070946                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225488                       # Number of bytes of host memory used
-host_seconds                                   575.08                       # Real time elapsed on the host
+host_inst_rate                                3768106                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3768106                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1884459398                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229696                       # Number of bytes of host memory used
+host_seconds                                   533.16                       # Real time elapsed on the host
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_ops                                    2008987605                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        8037684280                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data        3569416716                       # Number of bytes read from this memory
 system.physmem.bytes_read::total          11607100996                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                  13131370496                       # Throughput (bytes/s)
 system.membus.data_through_bus            13193226959                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index d6223b4..34c972f 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,23 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -147,6 +165,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +174,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +189,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +207,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +217,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +232,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +251,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +261,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
index ca52b45..b38cab2 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr

@@ -4,4 +4,3 @@
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(0, 1, ...)
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index a19734d..f48beb8 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 09:53:14
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:02:12
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index 4216234..068ca2e 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                2769739533000                       # Number of ticks simulated
 final_tick                               2769739533000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 892879                       # Simulator instruction rate (inst/s)
-host_op_rate                                   892879                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1230989339                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 233984                       # Number of bytes of host memory used
-host_seconds                                  2250.01                       # Real time elapsed on the host
+host_inst_rate                                1540787                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1540787                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2124243508                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 238596                       # Number of bytes of host memory used
+host_seconds                                  1303.87                       # Real time elapsed on the host
 sim_insts                                  2008987605                       # Number of instructions simulated
 sim_ops                                    2008987605                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            137792                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          30284544                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             30422336                       # Number of bytes read from this memory
@@ -50,6 +52,7 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         4278141000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -114,6 +117,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1478.418050                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.721884                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.721884                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1550                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           72                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1428                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.756836                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        4018852738                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       4018852738                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst   2009410475                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      2009410475                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    2009410475                       # number of demand (read+write) hits
@@ -196,6 +207,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000809                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.957636                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.998134                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32732                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          174                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          116                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1143                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        31199                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.998901                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         13642206                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13642206                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         8443                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      1051869                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1060312                       # number of ReadReq hits
@@ -330,6 +350,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4095.197836                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999804                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999804                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          160                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          466                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          999                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2416                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1445259988                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1445259988                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    509611834                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       509611834                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    210722944                       # number of WriteReq hits

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index cbb921b..116b954 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini

@@ -159,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -514,6 +516,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -530,6 +533,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,7 +632,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
index cba73e0..2de5e27 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr

@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: fcntl64(3, 2) passed through to host
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
index 3ba2de4..f17e243 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:40:46
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:55:24
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -1385,4 +1385,4 @@
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 640648369500 because target called exit()
+Exiting @ tick 629535413500 because target called exit()

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 6310afb..f4aa63f 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                629535413500                       # Number of ticks simulated
 final_tick                               629535413500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  71307                       # Simulator instruction rate (inst/s)
-host_op_rate                                    97111                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               32426577                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303200                       # Number of bytes of host memory used
-host_seconds                                 19414.18                       # Real time elapsed on the host
+host_inst_rate                                 111054                       # Simulator instruction rate (inst/s)
+host_op_rate                                   151240                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               50501117                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257896                       # Number of bytes of host memory used
+host_seconds                                 12465.77                       # Real time elapsed on the host
 sim_insts                                  1384370590                       # Number of instructions simulated
 sim_ops                                    1885325342                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            155136                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          30242496                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             30397632                       # Number of bytes read from this memory
@@ -305,6 +307,7 @@
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         4442867738                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups               438247561                       # Number of BP lookups
 system.cpu.branchPred.condPredicted         350864310                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          30620817                       # Number of conditional branches incorrect
@@ -650,6 +653,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1641.273486                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.801403                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.801403                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1685                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1551                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.822754                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         669498564                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        669498564                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    334702534                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       334702534                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     334702534                       # number of demand (read+write) hits
@@ -738,6 +750,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001578                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.955470                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.997256                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32748                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          154                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          507                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5020                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26968                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999390                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         13848752                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13848752                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        22592                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      1058063                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1080655                       # number of ReadReq hits
@@ -897,6 +918,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4094.376677                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999604                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999604                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          262                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          977                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         2409                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4          402                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1949922006                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1949922006                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    695282689                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       695282689                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    276093049                       # number of WriteReq hits

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
index 583a974..879581b 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -75,21 +80,25 @@
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -108,18 +117,21 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -129,7 +141,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -143,11 +156,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -160,6 +175,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -169,5 +185,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
index cba73e0..2de5e27 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr

@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: fcntl64(3, 2) passed through to host
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
index 2dca8a3..6d065fe 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:31:40
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 22:58:19
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index ae323b3..982d92f 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                945613126000                       # Number of ticks simulated
 final_tick                               945613126000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1181509                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1609052                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              807039161                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242488                       # Number of bytes of host memory used
-host_seconds                                  1171.71                       # Real time elapsed on the host
+host_inst_rate                                1817390                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2475033                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1241382789                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 247108                       # Number of bytes of host memory used
+host_seconds                                   761.74                       # Real time elapsed on the host
 sim_insts                                  1384381606                       # Number of instructions simulated
 sim_ops                                    1885336358                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        5561086004                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data        2464405274                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           8025491278                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                   9675679644                       # Throughput (bytes/s)
 system.membus.data_through_bus             9149449674                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index e7d15bd..0bdfc66 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,18 +100,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -115,6 +126,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -123,6 +135,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -137,14 +150,18 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -163,12 +180,14 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -179,6 +198,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -187,6 +207,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -201,12 +222,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -216,6 +240,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -225,7 +250,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -239,11 +265,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -256,6 +284,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -265,5 +294,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
index cba73e0..2de5e27 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr

@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: fcntl64(3, 2) passed through to host
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
index 15b548e..973b4e1 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 09:11:37
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 23:11:12
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 65ea4c6..ecd5fda 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                2326118592000                       # Number of ticks simulated
 final_tick                               2326118592000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 481372                       # Simulator instruction rate (inst/s)
-host_op_rate                                   653016                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              810455855                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 248632                       # Number of bytes of host memory used
-host_seconds                                  2870.14                       # Real time elapsed on the host
+host_inst_rate                                 968971                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1314478                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1631393565                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 255816                       # Number of bytes of host memory used
+host_seconds                                  1425.85                       # Real time elapsed on the host
 sim_insts                                  1381604339                       # Number of instructions simulated
 sim_ops                                    1874244941                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            113472                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          30232512                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             30345984                       # Number of bytes read from this memory
@@ -50,6 +52,7 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         4267404000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -124,6 +127,13 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1392.317060                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.679842                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.679842                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1439                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1339                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.702637                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        2780562807                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       2780562807                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst   1390251699                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1390251699                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1390251699                       # number of demand (read+write) hits
@@ -206,6 +216,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000923                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.957169                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.997708                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32743                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          120                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          144                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1387                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        31024                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999237                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         13744605                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13744605                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        18030                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      1054583                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1072613                       # number of ReadReq hits
@@ -340,6 +359,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4094.947189                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999743                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999743                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          118                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          568                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1040                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2341                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1796115775                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1796115775                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    618874540                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       618874540                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    276862898                       # number of WriteReq hits

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index d10bd65..20b5204 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini

@@ -120,6 +120,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -136,6 +137,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -158,6 +160,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -174,6 +177,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -183,6 +187,7 @@
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -204,6 +209,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -220,6 +226,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -246,7 +253,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr
index 1b49765..506aa6e 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr

@@ -3,4 +3,3 @@
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
index f56fe9b..46359a0 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout

@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 09:55:43
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:16:43
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 43769191000 because target called exit()
+Exiting @ tick 43690025000 because target called exit()

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
index fc01eaf..391c7c3 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                 43690025000                       # Number of ticks simulated
 final_tick                                43690025000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  91247                       # Simulator instruction rate (inst/s)
-host_op_rate                                    91247                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               45127446                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 283120                       # Number of bytes of host memory used
-host_seconds                                   968.15                       # Real time elapsed on the host
+host_inst_rate                                 133116                       # Simulator instruction rate (inst/s)
+host_op_rate                                   133116                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               65834414                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 238716                       # Number of bytes of host memory used
+host_seconds                                   663.64                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            454592                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          10138368                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             10592960                       # Number of bytes read from this memory
@@ -331,6 +333,7 @@
 system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         1521663500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.5                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                18742723                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          12318363                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           4775680                       # Number of conditional branches incorrect
@@ -442,6 +445,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1906.431852                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.930875                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.930875                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2046                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          105                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1090                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          790                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.999023                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          24821911                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         24821911                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     12250505                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        12250505                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      12250505                       # number of demand (read+write) hits
@@ -550,6 +561,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061272                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.054475                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.942712                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32060                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1155                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        17071                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13589                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          108                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978394                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          3980332                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         3980332                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        79314                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        33055                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         112369                       # number of ReadReq hits
@@ -684,6 +704,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4076.382661                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.995211                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.995211                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          922                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3118                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          69984376                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         69984376                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     20180292                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        20180292                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     13574591                       # number of WriteReq hits

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index 08705e6..f15dfa9 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini

@@ -159,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -504,6 +506,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -520,6 +523,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -529,6 +533,7 @@
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -550,6 +555,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -566,6 +572,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -592,7 +599,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
index 1b49765..506aa6e 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr

@@ -3,4 +3,3 @@
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
index d12ffcc..8619111 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout

@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 16 2013 01:34:33
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:24:06
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 24977022500 because target called exit()
+Exiting @ tick 24876941500 because target called exit()

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 63551bc..629fb2f 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                 24876941500                       # Number of ticks simulated
 final_tick                                24876941500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 131928                       # Simulator instruction rate (inst/s)
-host_op_rate                                   131928                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               41235030                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 285168                       # Number of bytes of host memory used
-host_seconds                                   603.30                       # Real time elapsed on the host
+host_inst_rate                                 202143                       # Simulator instruction rate (inst/s)
+host_op_rate                                   202143                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               63181048                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 239772                       # Number of bytes of host memory used
+host_seconds                                   393.74                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            490624                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          10154752                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             10645376                       # Number of bytes read from this memory
@@ -324,6 +326,7 @@
 system.membus.reqLayer0.utilization               5.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         1539567000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              6.2                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                16535475                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          10680150                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            413128                       # Number of conditional branches incorrect
@@ -656,6 +659,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1926.124790                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.940491                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.940491                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           91                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1531                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          359                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          27896466                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         27896466                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     13794941                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        13794941                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      13794941                       # number of demand (read+write) hits
@@ -744,6 +756,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064255                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.068608                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.936727                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32069                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          167                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1443                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        18046                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12352                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4           61                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978668                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          4053036                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         4053036                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        86004                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        34262                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         120266                       # number of ReadReq hits
@@ -878,6 +899,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4074.011744                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.994632                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.994632                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1078                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2940                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          71186914                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         71186914                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     20609776                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        20609776                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     13574069                       # number of WriteReq hits

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index c0c8f0d..16ac17b 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,26 @@
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +108,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +123,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +142,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +152,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
index 1ed7969..506aa6e 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr

@@ -1,7 +1,5 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
index 6c7ff54..faff617 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:03:40
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:27:58
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index db9503e..35c7928 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                 44221003000                       # Number of ticks simulated
 final_tick                                44221003000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2564036                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2564035                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1283487470                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224620                       # Number of bytes of host memory used
-host_seconds                                    34.45                       # Real time elapsed on the host
+host_inst_rate                                3596409                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3596407                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1800265277                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228820                       # Number of bytes of host memory used
+host_seconds                                    24.56                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         353752292                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         126702647                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            480454939                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                  12937468537                       # Throughput (bytes/s)
 system.membus.data_through_bus              572107835                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index b1fb247..927fb8f 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,23 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -147,6 +165,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +174,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +189,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +207,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +217,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +232,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +251,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +261,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
index 1b49765..506aa6e 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr

@@ -3,4 +3,3 @@
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
index f891751..b6a75fd 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:04:18
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:28:33
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index bac0183..dd1fcd9 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                133634727000                       # Number of ticks simulated
 final_tick                               133634727000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 775893                       # Simulator instruction rate (inst/s)
-host_op_rate                                   775893                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1173708198                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 233104                       # Number of bytes of host memory used
-host_seconds                                   113.86                       # Real time elapsed on the host
+host_inst_rate                                1534458                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1534458                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2321204993                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237688                       # Number of bytes of host memory used
+host_seconds                                    57.57                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            432896                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          10136896                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             10569792                       # Number of bytes read from this memory
@@ -50,6 +52,7 @@
 system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         1486377000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -114,6 +117,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1871.686406                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.913909                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.913909                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2045                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          191                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1708                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.998535                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         176952584                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        176952584                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     88361638                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        88361638                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      88361638                       # number of demand (read+write) hits
@@ -196,6 +207,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.057205                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.047481                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.937769                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32056                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          655                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9976                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        21194                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          117                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978271                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          3900109                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         3900109                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        69672                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        33258                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         102930                       # number of ReadReq hits
@@ -330,6 +350,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4078.863631                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.995816                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.995816                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          482                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3562                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          69984374                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         69984374                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     20215872                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        20215872                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     14469799                       # number of WriteReq hits

diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index 9b76986..3a6f7de 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini

@@ -159,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -514,6 +516,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -530,6 +533,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,7 +632,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/dist/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
index 946783e..51d96df 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout

@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:08:44
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 23:17:11
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 26765004500 because target called exit()
+Exiting @ tick 26810051000 because target called exit()

diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index df60742..044953a 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                 26810051000                       # Number of ticks simulated
 final_tick                                26810051000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  86453                       # Simulator instruction rate (inst/s)
-host_op_rate                                   122688                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               32687774                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303000                       # Number of bytes of host memory used
-host_seconds                                   820.19                       # Real time elapsed on the host
+host_inst_rate                                 140336                       # Simulator instruction rate (inst/s)
+host_op_rate                                   199155                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               53060871                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257660                       # Number of bytes of host memory used
+host_seconds                                   505.27                       # Real time elapsed on the host
 sim_insts                                    70907629                       # Number of instructions simulated
 sim_ops                                     100626876                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            299136                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           7943232                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              8242368                       # Number of bytes read from this memory
@@ -333,6 +335,7 @@
 system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         1203686693                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              4.5                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                16646392                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          12773976                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            607235                       # Number of conditional branches incorrect
@@ -678,6 +681,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1808.840382                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.883223                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.883223                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2039                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1260                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          677                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.995605                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          23425177                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         23425177                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     11662047                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        11662047                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      11662047                       # number of demand (read+write) hits
@@ -766,6 +777,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.041899                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.056290                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.912134                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31104                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1849                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        20230                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         8498                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          395                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949219                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          2814320                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         2814320                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        25996                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        33476                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total          59472                       # number of ReadReq hits
@@ -929,6 +949,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4068.859504                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.993374                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.993374                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1767                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2268                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          92301717                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         92301717                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     26063246                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        26063246                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     18266759                       # number of WriteReq hits

diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
index 6172e5c..b489983 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -75,21 +80,25 @@
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -108,18 +117,21 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -129,7 +141,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -143,11 +156,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -160,6 +175,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -169,5 +185,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
index cdf0f47..fd88c13 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:45:30
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 23:25:48
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 9f4bab8..130b6bb 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                 53932157000                       # Number of ticks simulated
 final_tick                                53932157000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2080365                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2952231                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1582195312                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 241268                       # Number of bytes of host memory used
-host_seconds                                    34.09                       # Real time elapsed on the host
+host_inst_rate                                1940189                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2753308                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1475586020                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 245844                       # Number of bytes of host memory used
+host_seconds                                    36.55                       # Real time elapsed on the host
 sim_insts                                    70913181                       # Number of instructions simulated
 sim_ops                                     100632428                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         312580272                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         106573345                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            419153617                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                   9230371187                       # Throughput (bytes/s)
 system.membus.data_through_bus              497813828                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits

diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
index 5e9534b..8802837 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,18 +100,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -115,6 +126,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -123,6 +135,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -137,14 +150,18 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -163,12 +180,14 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -179,6 +198,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -187,6 +207,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -201,12 +222,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -216,6 +240,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -225,7 +250,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -239,11 +265,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -256,6 +284,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -265,5 +294,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
index 6730951..89bb0e0 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 09:31:35
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 23:26:35
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index 178d6c7..7d6b41b 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                132689045000                       # Number of ticks simulated
 final_tick                               132689045000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 525201                       # Simulator instruction rate (inst/s)
-host_op_rate                                   744748                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              990262559                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 247408                       # Number of bytes of host memory used
-host_seconds                                   133.99                       # Real time elapsed on the host
+host_inst_rate                                1019812                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1446120                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1922848599                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254584                       # Number of bytes of host memory used
+host_seconds                                    69.01                       # Real time elapsed on the host
 sim_insts                                    70373628                       # Number of instructions simulated
 sim_ops                                      99791654                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            255488                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           7924480                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              8179968                       # Number of bytes read from this memory
@@ -50,6 +52,7 @@
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         1150308000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -124,6 +127,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1736.497265                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.847899                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.847899                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2018                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          184                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1755                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.985352                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         156309046                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        156309046                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     78126161                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        78126161                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      78126161                       # number of demand (read+write) hits
@@ -206,6 +217,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.035218                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.044809                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.926764                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31095                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          428                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        10156                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        19788                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          616                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.948944                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          2689980                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         2689980                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        14916                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        31426                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total          46342                       # number of ReadReq hits
@@ -340,6 +360,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4076.954355                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.995350                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.995350                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          443                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3604                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          94204142                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         94204142                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     27087367                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        27087367                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     19742869                       # number of WriteReq hits

diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index 0f57053..abfb793 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,25 @@
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +107,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+eventq_index=0
+executable=/dist/cpu2000/binaries/sparc/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +122,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +141,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +151,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
index 401e0da..f7abb9a 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr

@@ -1,4 +1,3 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 warn: ignoring syscall time(4026528248, 4026527848, ...)
 warn: ignoring syscall time(1375098, 4026527400, ...)
@@ -561,4 +560,3 @@
 warn: ignoring syscall time(7004192, 4026526056, ...)
 warn: ignoring syscall time(4, 4026527512, ...)
 warn: ignoring syscall time(0, 4026525760, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
index c44643a..9c35a9a 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:07:56
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:46:20
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index 0c3e0f3..f2f248d 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                 68148672000                       # Number of ticks simulated
 final_tick                                68148672000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2813738                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2850169                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1426739476                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 233072                       # Number of bytes of host memory used
-host_seconds                                    47.77                       # Real time elapsed on the host
+host_inst_rate                                3132375                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3172933                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1588309038                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237324                       # Number of bytes of host memory used
+host_seconds                                    42.91                       # Real time elapsed on the host
 sim_insts                                   134398962                       # Number of instructions simulated
 sim_ops                                     136139190                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         538214280                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         147559360                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            685773640                       # Number of bytes read from this memory
@@ -38,6 +40,7 @@
 system.membus.throughput                  11383698247                       # Throughput (bytes/s)
 system.membus.data_through_bus              775783918                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
 system.cpu.numCycles                        136297345                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started

diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
index e7e0ce2..937ce3e 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.l2cache]
@@ -147,6 +164,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +173,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +188,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +206,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +216,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+eventq_index=0
+executable=/dist/cpu2000/binaries/sparc/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +231,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +250,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +260,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr
index bb51748..f7abb9a 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr

@@ -560,4 +560,3 @@
 warn: ignoring syscall time(7004192, 4026526056, ...)
 warn: ignoring syscall time(4, 4026527512, ...)
 warn: ignoring syscall time(0, 4026525760, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
index 7747f2f..2ff9845 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:10:51
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:47:13
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index b5bc877..7fe81f5 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                202242260000                       # Number of ticks simulated
 final_tick                               202242260000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 788005                       # Simulator instruction rate (inst/s)
-host_op_rate                                   798208                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1185781953                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 240044                       # Number of bytes of host memory used
-host_seconds                                   170.56                       # Real time elapsed on the host
+host_inst_rate                                1441010                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1459668                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2168416558                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 246160                       # Number of bytes of host memory used
+host_seconds                                    93.27                       # Real time elapsed on the host
 sim_insts                                   134398962                       # Number of instructions simulated
 sim_ops                                     136139190                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            591488                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           7826624                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              8418112                       # Number of bytes read from this memory
@@ -50,6 +52,7 @@
 system.membus.reqLayer0.utilization               0.4                       # Layer utilization (%)
 system.membus.respLayer1.occupancy         1183797000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
 system.cpu.numCycles                        404484520                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -82,6 +85,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  2004.815325                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.978914                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.978914                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           74                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          456                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1427                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         269294166                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        269294166                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    134366547                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       134366547                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     134366547                       # number of demand (read+write) hits
@@ -164,6 +176,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.103331                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.037209                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.941490                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        30994                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          533                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12212                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17536                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          585                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.945862                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          3928089                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         3928089                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst       177782                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data        24464                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total         202246                       # number of ReadReq hits
@@ -298,6 +319,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4087.648350                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997961                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997961                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          529                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3530                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         116373718                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        116373718                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     37185801                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        37185801                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     20759140                       # number of WriteReq hits

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
index cd7da39..317ef3f 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini

@@ -120,6 +120,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -136,6 +137,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -158,6 +160,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -174,6 +177,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -183,6 +187,7 @@
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -204,6 +209,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -220,6 +226,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -246,7 +253,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/dist/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
index 1b49765..506aa6e 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr

@@ -3,4 +3,3 @@
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
index 037bfde..45898c9 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:05:17
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:29:41
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -23,4 +23,4 @@
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 1017016979500 because target called exit()
+Exiting @ tick 1009838214500 because target called exit()

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
index 864d4a5..01fe4f8 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                1009838214500                       # Number of ticks simulated
 final_tick                               1009838214500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  87394                       # Simulator instruction rate (inst/s)
-host_op_rate                                    87394                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               48496748                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 275936                       # Number of bytes of host memory used
-host_seconds                                 20822.81                       # Real time elapsed on the host
+host_inst_rate                                 128161                       # Simulator instruction rate (inst/s)
+host_op_rate                                   128161                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               71119760                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 230508                       # Number of bytes of host memory used
+host_seconds                                 14199.12                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             54976                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         125365056                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            125420032                       # Number of bytes read from this memory
@@ -325,6 +327,7 @@
 system.membus.reqLayer0.utilization               1.2                       # Layer utilization (%)
 system.membus.respLayer1.occupancy        18364778000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.8                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups               326538257                       # Number of BP lookups
 system.cpu.branchPred.condPredicted         252572868                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect         138234365                       # Number of conditional branches incorrect
@@ -436,6 +439,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   668.332859                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.326334                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.326334                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          858                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          785                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.418945                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         463858599                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        463858599                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    231927731                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       231927731                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     231927731                       # number of demand (read+write) hits
@@ -544,6 +553,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001058                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.486850                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.943594                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29793                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          158                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          613                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          725                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12815                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15482                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909210                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        106291061                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       106291061                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.data      6044291                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        6044291                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      3693280                       # number of Writeback hits
@@ -675,6 +693,14 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4082.357931                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.996669                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.996669                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          590                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2876                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          593                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           37                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1219759777                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1219759777                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    437268777                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       437268777                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    156014425                       # number of WriteReq hits

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index 3e178e7..20db05a 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini

@@ -159,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -504,6 +506,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -520,6 +523,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -529,6 +533,7 @@
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -550,6 +555,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -566,6 +572,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -592,7 +599,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/dist/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
index 1b49765..506aa6e 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr

@@ -3,4 +3,3 @@
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
index 3d7fe8a..b7f8b90 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 15 2013 19:07:40
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:30:51
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -25,4 +23,4 @@
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 694171131000 because target called exit()
+Exiting @ tick 685386545000 because target called exit()

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index 29e4de4..09d12ec 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                685386545000                       # Number of ticks simulated
 final_tick                               685386545000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 111182                       # Simulator instruction rate (inst/s)
-host_op_rate                                   111182                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               43894428                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 276060                       # Number of bytes of host memory used
-host_seconds                                 15614.43                       # Real time elapsed on the host
+host_inst_rate                                 166100                       # Simulator instruction rate (inst/s)
+host_op_rate                                   166100                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               65575812                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231660                       # Number of bytes of host memory used
+host_seconds                                 10451.82                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             61760                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         125792064                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            125853824                       # Number of bytes read from this memory
@@ -326,6 +328,7 @@
 system.membus.reqLayer0.utilization               1.7                       # Layer utilization (%)
 system.membus.respLayer1.occupancy        18493738500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              2.7                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups               381642976                       # Number of BP lookups
 system.cpu.branchPred.condPredicted         296606399                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          16082111                       # Number of conditional branches incorrect
@@ -657,6 +660,13 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   773.100738                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.377491                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.377491                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          964                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          907                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.470703                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         782110757                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        782110757                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    391053395                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       391053395                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     391053395                       # number of demand (read+write) hits
@@ -745,6 +755,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000819                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.513002                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.958966                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29778                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          146                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          978                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          594                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17297                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        10763                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908752                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        107098856                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       107098856                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.data      6106330                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        6106330                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      3725230                       # number of Writeback hits
@@ -876,6 +895,14 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4087.561673                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997940                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997940                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          690                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2994                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          408                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1430860164                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1430860164                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    538716411                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       538716411                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    155539725                       # number of WriteReq hits

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index 86a7050..6cbd45d 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,26 @@
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +108,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +123,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +142,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +152,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
index 1ed7969..506aa6e 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr

@@ -1,7 +1,5 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
index 33b8f7a..1dfd46c 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:09:10
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:36:30
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
index 87abf8a..8ad24bb 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                913189263000                       # Number of ticks simulated
 final_tick                               913189263000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                4050769                       # Simulator instruction rate (inst/s)
-host_op_rate                                  4050768                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2032728095                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217548                       # Number of bytes of host memory used
-host_seconds                                   449.24                       # Real time elapsed on the host
+host_inst_rate                                3833053                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3833053                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1923475514                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220744                       # Number of bytes of host memory used
+host_seconds                                   474.76                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        7305514036                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data        1974795935                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           9280309971                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                  11068994882                       # Throughput (bytes/s)
 system.membus.data_through_bus            10108087278                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index 482b126..2cb0680 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,23 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -147,6 +165,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +174,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +189,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +207,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +217,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +232,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +251,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +261,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
index 1b49765..506aa6e 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr

@@ -3,4 +3,3 @@
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
index 154161a..43eef16 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:14:34
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 18:44:35
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
index 27c712d..894d37c 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                2623386226000                       # Number of ticks simulated
 final_tick                               2623386226000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1731328                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1731328                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2495874089                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225024                       # Number of bytes of host memory used
-host_seconds                                  1051.09                       # Real time elapsed on the host
+host_inst_rate                                1625838                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1625838                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2343799751                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229480                       # Number of bytes of host memory used
+host_seconds                                  1119.29                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             51328                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         125367104                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            125418432                       # Number of bytes read from this memory
@@ -50,6 +52,7 @@
 system.membus.reqLayer0.utilization               0.4                       # Layer utilization (%)
 system.membus.respLayer1.occupancy        17636967000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -114,6 +117,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   612.458646                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.299052                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.299052                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          801                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          730                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.391113                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        3652757822                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       3652757822                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst   1826377708                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1826377708                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1826377708                       # number of demand (read+write) hits
@@ -196,6 +205,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001192                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.466135                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.931862                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29792                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1059                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1254                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27303                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909180                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        106294313                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       106294313                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.data      6044854                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        6044854                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      3693497                       # number of Writeback hits
@@ -327,6 +345,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4079.262869                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.995914                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.995914                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1238                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2584                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          200                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1219760064                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1219760064                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    437373249                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       437373249                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    158839182                       # number of WriteReq hits

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index d4b4507..c32ff37 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini

@@ -159,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -514,6 +516,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -530,6 +533,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,7 +632,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
index b4d96e4..5d8946e 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr

@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
index 7f1aa92..aa09d17 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:37:44
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 23:27:54
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -24,4 +24,4 @@
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 541686426500 because target called exit()
+Exiting @ tick 533797009000 because target called exit()

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 19d70b5..5e5db11 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                533797009000                       # Number of ticks simulated
 final_tick                               533797009000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 102910                       # Simulator instruction rate (inst/s)
-host_op_rate                                   114803                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               35565366                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 295220                       # Number of bytes of host memory used
-host_seconds                                 15008.90                       # Real time elapsed on the host
+host_inst_rate                                 163502                       # Simulator instruction rate (inst/s)
+host_op_rate                                   182399                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               56505895                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 249880                       # Number of bytes of host memory used
+host_seconds                                  9446.75                       # Real time elapsed on the host
 sim_insts                                  1544563023                       # Number of instructions simulated
 sim_ops                                    1723073835                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             47680                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         143743296                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            143790976                       # Number of bytes read from this memory
@@ -327,6 +329,7 @@
 system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
 system.membus.respLayer1.occupancy        21085487000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              4.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups               303451211                       # Number of BP lookups
 system.cpu.branchPred.condPredicted         249690817                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect          15200865                       # Number of conditional branches incorrect
@@ -668,6 +671,13 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   628.438821                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.306855                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.306855                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          754                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          726                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.368164                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         579143830                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        579143830                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    289570320                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       289570320                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     289570320                       # number of demand (read+write) hits
@@ -756,6 +766,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000618                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.525223                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.962312                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29773                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           79                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1896                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        23750                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3957                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908600                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        111203780                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       111203780                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst           28                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      6288761                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        6288789                       # number of ReadReq hits
@@ -899,6 +918,14 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4088.041920                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.998057                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.998057                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          642                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2397                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1056                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1355914350                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1355914350                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    489062653                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       489062653                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    166956698                       # number of WriteReq hits

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index 4c52e04..1a911e7 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -75,21 +80,25 @@
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -108,18 +117,21 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -129,7 +141,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -143,11 +156,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -160,6 +175,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -169,5 +185,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
index 836ec08..9223280 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:33:02
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 23:35:09
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index c05db51..de1eec5 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                861538200000                       # Number of ticks simulated
 final_tick                               861538200000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2812355                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3137389                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1568696760                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234512                       # Number of bytes of host memory used
-host_seconds                                   549.21                       # Real time elapsed on the host
+host_inst_rate                                2414882                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2693979                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1346991470                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 238968                       # Number of bytes of host memory used
+host_seconds                                   639.60                       # Real time elapsed on the host
 sim_insts                                  1544563041                       # Number of instructions simulated
 sim_ops                                    1723073853                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        6178262356                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data        1581387671                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           7759650027                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                   9731209155                       # Throughput (bytes/s)
 system.membus.data_through_bus             8383808419                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
index 0b3714a..0592444 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,18 +100,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -115,6 +126,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -123,6 +135,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -137,14 +150,18 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -163,12 +180,14 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -179,6 +198,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -187,6 +207,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -201,12 +222,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -216,6 +240,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -225,7 +250,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -239,11 +265,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -256,6 +284,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -265,5 +294,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
index 8e102e9..684ae1c 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:46:27
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 23:38:44
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 0ee2187..3ce47f2 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                2391205115000                       # Number of ticks simulated
 final_tick                               2391205115000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 594937                       # Simulator instruction rate (inst/s)
-host_op_rate                                   663956                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              924522029                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 240640                       # Number of bytes of host memory used
-host_seconds                                  2586.42                       # Real time elapsed on the host
+host_inst_rate                                1202285                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1341761                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1868329144                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 247832                       # Number of bytes of host memory used
+host_seconds                                  1279.86                       # Real time elapsed on the host
 sim_insts                                  1538759601                       # Number of instructions simulated
 sim_ops                                    1717270334                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             39424                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         125322112                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            125361536                       # Number of bytes read from this memory
@@ -50,6 +52,7 @@
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
 system.membus.respLayer1.occupancy        17628966000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -124,6 +127,13 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   514.976015                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.251453                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.251453                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          631                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          606                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.308105                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        3089131818                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       3089131818                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst   1544564952                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      1544564952                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    1544564952                       # number of demand (read+write) hits
@@ -206,6 +216,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000737                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.467360                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.945651                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29768                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1082                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1693                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26880                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908447                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        106351328                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       106351328                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst           22                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data      6048805                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        6048827                       # number of ReadReq hits
@@ -340,6 +359,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4083.522356                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.996954                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.996954                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          157                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1214                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2578                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          146                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        1319055826                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1319055826                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data    475158039                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total       475158039                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    170696898                       # number of WriteReq hits

diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index 593d636..40d9825 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -76,16 +81,19 @@
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[4]
@@ -93,6 +101,7 @@
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -103,22 +112,26 @@
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -128,7 +141,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
+eventq_index=0
+executable=/dist/cpu2000/binaries/x86/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -142,11 +156,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -159,6 +175,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -168,5 +185,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
index 5a2f266..ff491d9 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:38:48
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 21:14:55
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index 256e15d..5fca1ed 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                2846007227500                       # Number of ticks simulated
 final_tick                               2846007227500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1357896                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2115724                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1284732870                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 240864                       # Number of bytes of host memory used
-host_seconds                                  2215.25                       # Real time elapsed on the host
+host_inst_rate                                1743046                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2715824                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1649131867                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 242928                       # Number of bytes of host memory used
+host_seconds                                  1725.76                       # Real time elapsed on the host
 sim_insts                                  3008081022                       # Number of instructions simulated
 sim_ops                                    4686862596                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst       32105863056                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data        5023868345                       # Number of bytes read from this memory
 system.physmem.bytes_read::total          37129731401                       # Number of bytes read from this memory
@@ -36,6 +38,8 @@
 system.membus.throughput                  13588998587                       # Throughput (bytes/s)
 system.membus.data_through_bus            38674388193                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
 system.cpu.numCycles                       5692014456                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started

diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index 8de21ec..5c76444 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -69,6 +74,7 @@
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dcache]
 type=BaseCache
@@ -76,6 +82,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -84,6 +91,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -98,18 +106,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
@@ -120,6 +132,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -128,6 +141,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -142,12 +156,15 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -158,16 +175,19 @@
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
@@ -178,6 +198,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -186,6 +207,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -200,12 +222,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -215,6 +240,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -224,7 +250,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
+eventq_index=0
+executable=/dist/cpu2000/binaries/x86/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -238,11 +265,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -255,6 +284,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -264,5 +294,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
index 2a7659f..d2167f7 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:55:52
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 21:25:13
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index f740c02..49729ff 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                5882580526000                       # Number of ticks simulated
 final_tick                               5882580526000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 876676                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1365940                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1714420225                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 249312                       # Number of bytes of host memory used
-host_seconds                                  3431.24                       # Real time elapsed on the host
+host_inst_rate                                 833754                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1299064                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1630482633                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 251632                       # Number of bytes of host memory used
+host_seconds                                  3607.88                       # Real time elapsed on the host
 sim_insts                                  3008081022                       # Number of instructions simulated
 sim_ops                                    4686862596                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             43200                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         125326976                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            125370176                       # Number of bytes read from this memory
@@ -52,6 +54,8 @@
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
 system.membus.respLayer1.occupancy        17630181000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
 system.cpu.numCycles                      11765161052                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -86,6 +90,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   555.705054                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.271340                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.271340                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          665                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          632                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.324707                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        8026466441                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       8026466441                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst   4013232208                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total      4013232208                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst    4013232208                       # number of demand (read+write) hits
@@ -168,6 +178,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000783                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.479548                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.950203                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29783                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          996                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          743                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27921                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908905                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        106336271                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       106336271                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.data      6045911                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        6045911                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks      3697956                       # number of Writeback hits
@@ -299,6 +318,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  4084.587030                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997214                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997214                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          926                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2744                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          320                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses        3364538845                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       3364538845                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data   1231961896                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total      1231961896                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    436638511                       # number of WriteReq hits

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
index 8a34756..1a6e862 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini

@@ -120,6 +120,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -136,6 +137,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -158,6 +160,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -174,6 +177,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -183,6 +187,7 @@
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -204,6 +209,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -220,6 +226,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -246,7 +253,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr
index 1b49765..506aa6e 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr

@@ -3,4 +3,3 @@
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
index 27c876a..66d60ad 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout

@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:18:38
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 19:03:25
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -21,4 +23,4 @@
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 41671895000 because target called exit()
+122 123 124 Exiting @ tick 41680207000 because target called exit()

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
index 5f89f07..3f6e9d4 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                 41680207000                       # Number of ticks simulated
 final_tick                                41680207000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  93645                       # Simulator instruction rate (inst/s)
-host_op_rate                                    93645                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               42470141                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 279708                       # Number of bytes of host memory used
-host_seconds                                   981.40                       # Real time elapsed on the host
+host_inst_rate                                 131207                       # Simulator instruction rate (inst/s)
+host_op_rate                                   131207                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               59505524                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 234284                       # Number of bytes of host memory used
+host_seconds                                   700.44                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            178816                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            137216                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               316032                       # Number of bytes read from this memory
@@ -243,6 +245,7 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           45973500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                13412627                       # Number of BP lookups
 system.cpu.branchPred.condPredicted           9650146                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           4269214                       # Number of conditional branches incorrect
@@ -354,6 +357,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1492.182806                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.728605                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.728605                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1885                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          613                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          136                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          959                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.920410                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          19923420                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         19923420                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst      9945551                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total         9945551                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst       9945551                       # number of demand (read+write) hits
@@ -462,6 +474,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.055565                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.010711                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.066821                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3282                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          129                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          700                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          168                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2213                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.100159                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            99830                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           99830                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         6726                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           53                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           6779                       # number of ReadReq hits
@@ -594,6 +615,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  1441.367780                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.351896                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.351896                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2066                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           58                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          211                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          403                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1372                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.504395                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          52996825                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         52996825                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     19995621                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        19995621                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      6492829                       # number of WriteReq hits

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index 201e62f..78509c3 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini

@@ -159,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -504,6 +506,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -520,6 +523,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -529,6 +533,7 @@
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -550,6 +555,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -566,6 +572,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -592,7 +599,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
index 1b49765..506aa6e 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr

@@ -3,4 +3,3 @@
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
index 2fe61da..c12c73c 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout

@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 16 2013 01:34:33
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 19:15:16
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -21,4 +23,4 @@
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 23492267500 because target called exit()
+122 123 124 Exiting @ tick 23461709500 because target called exit()

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 4456924..b0acaf5 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                 23461709500                       # Number of ticks simulated
 final_tick                                23461709500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 127245                       # Simulator instruction rate (inst/s)
-host_op_rate                                   127245                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               35464472                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 280732                       # Number of bytes of host memory used
-host_seconds                                   661.56                       # Real time elapsed on the host
+host_inst_rate                                 186682                       # Simulator instruction rate (inst/s)
+host_op_rate                                   186682                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               52030153                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 235304                       # Number of bytes of host memory used
+host_seconds                                   450.93                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            195968                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            138624                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               334592                       # Number of bytes read from this memory
@@ -244,6 +246,7 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           49012250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                14847721                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          10774921                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            922205                       # Number of conditional branches incorrect
@@ -576,6 +579,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1596.482984                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.779533                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.779533                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1934                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          184                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          766                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          924                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.944336                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          29479830                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         29479830                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     14719872                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        14719872                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      14719872                       # number of demand (read+write) hits
@@ -664,6 +676,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061354                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.011641                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.073535                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3590                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          910                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2431                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.109558                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           116249                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          116249                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         8448                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           55                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           8503                       # number of ReadReq hits
@@ -796,6 +817,14 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  1459.152638                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.356238                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.356238                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2088                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          542                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1390                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.509766                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          56179001                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         56179001                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     21586035                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        21586035                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      6492869                       # number of WriteReq hits

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 04249e1..b06f5d8 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,26 @@
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +108,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +123,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +142,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +152,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr
index 1ed7969..506aa6e 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr

@@ -1,7 +1,5 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
index 5083775..53155af 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout

@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:32:22
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 19:22:57
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sav
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
index 31612b0..69d43d9 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                 45951567500                       # Number of ticks simulated
 final_tick                                45951567500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3944537                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3944535                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1972268010                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220188                       # Number of bytes of host memory used
-host_seconds                                    23.30                       # Real time elapsed on the host
+host_inst_rate                                2604589                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2604587                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1302294342                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224388                       # Number of bytes of host memory used
+host_seconds                                    35.29                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         367612356                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         108337521                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            475949877                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                  11030545389                       # Throughput (bytes/s)
 system.membus.data_through_bus              506870851                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 2ef8f23..3fa8979 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,23 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -147,6 +165,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +174,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +189,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +207,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +217,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+eventq_index=0
+executable=/dist/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +232,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +251,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +261,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr
index 1b49765..506aa6e 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr

@@ -3,4 +3,3 @@
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
index b809995..078852d 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout

@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 10:32:58
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 19:23:43
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.

diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
index be0605d..d8a9ee8 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                118729316000                       # Number of ticks simulated
 final_tick                               118729316000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2022504                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2022504                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2612866318                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228676                       # Number of bytes of host memory used
-host_seconds                                    45.44                       # Real time elapsed on the host
+host_inst_rate                                1382014                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1382013                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1785419086                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 233256                       # Number of bytes of host memory used
+host_seconds                                    66.50                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            167744                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            137216                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               304960                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           42885000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -106,6 +109,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1418.052773                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.692409                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.692409                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1829                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          223                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          585                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          953                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.893066                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         183814690                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        183814690                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     91894580                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        91894580                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      91894580                       # number of demand (read+write) hits
@@ -188,6 +200,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.052033                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.010720                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.063296                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3109                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          221                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          703                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2096                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.094879                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            91577                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           91577                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         5889                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           53                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           5942                       # number of ReadReq hits
@@ -320,6 +341,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  1442.043392                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.352061                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.352061                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2066                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          173                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          487                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1372                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.504395                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          52996825                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         52996825                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     19995723                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        19995723                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      6499355                       # number of WriteReq hits

diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index 90382fb..69c7d8e 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini

@@ -159,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -514,6 +516,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -530,6 +533,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,7 +632,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/dist/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
index 5ce7704..6ec0339 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout

@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:15:41
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 23:45:59
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
+Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
+Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -21,4 +23,4 @@
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 74201024500 because target called exit()
+122 123 124 Exiting @ tick 74219948500 because target called exit()

diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index ac21abc..3723ab1 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                 74219948500                       # Number of ticks simulated
 final_tick                                74219948500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  84730                       # Simulator instruction rate (inst/s)
-host_op_rate                                    92772                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               36497737                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 298520                       # Number of bytes of host memory used
-host_seconds                                  2033.55                       # Real time elapsed on the host
+host_inst_rate                                 133200                       # Simulator instruction rate (inst/s)
+host_op_rate                                   145842                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               57376166                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253176                       # Number of bytes of host memory used
+host_seconds                                  1293.57                       # Real time elapsed on the host
 sim_insts                                   172303021                       # Number of instructions simulated
 sim_ops                                     188656503                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            131072                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            111680                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               242752                       # Number of bytes read from this memory
@@ -237,6 +239,7 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           35532750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                94784274                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          74784006                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           6281562                       # Number of conditional branches incorrect
@@ -581,6 +584,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1347.740549                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.658076                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.658076                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1731                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          544                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           27                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1037                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.845215                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          73705913                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         73705913                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     36845557                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        36845557                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      36845557                       # number of demand (read+write) hits
@@ -669,6 +681,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.043505                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.016384                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.060042                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         2732                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           91                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          604                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3           28                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1970                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.083374                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            51779                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           51779                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         2073                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           88                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           2161                       # number of ReadReq hits
@@ -810,6 +831,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  1406.103135                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.343287                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.343287                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1795                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          353                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1378                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.438232                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          93593418                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         93593418                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     34384711                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        34384711                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     12356564                       # number of WriteReq hits

diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
index 46e3b79..0b27d47 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -75,21 +80,25 @@
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -108,18 +117,21 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -129,7 +141,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -143,11 +156,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -160,6 +175,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -169,5 +185,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
index debc939..3a7a720 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:16:29
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 23 2014 00:00:14
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
 Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav
 Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2

diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
index 24cdef3..c33d292 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                103106766000                       # Number of ticks simulated
 final_tick                               103106766000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2813934                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3080985                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1683727447                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236772                       # Number of bytes of host memory used
-host_seconds                                    61.24                       # Real time elapsed on the host
+host_inst_rate                                2018881                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2210479                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1208004529                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 241364                       # Number of bytes of host memory used
+host_seconds                                    85.35                       # Real time elapsed on the host
 sim_insts                                   172317409                       # Number of instructions simulated
 sim_ops                                     188670891                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         759440204                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         110533661                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            869973865                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                   8876496088                       # Throughput (bytes/s)
 system.membus.data_through_bus              915226805                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits

diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
index beab376..a68b7de 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,18 +100,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -115,6 +126,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -123,6 +135,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -137,14 +150,18 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -163,12 +180,14 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -179,6 +198,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -187,6 +207,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -201,12 +222,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -216,6 +240,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -225,7 +250,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
+eventq_index=0
+executable=/dist/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -239,11 +265,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -256,6 +284,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -265,5 +294,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
index 5593539..50f61b8 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 09:33:12
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 23 2014 00:01:50
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
 Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav
 Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2

diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index 3a3e9e5..daccb0e 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                232072304000                       # Number of ticks simulated
 final_tick                               232072304000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 705973                       # Simulator instruction rate (inst/s)
-host_op_rate                                   773116                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              953412259                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 242928                       # Number of bytes of host memory used
-host_seconds                                   243.41                       # Real time elapsed on the host
+host_inst_rate                                1248624                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1367377                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1686259354                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 250108                       # Number of bytes of host memory used
+host_seconds                                   137.63                       # Real time elapsed on the host
 sim_insts                                   171842483                       # Number of instructions simulated
 sim_ops                                     188185920                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            110656                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            110336                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               220992                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           31077000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -116,6 +119,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1147.986161                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.560540                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.560540                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1545                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          288                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          270                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          942                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.754395                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         379723155                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        379723155                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    189857001                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       189857001                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     189857001                       # number of demand (read+write) hits
@@ -198,6 +210,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.035676                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.015368                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.051137                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         2369                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          320                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          322                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1679                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.072296                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            42317                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           42317                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         1322                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           57                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           1379                       # number of ReadReq hits
@@ -330,6 +351,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  1363.611259                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.332913                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.332913                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1749                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           14                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          302                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1345                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.427002                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          84020083                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         84020083                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     29599357                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        29599357                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     12363187                       # number of WriteReq hits

diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index 4507117..ead3fce 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,25 @@
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +107,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+eventq_index=0
+executable=/dist/cpu2000/binaries/sparc/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +122,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +141,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +151,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
index 7edd901..1a4f967 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr

@@ -1,3 +1 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
index 1f1c88e..522507b 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:10:38
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:48:57
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
 Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav
 Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2

diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
index 806cadb..b414e15 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                 96722945000                       # Number of ticks simulated
 final_tick                                96722945000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3763101                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3763105                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1881563141                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229516                       # Number of bytes of host memory used
-host_seconds                                    51.41                       # Real time elapsed on the host
+host_inst_rate                                2588672                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2588674                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1294344494                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 233760                       # Number of bytes of host memory used
+host_seconds                                    74.73                       # Real time elapsed on the host
 sim_insts                                   193444518                       # Number of instructions simulated
 sim_ops                                     193444756                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst         773782140                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         223463413                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            997245553                       # Number of bytes read from this memory
@@ -38,6 +40,7 @@
 system.membus.throughput                  11057254439                       # Throughput (bytes/s)
 system.membus.data_through_bus             1069490213                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  401                       # Number of system calls
 system.cpu.numCycles                        193445891                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started

diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
index bac902c..5f60b57 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.l2cache]
@@ -147,6 +164,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +173,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +188,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +206,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +216,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+eventq_index=0
+executable=/dist/cpu2000/binaries/sparc/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +231,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +250,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +260,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
index 1393665..cbae3bd 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:08:55
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 19:50:23
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
 Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
 Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2

diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
index 471075d..4c0f0b4 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                270563082000                       # Number of ticks simulated
 final_tick                               270563082000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 872463                       # Simulator instruction rate (inst/s)
-host_op_rate                                   872464                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1220278409                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236504                       # Number of bytes of host memory used
-host_seconds                                   221.72                       # Real time elapsed on the host
+host_inst_rate                                1313314                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1313315                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1836878526                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 242660                       # Number of bytes of host memory used
+host_seconds                                   147.30                       # Real time elapsed on the host
 sim_insts                                   193444518                       # Number of instructions simulated
 sim_ops                                     193444756                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            230208                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            100864                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               331072                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           46557000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  401                       # Number of system calls
 system.cpu.numCycles                        541126164                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -74,6 +77,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1591.579171                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.777138                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.777138                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1926                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           50                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          624                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          514                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          687                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.940430                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         386903360                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        386903360                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    193433248                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       193433248                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     193433248                       # number of demand (read+write) hits
@@ -156,6 +168,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.069436                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.012300                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.081736                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4097                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           40                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          700                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          625                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2688                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.125031                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           116103                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          116103                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         8691                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           8691                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks            2                       # number of Writeback hits
@@ -283,6 +304,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  1237.203941                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.302052                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.302052                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1574                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0            5                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           39                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          271                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1237                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.384277                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         153469402                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        153469402                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     57734570                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        57734570                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     18975362                       # number of WriteReq hits

diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
index 210f89c..e8d7fb6 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini

@@ -165,6 +165,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -181,6 +182,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -520,6 +522,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -536,6 +539,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -584,6 +588,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -600,6 +605,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -626,7 +632,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/dist/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
index 6074206..1e66bd9 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout

@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:39:37
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 21:43:52
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -22,4 +24,4 @@
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 144337151000 because target called exit()
+122 123 124 Exiting @ tick 144463317000 because target called exit()

diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index 3f8722e..1427887 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                144463317000                       # Number of ticks simulated
 final_tick                               144463317000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  55445                       # Simulator instruction rate (inst/s)
-host_op_rate                                    92931                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               60647702                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 328672                       # Number of bytes of host memory used
-host_seconds                                  2382.01                       # Real time elapsed on the host
+host_inst_rate                                  81167                       # Simulator instruction rate (inst/s)
+host_op_rate                                   136043                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               88782348                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 282908                       # Number of bytes of host memory used
+host_seconds                                  1627.16                       # Real time elapsed on the host
 sim_insts                                   132071192                       # Number of instructions simulated
 sim_ops                                     221363384                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            217088                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            125568                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               342656                       # Number of bytes read from this memory
@@ -251,6 +253,7 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           50662837                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                18648233                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          18648233                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           1490176                       # Number of conditional branches incorrect
@@ -260,6 +263,7 @@
 system.cpu.branchPred.BTBHitPct             94.591126                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                 1320367                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect              22841                       # Number of incorrect RAS predictions.
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
 system.cpu.numCycles                        289221873                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -552,6 +556,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1619.938452                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.790986                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.790986                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1967                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          185                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          767                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          122                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          797                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.960449                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          44713203                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         44713203                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     22344300                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        22344300                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      22344300                       # number of demand (read+write) hits
@@ -640,6 +653,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.068064                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.009517                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.077634                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3826                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          194                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          876                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          145                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2560                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.116760                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            75773                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           75773                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         3227                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           36                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           3263                       # number of ReadReq hits
@@ -786,6 +808,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  1438.861304                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.351284                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.351284                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1947                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           70                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          432                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1395                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.475342                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         132211530                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        132211530                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     45588097                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        45588097                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     20514029                       # number of WriteReq hits

diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
index a8660b2..4ce0c43 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -76,16 +81,19 @@
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[4]
@@ -93,6 +101,7 @@
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -103,22 +112,26 @@
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -128,7 +141,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+eventq_index=0
+executable=/dist/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -142,11 +156,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -159,6 +175,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -168,5 +185,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
index 61953e3..45d32ca 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout

@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:46:06
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 22:11:10
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 

diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
index 3063054..bc7c540 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                131393279000                       # Number of ticks simulated
 final_tick                               131393279000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1210449                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2028822                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1204235272                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 265804                       # Number of bytes of host memory used
-host_seconds                                   109.11                       # Real time elapsed on the host
+host_inst_rate                                1414135                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2370219                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1406875667                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 267896                       # Number of bytes of host memory used
+host_seconds                                    93.39                       # Real time elapsed on the host
 sim_insts                                   132071193                       # Number of instructions simulated
 sim_ops                                     221363385                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst        1387954936                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         310423752                       # Number of bytes read from this memory
 system.physmem.bytes_read::total           1698378688                       # Number of bytes read from this memory
@@ -36,6 +38,8 @@
 system.membus.throughput                  13685638205                       # Throughput (bytes/s)
 system.membus.data_through_bus             1798200879                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
 system.cpu.numCycles                        262786559                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started

diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
index 00a43a1..b3c95de 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -69,6 +74,7 @@
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dcache]
 type=BaseCache
@@ -76,6 +82,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -84,6 +91,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -98,18 +106,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
@@ -120,6 +132,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -128,6 +141,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -142,12 +156,15 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -158,16 +175,19 @@
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
@@ -178,6 +198,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -186,6 +207,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -200,12 +222,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -215,6 +240,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -224,7 +250,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
+eventq_index=0
+executable=/dist/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -238,11 +265,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -255,6 +284,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -264,5 +294,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
index b436e7f..cc37865 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout

@@ -1,10 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:51:48
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 22:12:53
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 

diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
index 9cfd1bb..2eac3bb 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                250953957000                       # Number of ticks simulated
 final_tick                               250953957000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 789102                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1322606                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1499404446                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 274284                       # Number of bytes of host memory used
-host_seconds                                   167.37                       # Real time elapsed on the host
+host_inst_rate                                 770398                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1291257                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1463865173                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 276604                       # Number of bytes of host memory used
+host_seconds                                   171.43                       # Real time elapsed on the host
 sim_insts                                   132071193                       # Number of instructions simulated
 sim_ops                                     221363385                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            181760                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            121280                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               303040                       # Number of bytes read from this memory
@@ -44,6 +46,8 @@
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy           42633500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
 system.cpu.numCycles                        501907914                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -78,6 +82,15 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst  1455.296642                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.710594                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.710594                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1858                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           60                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          498                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          394                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          869                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.907227                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         346993430                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        346993430                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    173489674                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       173489674                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     173489674                       # number of demand (read+write) hits
@@ -160,6 +173,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.055847                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.006963                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.062811                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3164                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          513                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          516                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2064                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.096558                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            57590                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           57590                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst         1854                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data            7                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total           1861                       # number of ReadReq hits
@@ -292,6 +314,15 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data  1363.457571                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.332875                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.332875                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1864                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0            8                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           13                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           44                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          471                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1328                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.455078                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         154397377                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        154397377                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     56681678                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        56681678                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     20514153                       # number of WriteReq hits

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 730b05e..982acdd 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini

@@ -15,16 +15,16 @@
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+pal=/dist/binaries/ts_osfpal
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -108,6 +108,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.dcache.tags
@@ -124,6 +125,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.dtb]
@@ -146,6 +148,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.icache.tags
@@ -162,6 +165,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.interrupts]
@@ -171,6 +175,7 @@
 [system.cpu0.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu0.itb]
 type=AlphaTLB
@@ -234,6 +239,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.dcache.tags
@@ -250,6 +256,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.dtb]
@@ -272,6 +279,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.icache.tags
@@ -288,6 +296,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.interrupts]
@@ -297,6 +306,7 @@
 [system.cpu1.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu1.itb]
 type=AlphaTLB
@@ -333,7 +343,7 @@
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -356,7 +366,7 @@
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -390,6 +400,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -406,6 +417,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.l2c]
@@ -423,6 +435,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.l2c.tags
@@ -439,6 +452,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.membus]
@@ -495,7 +509,7 @@
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
index 0bcb6e8..20fe2d6 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr

@@ -2,4 +2,3 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index 4103513..3fdb0e0 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout

@@ -1,15 +1,13 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:50
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:41
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 97861500
-Exiting @ tick 1870335643500 because m5_exit instruction encountered
+Exiting @ tick 1870335522500 because m5_exit instruction encountered

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index e7342cf..42e3976 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                1870335522500                       # Number of ticks simulated
 final_tick                               1870335522500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1806360                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1806359                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            53496127424                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 353980                       # Number of bytes of host memory used
-host_seconds                                    34.96                       # Real time elapsed on the host
+host_inst_rate                                3158607                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3158605                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            93543458564                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309852                       # Number of bytes of host memory used
+host_seconds                                    19.99                       # Real time elapsed on the host
 sim_insts                                    63154034                       # Number of instructions simulated
 sim_ops                                      63154034                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.inst           761216                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data         66693056                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2649600                       # Number of bytes read from this memory
@@ -51,6 +53,7 @@
 system.membus.throughput                     42160248                       # Throughput (bytes/s)
 system.membus.data_through_bus               78853810                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                  1000626                       # number of replacements
 system.l2c.tags.tagsinuse                65381.922680                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    2464737                       # Total number of references to valid blocks.
@@ -68,6 +71,15 @@
 system.l2c.tags.occ_percent::cpu1.inst       0.002661                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.000305                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.997649                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        65142                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          769                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1         3264                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         6912                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6232                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        47965                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.993988                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 32109442                       # Number of tag accesses
+system.l2c.tags.data_accesses                32109442                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.inst             873086                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.data             763077                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.inst             101896                       # number of ReadReq hits
@@ -188,6 +200,11 @@
 system.iocache.tags.occ_blocks::tsunami.ide     0.435437                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::tsunami.ide     0.027215                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.027215                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               375543                       # Number of tag accesses
+system.iocache.tags.data_accesses              375543                       # Number of data accesses
 system.iocache.ReadReq_misses::tsunami.ide          175                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -424,6 +441,13 @@
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.244754                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998525                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.998525                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           59                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          345                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses         58115132                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        58115132                       # Number of data accesses
 system.cpu0.icache.ReadReq_hits::cpu0.inst     56345132                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total       56345132                       # number of ReadReq hits
 system.cpu0.icache.demand_hits::cpu0.inst     56345132                       # number of demand (read+write) hits
@@ -466,6 +490,13 @@
 system.cpu0.dcache.tags.occ_blocks::cpu0.data   507.129778                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.990488                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.990488                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          443                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         62404072                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        62404072                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data      7298337                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total        7298337                       # number of ReadReq hits
 system.cpu0.dcache.WriteReq_hits::cpu0.data      5462263                       # number of WriteReq hits
@@ -661,6 +692,11 @@
 system.cpu1.icache.tags.occ_blocks::cpu1.inst   427.126317                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.834231                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.834231                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses          6039396                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         6039396                       # Number of data accesses
 system.cpu1.icache.ReadReq_hits::cpu1.inst      5832136                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total        5832136                       # number of ReadReq hits
 system.cpu1.icache.demand_hits::cpu1.inst      5832136                       # number of demand (read+write) hits
@@ -703,6 +739,12 @@
 system.cpu1.dcache.tags.occ_blocks::cpu1.data   421.562730                       # Average occupied blocks per requestor
 system.cpu1.dcache.tags.occ_percent::cpu1.data     0.823365                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_percent::total     0.823365                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          338                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          337                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.660156                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses          7735310                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses         7735310                       # Number of data accesses
 system.cpu1.dcache.ReadReq_hits::cpu1.data      1109521                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total        1109521                       # number of ReadReq hits
 system.cpu1.dcache.WriteReq_hits::cpu1.data       707457                       # number of WriteReq hits

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 7f56b64..b586add 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini

@@ -15,16 +15,16 @@
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+pal=/dist/binaries/ts_osfpal
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -108,6 +108,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.dcache.tags
@@ -124,6 +125,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.dtb]
@@ -146,6 +148,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.icache.tags
@@ -162,6 +165,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.interrupts]
@@ -171,6 +175,7 @@
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -192,6 +197,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.cpu.l2cache.tags
@@ -208,6 +214,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.cpu.toL2Bus]
@@ -251,7 +258,7 @@
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -274,7 +281,7 @@
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -308,6 +315,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -324,6 +332,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.membus]
@@ -380,7 +389,7 @@
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
index 0bcb6e8..20fe2d6 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr

@@ -2,4 +2,3 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index b63c77b..142ae35 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout

@@ -1,14 +1,12 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:50
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:41
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1829332269000 because m5_exit instruction encountered
+Exiting @ tick 1829332258000 because m5_exit instruction encountered

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 01a0692..2043677 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                1829332258000                       # Number of ticks simulated
 final_tick                               1829332258000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1538182                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1538181                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            46867449524                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 350908                       # Number of bytes of host memory used
-host_seconds                                    39.03                       # Real time elapsed on the host
+host_inst_rate                                3003513                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3003511                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            91515177007                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 306744                       # Number of bytes of host memory used
+host_seconds                                    19.99                       # Real time elapsed on the host
 sim_insts                                    60038305                       # Number of instructions simulated
 sim_ops                                      60038305                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            857984                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          66839424                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
@@ -50,6 +52,11 @@
 system.iocache.tags.occ_blocks::tsunami.ide     1.225570                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::tsunami.ide     0.076598                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.076598                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               375534                       # Number of tag accesses
+system.iocache.tags.data_accesses              375534                       # Number of data accesses
 system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -97,6 +104,7 @@
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -278,6 +286,13 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   511.215243                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.998467                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.998467                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          332                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          60970364                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         60970364                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     59129922                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        59129922                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      59129922                       # number of demand (read+write) hits
@@ -324,6 +339,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.074270                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.064818                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.998297                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65163                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          781                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3260                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4024                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3055                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54043                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         31737437                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        31737437                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst       906797                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       811229                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1718026                       # number of ReadReq hits
@@ -400,6 +424,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.997802                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999996                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          443                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          66369799                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         66369799                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data      7807780                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total         7807780                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      5848212                       # number of WriteReq hits

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index c1c2c44..87138f3 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini

@@ -15,16 +15,16 @@
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
 eventq_index=0
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+pal=/dist/binaries/ts_osfpal
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -101,6 +101,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.dcache.tags
@@ -117,6 +118,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.dtb]
@@ -139,6 +141,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.icache.tags
@@ -155,6 +158,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.interrupts]
@@ -164,6 +168,7 @@
 [system.cpu0.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu0.itb]
 type=AlphaTLB
@@ -220,6 +225,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.dcache.tags
@@ -236,6 +242,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.dtb]
@@ -258,6 +265,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.icache.tags
@@ -274,6 +282,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.interrupts]
@@ -283,6 +292,7 @@
 [system.cpu1.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu1.itb]
 type=AlphaTLB
@@ -319,7 +329,7 @@
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -342,7 +352,7 @@
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -376,6 +386,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -392,6 +403,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.l2c]
@@ -409,6 +421,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.l2c.tags
@@ -425,6 +438,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.membus]
@@ -505,7 +519,7 @@
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
index 0bcb6e8..20fe2d6 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr

@@ -2,4 +2,3 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index a33dd38..2d1ba2c 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout

@@ -1,15 +1,13 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:51
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:25:12
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 675287000
-Exiting @ tick 1961841175000 because m5_exit instruction encountered
+info: Launching CPU 1 @ 688618000
+Exiting @ tick 1960909874500 because m5_exit instruction encountered

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 8b5007c..46997f6 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                1960909874500                       # Number of ticks simulated
 final_tick                               1960909874500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 787846                       # Simulator instruction rate (inst/s)
-host_op_rate                                   787845                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            25353578812                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 353976                       # Number of bytes of host memory used
-host_seconds                                    77.34                       # Real time elapsed on the host
+host_inst_rate                                1305982                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1305981                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            42027651646                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309852                       # Number of bytes of host memory used
+host_seconds                                    46.66                       # Real time elapsed on the host
 sim_insts                                    60933947                       # Number of instructions simulated
 sim_ops                                      60933947                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.inst           833472                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data         24887104                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2650688                       # Number of bytes read from this memory
@@ -416,6 +418,7 @@
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 system.membus.respLayer2.occupancy          376315500                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                   342160                       # number of replacements
 system.l2c.tags.tagsinuse                65219.945305                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    2443226                       # Total number of references to valid blocks.
@@ -433,6 +436,15 @@
 system.l2c.tags.occ_percent::cpu1.inst       0.002426                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.000675                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.995177                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        65187                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          761                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         5186                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         7242                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        51881                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.994675                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 25932224                       # Number of tag accesses
+system.l2c.tags.data_accesses                25932224                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.inst             684719                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.data             664525                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.inst             317383                       # number of ReadReq hits
@@ -724,6 +736,11 @@
 system.iocache.tags.occ_blocks::tsunami.ide     0.570482                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::tsunami.ide     0.035655                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.035655                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               375534                       # Number of tag accesses
+system.iocache.tags.data_accesses              375534                       # Number of data accesses
 system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -1105,6 +1122,14 @@
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.398756                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992966                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.992966                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses         48690501                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        48690501                       # Number of data accesses
 system.cpu0.icache.ReadReq_hits::cpu0.inst     47294969                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total       47294969                       # number of ReadReq hits
 system.cpu0.icache.demand_hits::cpu0.inst     47294969                       # number of demand (read+write) hits
@@ -1183,6 +1208,13 @@
 system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.271614                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986859                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.986859                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          318                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         51851796                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        51851796                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data      6451735                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total        6451735                       # number of ReadReq hits
 system.cpu0.dcache.WriteReq_hits::cpu0.data      4706856                       # number of WriteReq hits
@@ -1461,6 +1493,12 @@
 system.cpu1.icache.tags.occ_blocks::cpu1.inst   446.450379                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.871973                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.871973                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           72                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3          439                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses         13271059                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        13271059                       # Number of data accesses
 system.cpu1.icache.ReadReq_hits::cpu1.inst     12635285                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total       12635285                       # number of ReadReq hits
 system.cpu1.icache.demand_hits::cpu1.inst     12635285                       # number of demand (read+write) hits
@@ -1539,6 +1577,12 @@
 system.cpu1.dcache.tags.occ_blocks::cpu1.data   485.752776                       # Average occupied blocks per requestor
 system.cpu1.dcache.tags.occ_percent::cpu1.data     0.948736                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_percent::total     0.948736                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          326                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           31                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3          295                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.636719                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         16587420                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        16587420                       # Number of data accesses
 system.cpu1.dcache.ReadReq_hits::cpu1.data      2220669                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total        2220669                       # number of ReadReq hits
 system.cpu1.dcache.WriteReq_hits::cpu1.data      1595283                       # number of WriteReq hits

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 54bf6e9..161fac4 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=true
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -13,15 +15,16 @@
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/dist/m5/system/binaries/console
+console=/dist/binaries/console
+eventq_index=0
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/dist/binaries/ts_osfpal
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -39,6 +42,7 @@
 type=Bridge
 clk_domain=system.clk_domain
 delay=50000
+eventq_index=0
 ranges=8796093022208:18446744073709551615
 req_size=16
 resp_size=16
@@ -48,6 +52,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -60,6 +65,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -86,6 +92,7 @@
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -94,6 +101,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.dcache.tags
@@ -108,11 +116,14 @@
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -121,6 +132,7 @@
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -129,6 +141,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.icache.tags
@@ -143,17 +156,23 @@
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -162,6 +181,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -170,6 +190,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.cpu.l2cache.tags
@@ -184,12 +205,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -199,10 +223,12 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.disk0]
@@ -210,19 +236,22 @@
 children=image
 delay=1000000
 driveID=master
+eventq_index=0
 image=system.disk0.image
 
 [system.disk0.image]
 type=CowDiskImage
 children=child
 child=system.disk0.image.child
+eventq_index=0
 image_file=
 read_only=false
 table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+eventq_index=0
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -230,28 +259,33 @@
 children=image
 delay=1000000
 driveID=master
+eventq_index=0
 image=system.disk2.image
 
 [system.disk2.image]
 type=CowDiskImage
 children=child
 child=system.disk2.image.child
+eventq_index=0
 image_file=
 read_only=false
 table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+eventq_index=0
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
 type=IntrControl
+eventq_index=0
 sys=system
 
 [system.iobus]
 type=NoncoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 use_default_range=true
 width=8
@@ -265,6 +299,7 @@
 addr_ranges=0:134217727
 assoc=8
 clk_domain=system.clk_domain
+eventq_index=0
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -273,6 +308,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -287,13 +323,16 @@
 assoc=8
 block_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -305,6 +344,7 @@
 [system.membus.badaddr_responder]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -331,6 +371,7 @@
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -342,29 +383,35 @@
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[1]
 
 [system.simple_disk]
 type=SimpleDisk
 children=disk
 disk=system.simple_disk.disk
+eventq_index=0
 system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+eventq_index=0
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
 type=Terminal
+eventq_index=0
 intr_control=system.intrctrl
 number=0
 output=true
@@ -373,6 +420,7 @@
 [system.tsunami]
 type=Tsunami
 children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+eventq_index=0
 intrctrl=system.intrctrl
 system=system
 
@@ -381,6 +429,7 @@
 clk_domain=system.clk_domain
 cpu=system.cpu
 disk=system.simple_disk
+eventq_index=0
 pio_addr=8804682956800
 pio_latency=100000
 platform=system.tsunami
@@ -391,6 +440,7 @@
 [system.tsunami.cchip]
 type=TsunamiCChip
 clk_domain=system.clk_domain
+eventq_index=0
 pio_addr=8803072344064
 pio_latency=100000
 system=system
@@ -419,6 +469,7 @@
 BAR5Size=0
 BIST=0
 CacheLineSize=0
+CapabilityPtr=0
 CardbusCIS=0
 ClassCode=2
 Command=0
@@ -428,8 +479,40 @@
 InterruptLine=30
 InterruptPin=1
 LatencyTimer=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
 MaximumLatency=52
 MinimumGrant=176
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
 ProgIF=0
 Revision=0
 Status=656
@@ -446,6 +529,7 @@
 dma_read_factor=0
 dma_write_delay=0
 dma_write_factor=0
+eventq_index=0
 hardware_address=00:90:00:00:00:01
 intr_delay=10000000
 pci_bus=0
@@ -469,6 +553,7 @@
 [system.tsunami.fake_OROM]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8796093677568
 pio_latency=100000
@@ -486,6 +571,7 @@
 [system.tsunami.fake_ata0]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848432
 pio_latency=100000
@@ -503,6 +589,7 @@
 [system.tsunami.fake_ata1]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848304
 pio_latency=100000
@@ -520,6 +607,7 @@
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848569
 pio_latency=100000
@@ -537,6 +625,7 @@
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848451
 pio_latency=100000
@@ -554,6 +643,7 @@
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848515
 pio_latency=100000
@@ -571,6 +661,7 @@
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848579
 pio_latency=100000
@@ -588,6 +679,7 @@
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848643
 pio_latency=100000
@@ -605,6 +697,7 @@
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848707
 pio_latency=100000
@@ -622,6 +715,7 @@
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848771
 pio_latency=100000
@@ -639,6 +733,7 @@
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848835
 pio_latency=100000
@@ -656,6 +751,7 @@
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848899
 pio_latency=100000
@@ -673,6 +769,7 @@
 [system.tsunami.fake_pnp_write]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615850617
 pio_latency=100000
@@ -690,6 +787,7 @@
 [system.tsunami.fake_ppc]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848891
 pio_latency=100000
@@ -707,6 +805,7 @@
 [system.tsunami.fake_sm_chip]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848816
 pio_latency=100000
@@ -724,6 +823,7 @@
 [system.tsunami.fake_uart1]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848696
 pio_latency=100000
@@ -741,6 +841,7 @@
 [system.tsunami.fake_uart2]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848936
 pio_latency=100000
@@ -758,6 +859,7 @@
 [system.tsunami.fake_uart3]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848680
 pio_latency=100000
@@ -775,6 +877,7 @@
 [system.tsunami.fake_uart4]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848944
 pio_latency=100000
@@ -793,6 +896,7 @@
 type=BadDevice
 clk_domain=system.clk_domain
 devicename=FrameBuffer
+eventq_index=0
 pio_addr=8804615848912
 pio_latency=100000
 system=system
@@ -820,6 +924,7 @@
 BAR5Size=0
 BIST=0
 CacheLineSize=0
+CapabilityPtr=0
 CardbusCIS=0
 ClassCode=1
 Command=0
@@ -829,8 +934,40 @@
 InterruptLine=31
 InterruptPin=1
 LatencyTimer=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
 MaximumLatency=0
 MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
 ProgIF=133
 Revision=0
 Status=640
@@ -842,6 +979,7 @@
 config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
+eventq_index=0
 io_shift=0
 pci_bus=0
 pci_dev=0
@@ -856,6 +994,7 @@
 [system.tsunami.io]
 type=TsunamiIO
 clk_domain=system.clk_domain
+eventq_index=0
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=100000
@@ -868,6 +1007,7 @@
 [system.tsunami.pchip]
 type=TsunamiPChip
 clk_domain=system.clk_domain
+eventq_index=0
 pio_addr=8802535473152
 pio_latency=100000
 system=system
@@ -878,6 +1018,7 @@
 type=PciConfigAll
 bus=0
 clk_domain=system.clk_domain
+eventq_index=0
 pio_addr=0
 pio_latency=30000
 platform=system.tsunami
@@ -888,6 +1029,7 @@
 [system.tsunami.uart]
 type=Uart8250
 clk_domain=system.clk_domain
+eventq_index=0
 pio_addr=8804615848952
 pio_latency=100000
 platform=system.tsunami
@@ -897,5 +1039,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
index 0bcb6e8..20fe2d6 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr

@@ -2,4 +2,3 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
-hack: be nice to actually delete the event here

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index cabc90a..fa5fb8a 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout

@@ -1,14 +1,12 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:50
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:48
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /dist/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1918473094000 because m5_exit instruction encountered
+Exiting @ tick 1920428041000 because m5_exit instruction encountered

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 479e1f7..01b0606 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                1920428041000                       # Number of ticks simulated
 final_tick                               1920428041000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1218375                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1218374                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            41646226437                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 305884                       # Number of bytes of host memory used
-host_seconds                                    46.11                       # Real time elapsed on the host
+host_inst_rate                                1405906                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1405905                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            48056353161                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 307800                       # Number of bytes of host memory used
+host_seconds                                    39.96                       # Real time elapsed on the host
 sim_insts                                    56182750                       # Number of instructions simulated
 sim_ops                                      56182750                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            850688                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          24846912                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
@@ -414,6 +416,11 @@
 system.iocache.tags.occ_blocks::tsunami.ide     1.352288                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::tsunami.ide     0.084518                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.084518                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               375525                       # Number of tag accesses
+system.iocache.tags.data_accesses              375525                       # Number of data accesses
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -509,6 +516,7 @@
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -756,6 +764,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   508.321671                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.992816                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.992816                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          438                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          57123599                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         57123599                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     55265541                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        55265541                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      55265541                       # number of demand (read+write) hits
@@ -838,6 +854,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.072615                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.075609                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.996351                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1050                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4896                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3257                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55781                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         25947571                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        25947571                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst       915717                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       814814                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1730531                       # number of ReadReq hits
@@ -1004,6 +1029,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.978915                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999959                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999959                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          187                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          63152102                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63152102                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data      7814622                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total         7814622                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      5852326                       # number of WriteReq hits

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index db7088f..894acec 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini

@@ -12,7 +12,7 @@
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -23,7 +23,7 @@
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
@@ -75,7 +75,7 @@
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-arm-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -137,6 +137,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.dcache.tags
@@ -153,6 +154,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.dtb]
@@ -185,6 +187,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.icache.tags
@@ -201,6 +204,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.interrupts]
@@ -297,6 +301,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.dcache.tags
@@ -313,6 +318,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.dtb]
@@ -345,6 +351,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.icache.tags
@@ -361,6 +368,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.interrupts]
@@ -440,6 +448,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -456,6 +465,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.l2c]
@@ -473,6 +483,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.l2c.tags
@@ -489,6 +500,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.membus]

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
index 4ccac5e..5a43c8b 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr

@@ -1,7 +1,6 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
-warn: DTB file specified, but no device tree support in kernel
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
@@ -15,4 +14,3 @@
 warn: LCD dual screen mode not supported
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr icialluis' unimplemented
-hack: be nice to actually delete the event here

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
index 789ceb6..1e25209 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout

@@ -1,14 +1,12 @@
-Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual/simout
-Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 09:04:45
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 17:30:53
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 912096763500 because m5_exit instruction encountered

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index 622f0da..eb8ceda 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                912096763500                       # Number of ticks simulated
 final_tick                               912096763500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1031681                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1328287                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            15269405009                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 443324                       # Number of bytes of host memory used
-host_seconds                                    59.73                       # Real time elapsed on the host
+host_inst_rate                                1859152                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2393654                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            27516397451                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 399324                       # Number of bytes of host memory used
+host_seconds                                    33.15                       # Real time elapsed on the host
 sim_insts                                    61625970                       # Number of instructions simulated
 sim_ops                                      79343340                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd     39321600                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
@@ -87,6 +89,7 @@
 system.membus.throughput                     64986577                       # Throughput (bytes/s)
 system.membus.data_through_bus               59274047                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                    70658                       # number of replacements
 system.l2c.tags.tagsinuse                51560.149653                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    1623339                       # Total number of references to valid blocks.
@@ -110,6 +113,19 @@
 system.l2c.tags.occ_percent::cpu1.inst       0.032447                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.050521                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.786745                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65148                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          203                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3771                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3        12549                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        48575                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.994080                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 16906854                       # Number of tag accesses
+system.l2c.tags.data_accesses                16906854                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.dtb.walker         3874                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.itb.walker         1919                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.inst             421038                       # number of ReadReq hits
@@ -349,6 +365,12 @@
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.015216                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998077                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.998077                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          508                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses         30669233                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        30669233                       # Number of data accesses
 system.cpu0.icache.ReadReq_hits::cpu0.inst     29811115                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total       29811115                       # number of ReadReq hits
 system.cpu0.icache.demand_hits::cpu0.inst     29811115                       # number of demand (read+write) hits
@@ -391,6 +413,11 @@
 system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.763091                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.966334                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.966334                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          372                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          372                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.726562                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         51675155                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        51675155                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data      6512305                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total        6512305                       # number of ReadReq hits
 system.cpu0.dcache.WriteReq_hits::cpu0.data      5630881                       # number of WriteReq hits
@@ -409,8 +436,8 @@
 system.cpu0.dcache.WriteReq_misses::total       167342                       # number of WriteReq misses
 system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9062                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_misses::total         9062                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7469                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7469                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7466                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7466                       # number of StoreCondReq misses
 system.cpu0.dcache.demand_misses::cpu0.data       364509                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_misses::total        364509                       # number of demand (read+write) misses
 system.cpu0.dcache.overall_misses::cpu0.data       364509                       # number of overall misses
@@ -421,8 +448,8 @@
 system.cpu0.dcache.WriteReq_accesses::total      5798223                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       160681                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::total       160681                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       160649                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       160649                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       160646                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       160646                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.demand_accesses::cpu0.data     12507695                       # number of demand (read+write) accesses
 system.cpu0.dcache.demand_accesses::total     12507695                       # number of demand (read+write) accesses
 system.cpu0.dcache.overall_accesses::cpu0.data     12507695                       # number of overall (read+write) accesses
@@ -433,8 +460,8 @@
 system.cpu0.dcache.WriteReq_miss_rate::total     0.028861                       # miss rate for WriteReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.056397                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.056397                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.046493                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.046493                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.046475                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.046475                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029143                       # miss rate for demand accesses
 system.cpu0.dcache.demand_miss_rate::total     0.029143                       # miss rate for demand accesses
 system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029143                       # miss rate for overall accesses
@@ -525,6 +552,14 @@
 system.cpu1.icache.tags.occ_blocks::cpu1.inst   475.447912                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.928609                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.928609                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          261                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           20                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses         32848033                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        32848033                       # Number of data accesses
 system.cpu1.icache.ReadReq_hits::cpu1.inst     31979125                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total       31979125                       # number of ReadReq hits
 system.cpu1.icache.demand_hits::cpu1.inst     31979125                       # number of demand (read+write) hits
@@ -567,6 +602,14 @@
 system.cpu1.dcache.tags.occ_blocks::cpu1.data   447.573682                       # Average occupied blocks per requestor
 system.cpu1.dcache.tags.occ_percent::cpu1.data     0.874167                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_percent::total     0.874167                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          267                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          226                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         48417680                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        48417680                       # Number of data accesses
 system.cpu1.dcache.ReadReq_hits::cpu1.data      7002209                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total        7002209                       # number of ReadReq hits
 system.cpu1.dcache.WriteReq_hits::cpu1.data      4520313                       # number of WriteReq hits
@@ -585,8 +628,8 @@
 system.cpu1.dcache.WriteReq_misses::total       125920                       # number of WriteReq misses
 system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11251                       # number of LoadLockedReq misses
 system.cpu1.dcache.LoadLockedReq_misses::total        11251                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10139                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10139                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10133                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        10133                       # number of StoreCondReq misses
 system.cpu1.dcache.demand_misses::cpu1.data       324195                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_misses::total        324195                       # number of demand (read+write) misses
 system.cpu1.dcache.overall_misses::cpu1.data       324195                       # number of overall misses
@@ -597,8 +640,8 @@
 system.cpu1.dcache.WriteReq_accesses::total      4646233                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        89205                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::total        89205                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        89169                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        89169                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        89163                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        89163                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.demand_accesses::cpu1.data     11846717                       # number of demand (read+write) accesses
 system.cpu1.dcache.demand_accesses::total     11846717                       # number of demand (read+write) accesses
 system.cpu1.dcache.overall_accesses::cpu1.data     11846717                       # number of overall (read+write) accesses
@@ -609,8 +652,8 @@
 system.cpu1.dcache.WriteReq_miss_rate::total     0.027102                       # miss rate for WriteReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.126125                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.126125                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.113705                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.113705                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.113646                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.113646                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027366                       # miss rate for demand accesses
 system.cpu1.dcache.demand_miss_rate::total     0.027366                       # miss rate for demand accesses
 system.cpu1.dcache.overall_miss_rate::cpu1.data     0.027366                       # miss rate for overall accesses
@@ -632,6 +675,8 @@
 system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
+system.iocache.tags.data_accesses                   0                       # Number of data accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 196c328..ab338ac 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini

@@ -12,7 +12,7 @@
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -23,7 +23,7 @@
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
@@ -75,7 +75,7 @@
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-arm-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -137,6 +137,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.dcache.tags
@@ -153,6 +154,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.dtb]
@@ -185,6 +187,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.icache.tags
@@ -201,6 +204,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.interrupts]
@@ -255,6 +259,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.cpu.l2cache.tags
@@ -271,6 +276,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.cpu.toL2Bus]
@@ -324,6 +330,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -340,6 +347,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.membus]

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
index eda827f..4174229 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr

@@ -1,7 +1,6 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
-warn: DTB file specified, but no device tree support in kernel
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
@@ -14,4 +13,3 @@
 warn: LCD dual screen mode not supported
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr bpiallis' unimplemented
-hack: be nice to actually delete the event here

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index 0ff7b53..8105d53 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout

@@ -1,14 +1,12 @@
-Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:30:49
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 17:30:43
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2332810264000 because m5_exit instruction encountered

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index cb6c51d..0b833a7 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                2332810264000                       # Number of ticks simulated
 final_tick                               2332810264000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 993135                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1277110                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            38352024586                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 443324                       # Number of bytes of host memory used
-host_seconds                                    60.83                       # Real time elapsed on the host
+host_inst_rate                                1656319                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2129924                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            63962280307                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 398176                       # Number of bytes of host memory used
+host_seconds                                    36.47                       # Real time elapsed on the host
 sim_insts                                    60408639                       # Number of instructions simulated
 sim_ops                                      77681819                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    111673344                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          192                       # Number of bytes read from this memory
@@ -72,6 +74,7 @@
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.iobus.throughput                      48895252                       # Throughput (bytes/s)
 system.iobus.data_through_bus               114063346                       # Total data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                     14971214                       # DTB read hits
@@ -147,6 +150,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   511.678593                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999372                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999372                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           78                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          255                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          62285702                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         62285702                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     60583498                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        60583498                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      60583498                       # number of demand (read+write) hits
@@ -197,6 +208,18 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.107036                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.092911                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.763050                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65380                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3589                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         9187                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        52388                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997620                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         17035899                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        17035899                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7507                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3129                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.inst       838871                       # number of ReadReq hits
@@ -297,6 +320,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.997031                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          278                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          97632617                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         97632617                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     13180066                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        13180066                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      9962072                       # number of WriteReq hits
@@ -361,6 +391,8 @@
 system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
+system.iocache.tags.data_accesses                   0                       # Number of data accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index 051cf58..da0c44a 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini

@@ -12,7 +12,7 @@
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -23,7 +23,7 @@
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
@@ -75,7 +75,7 @@
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-arm-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -130,6 +130,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.dcache.tags
@@ -146,6 +147,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.dtb]
@@ -178,6 +180,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.icache.tags
@@ -194,6 +197,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.interrupts]
@@ -283,6 +287,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.dcache.tags
@@ -299,6 +304,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.dtb]
@@ -331,6 +337,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.icache.tags
@@ -347,6 +354,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.interrupts]
@@ -426,6 +434,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -442,6 +451,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.l2c]
@@ -459,6 +469,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.l2c.tags
@@ -475,6 +486,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.membus]

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
index 4ccac5e..5a43c8b 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr

@@ -1,7 +1,6 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
-warn: DTB file specified, but no device tree support in kernel
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
@@ -15,4 +14,3 @@
 warn: LCD dual screen mode not supported
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr icialluis' unimplemented
-hack: be nice to actually delete the event here

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
index c328b32..012824f 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout

@@ -1,14 +1,12 @@
-Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simout
-Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:25:29
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 17:31:37
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1194883580500 because m5_exit instruction encountered
+Exiting @ tick 1196134388000 because m5_exit instruction encountered

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index 168e144..da78d67 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

@@ -1,150 +1,156 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.195792                       # Number of seconds simulated
-sim_ticks                                1195791950500                       # Number of ticks simulated
-final_tick                               1195791950500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.196134                       # Number of seconds simulated
+sim_ticks                                1196134388000                       # Number of ticks simulated
+final_tick                               1196134388000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 418462                       # Simulator instruction rate (inst/s)
-host_op_rate                                   533251                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8153682245                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 447424                       # Number of bytes of host memory used
-host_seconds                                   146.66                       # Real time elapsed on the host
-sim_insts                                    61370228                       # Number of instructions simulated
-sim_ops                                      78204808                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 708523                       # Simulator instruction rate (inst/s)
+host_op_rate                                   902798                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            13791811883                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 403420                       # Number of bytes of host memory used
+host_seconds                                    86.73                       # Real time elapsed on the host
+sim_insts                                    61448705                       # Number of instructions simulated
+sim_ops                                      78297711                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd     51904512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker          256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           463716                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          6626164                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           393380                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4724852                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           256412                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2903920                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             62155172                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       463716                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       256412                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          720128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4136128                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data       3027304                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7163472                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst           323996                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4798512                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             62145764                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       393380                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       323996                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          717376                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4112768                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7140112                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd       6488064                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker            4                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             13464                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            103606                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             12365                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             73898                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              4088                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             45400                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               6654629                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           64627                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           756826                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               821463                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        43405972                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker           214                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu1.inst              5144                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             75003                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               6654482                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           64262                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               821098                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        43393546                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker            54                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker           107                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              387790                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             5541235                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              328876                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             3950101                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           214                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.itb.walker            54                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              214429                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             2428449                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51978249                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         387790                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         214429                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             602218                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3458903                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data            2531631                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data                 33                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                5990567                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3458903                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       43405972                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          214                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              270869                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             4011683                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51955503                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         328876                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         270869                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             599745                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3438383                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data              14212                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            2516727                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                5969323                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3438383                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       43393546                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker           54                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker          107                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             387790                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            8072866                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             328876                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3964314                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          214                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.itb.walker           54                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             214429                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            2428483                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               57968816                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       6654629                       # Number of read requests accepted
-system.physmem.writeReqs                       821463                       # Number of write requests accepted
-system.physmem.readBursts                     6654629                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     821463                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                425873472                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     22784                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7293184                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  62155172                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7163472                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      356                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  707504                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          10661                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              415730                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              415559                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              414961                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              415335                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              422368                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              415375                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              415446                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              415289                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              415350                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              415631                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             415265                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             414898                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             415491                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             416088                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             415759                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             415728                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7313                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7201                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6692                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6866                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7393                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6958                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7169                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6986                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                6988                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7250                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6972                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6687                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7223                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7529                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7375                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7354                       # Per bank write bursts
+system.physmem.bw_total::cpu1.inst             270869                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            6528410                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               57924826                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       6654482                       # Number of read requests accepted
+system.physmem.writeReqs                       821098                       # Number of write requests accepted
+system.physmem.readBursts                     6654482                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     821098                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                425858048                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     28800                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7268928                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  62145764                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7140112                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      450                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  707519                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          11807                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              415388                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              415219                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              415339                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              415675                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              422391                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              415542                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              415783                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              415483                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              416074                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              415577                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             415272                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             414856                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             415143                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             415555                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             415537                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             415198                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6998                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6842                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7022                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7170                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7417                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7181                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7437                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7180                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7616                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7218                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7106                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6658                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6803                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7016                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7092                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6821                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1195787534500                       # Total gap between requests
+system.physmem.totGap                    1196129800000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    6825                       # Read request sizes (log2)
 system.physmem.readPktSize::3                 6488064                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  159740                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  159593                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 756836                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  64627                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    636769                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    483388                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    484627                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   1579502                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                   1123930                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   1118197                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   1114450                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     25137                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     24391                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      9450                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     9387                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     9266                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     8971                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     8900                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     8855                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     8823                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      219                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       11                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  64262                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    634838                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    481612                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    482409                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                   1579414                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                   1125551                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                   1120257                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   1116869                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     25458                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     24379                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      9272                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     9173                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     9118                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     8948                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     8870                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     8835                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     8809                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      205                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       15                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -159,29 +165,29 @@
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      5178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      5187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      5182                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      5179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      5180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      5179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      5179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      5180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      5177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      5179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     5177                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     5178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     5178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     5178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     5179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     5179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     5178                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5184                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5183                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                      5162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                      5164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                      5162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                      5162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                      5163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                      5161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                      5162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                      5165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                      5162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                      5162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                     5162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                     5161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                     5163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                     5162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                     5162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     5165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     5161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5161                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5162                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
@@ -191,408 +197,401 @@
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        74963                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean     5778.397556                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     392.859970                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev   13041.482454                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-71          26098     34.81%     34.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-135        15301     20.41%     55.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-199         3417      4.56%     59.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-263         2337      3.12%     62.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-327         1552      2.07%     64.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-391         1311      1.75%     66.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-455         1048      1.40%     68.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-519         1133      1.51%     69.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-583          708      0.94%     70.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-647          576      0.77%     71.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-711          588      0.78%     72.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-775          600      0.80%     72.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-839          313      0.42%     73.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-903          304      0.41%     73.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-967          211      0.28%     74.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1031          484      0.65%     74.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1095          181      0.24%     74.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1159          133      0.18%     75.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1223          163      0.22%     75.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1287          181      0.24%     75.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1351          117      0.16%     75.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1415         2275      3.03%     78.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1479          133      0.18%     78.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1543           94      0.13%     79.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1607           64      0.09%     79.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1671           60      0.08%     79.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1735           43      0.06%     79.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1799          123      0.16%     79.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1863           53      0.07%     79.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1927           29      0.04%     79.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1991           21      0.03%     79.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2055          191      0.25%     79.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2119           19      0.03%     79.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2183           18      0.02%     79.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2247           24      0.03%     79.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2311           41      0.05%     79.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2375           14      0.02%     79.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2439           25      0.03%     80.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2503           28      0.04%     80.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2567           24      0.03%     80.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2631           25      0.03%     80.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2695           17      0.02%     80.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2759           20      0.03%     80.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2823           20      0.03%     80.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2887            7      0.01%     80.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2951           20      0.03%     80.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3015            6      0.01%     80.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3079          190      0.25%     80.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3143           23      0.03%     80.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3207            8      0.01%     80.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3271           10      0.01%     80.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3335           98      0.13%     80.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3399            7      0.01%     80.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3463            7      0.01%     80.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3527           16      0.02%     80.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3591           20      0.03%     80.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3655            6      0.01%     80.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3719           20      0.03%     80.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3783           37      0.05%     80.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3847           47      0.06%     80.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3911           17      0.02%     80.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3975            8      0.01%     80.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4039            6      0.01%     80.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4103          197      0.26%     81.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4167            7      0.01%     81.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4231           10      0.01%     81.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4295           14      0.02%     81.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4359           80      0.11%     81.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4423            4      0.01%     81.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4487           14      0.02%     81.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4551            3      0.00%     81.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4615           33      0.04%     81.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4679           14      0.02%     81.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4743            3      0.00%     81.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4807            4      0.01%     81.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4871           23      0.03%     81.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4935            5      0.01%     81.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4999            7      0.01%     81.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5063           15      0.02%     81.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5127          154      0.21%     81.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5191            3      0.00%     81.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5255           14      0.02%     81.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5319            6      0.01%     81.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5383           35      0.05%     81.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5447          170      0.23%     82.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5511           59      0.08%     82.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5639           78      0.10%     82.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5703            1      0.00%     82.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5895            9      0.01%     82.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6151           89      0.12%     82.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6279            2      0.00%     82.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6407           70      0.09%     82.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6471            1      0.00%     82.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6535            2      0.00%     82.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6599            1      0.00%     82.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6663          108      0.14%     82.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6855            1      0.00%     82.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6919           17      0.02%     82.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7047            1      0.00%     82.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7175           32      0.04%     82.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7431          132      0.18%     82.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7687           28      0.04%     82.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7943           74      0.10%     82.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8007            1      0.00%     82.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8071            1      0.00%     82.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8199           29      0.04%     83.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8384-8391            1      0.00%     83.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8455           75      0.10%     83.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8711           29      0.04%     83.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8832-8839            2      0.00%     83.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8967          130      0.17%     83.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9152-9159            1      0.00%     83.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9223           29      0.04%     83.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9280-9287            1      0.00%     83.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9479           17      0.02%     83.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9728-9735          100      0.13%     83.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9856-9863            1      0.00%     83.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-9991           74      0.10%     83.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10247           86      0.11%     83.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10496-10503           12      0.02%     83.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10752-10759           80      0.11%     83.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11015           29      0.04%     83.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11136-11143            2      0.00%     83.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11200-11207            1      0.00%     83.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11271          147      0.20%     84.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11456-11463            1      0.00%     84.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11527            8      0.01%     84.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11783           25      0.03%     84.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11904-11911            1      0.00%     84.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12039           77      0.10%     84.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12295          181      0.24%     84.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12480-12487            1      0.00%     84.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12551           36      0.05%     84.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12807           17      0.02%     84.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12864-12871            1      0.00%     84.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13063           77      0.10%     84.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13248-13255            1      0.00%     84.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13319          164      0.22%     84.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13568-13575           12      0.02%     84.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13831           12      0.02%     84.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13952-13959            1      0.00%     84.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14087           27      0.04%     84.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14144-14151            1      0.00%     84.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14215            3      0.00%     84.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14343          162      0.22%     85.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14599           88      0.12%     85.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14656-14663            1      0.00%     85.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14848-14855           21      0.03%     85.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15040-15047            2      0.00%     85.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15111           28      0.04%     85.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15232-15239            1      0.00%     85.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15367          218      0.29%     85.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15623           20      0.03%     85.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15872-15879           17      0.02%     85.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16000-16007            1      0.00%     85.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16135            8      0.01%     85.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16256-16263            2      0.00%     85.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16391          272      0.36%     86.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16640-16647            7      0.01%     86.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16768-16775            1      0.00%     86.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16896-16903           16      0.02%     86.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17152-17159           23      0.03%     86.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17280-17287            1      0.00%     86.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17408-17415          224      0.30%     86.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17600-17607            2      0.00%     86.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17664-17671           24      0.03%     86.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17920-17927           18      0.02%     86.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18112-18119            1      0.00%     86.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18176-18183           85      0.11%     86.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18304-18311            1      0.00%     86.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18432-18439          154      0.21%     86.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18688-18695           30      0.04%     86.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18944-18951           16      0.02%     86.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19200-19207           19      0.03%     86.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19328-19335            1      0.00%     86.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19456-19463          169      0.23%     87.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19712-19719           71      0.09%     87.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19968-19975           12      0.02%     87.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20224-20231           44      0.06%     87.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20288-20295            1      0.00%     87.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20352-20359            1      0.00%     87.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20480-20487          167      0.22%     87.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20608-20615            3      0.00%     87.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20736-20743           78      0.10%     87.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20800-20807            1      0.00%     87.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20864-20871            1      0.00%     87.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20992-20999           25      0.03%     87.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21184-21191            2      0.00%     87.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21248-21255           12      0.02%     87.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21376-21383            1      0.00%     87.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21504-21511          139      0.19%     87.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21760-21767           23      0.03%     87.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22016-22023           79      0.11%     88.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22208-22215            1      0.00%     88.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22272-22279            9      0.01%     88.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22528-22535           89      0.12%     88.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22592-22599            2      0.00%     88.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22784-22791           71      0.09%     88.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23040-23047          103      0.14%     88.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23296-23303           16      0.02%     88.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23360-23367            1      0.00%     88.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23552-23559           26      0.03%     88.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23680-23687            1      0.00%     88.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23808-23815          131      0.17%     88.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24064-24071           26      0.03%     88.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24320-24327           72      0.10%     88.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24384-24391            1      0.00%     88.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24576-24583           23      0.03%     88.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24832-24839           77      0.10%     88.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25088-25095           26      0.03%     88.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25216-25223            1      0.00%     88.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25344-25351          132      0.18%     89.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25600-25607           29      0.04%     89.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25856-25863           15      0.02%     89.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26112-26119           98      0.13%     89.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26240-26247            1      0.00%     89.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26304-26311            2      0.00%     89.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26368-26375           75      0.10%     89.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26432-26439            1      0.00%     89.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26560-26567            1      0.00%     89.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26624-26631           84      0.11%     89.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26880-26887           13      0.02%     89.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27136-27143           81      0.11%     89.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27392-27399           23      0.03%     89.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27584-27591            1      0.00%     89.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27648-27655          143      0.19%     89.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27840-27847            1      0.00%     89.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27904-27911            9      0.01%     89.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28032-28039            1      0.00%     89.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28160-28167           25      0.03%     89.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28288-28295            1      0.00%     89.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28416-28423           80      0.11%     90.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28544-28551            3      0.00%     90.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28608-28615            1      0.00%     90.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28672-28679          176      0.23%     90.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28736-28743            1      0.00%     90.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28928-28935           40      0.05%     90.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29184-29191           16      0.02%     90.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29440-29447           72      0.10%     90.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29632-29639            1      0.00%     90.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29696-29703          167      0.22%     90.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29760-29767            1      0.00%     90.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29952-29959           13      0.02%     90.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30208-30215            6      0.01%     90.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30272-30279            2      0.00%     90.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30464-30471           29      0.04%     90.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30592-30599            1      0.00%     90.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30720-30727          150      0.20%     90.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30848-30855            1      0.00%     90.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30976-30983           84      0.11%     91.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31232-31239           19      0.03%     91.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31488-31495           30      0.04%     91.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31552-31559            1      0.00%     91.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31616-31623            1      0.00%     91.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31744-31751          220      0.29%     91.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31872-31879            1      0.00%     91.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32000-32007           20      0.03%     91.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32256-32263           17      0.02%     91.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32512-32519           10      0.01%     91.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32640-32647            1      0.00%     91.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32768-32775          269      0.36%     91.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33024-33031           14      0.02%     91.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33216-33223            1      0.00%     91.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33280-33287           25      0.03%     91.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33344-33351            2      0.00%     91.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33536-33543           22      0.03%     91.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33600-33607            1      0.00%     91.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33664-33671            1      0.00%     91.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33728-33735            1      0.00%     91.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33792-33799          216      0.29%     92.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33920-33927            1      0.00%     92.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34048-34055           26      0.03%     92.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34176-34183            1      0.00%     92.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34304-34311           19      0.03%     92.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34560-34567           84      0.11%     92.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34688-34695            2      0.00%     92.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34816-34823          148      0.20%     92.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34880-34887            1      0.00%     92.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35072-35079           27      0.04%     92.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35328-35335            6      0.01%     92.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35584-35591           13      0.02%     92.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35776-35783            1      0.00%     92.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35840-35847          165      0.22%     92.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35904-35911            1      0.00%     92.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36096-36103           71      0.09%     92.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36352-36359           14      0.02%     92.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36480-36487            1      0.00%     92.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36608-36615           37      0.05%     93.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36800-36807            1      0.00%     93.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36864-36871          169      0.23%     93.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36928-36935            1      0.00%     93.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36992-36999            2      0.00%     93.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37120-37127           79      0.11%     93.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37248-37255            1      0.00%     93.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37376-37383           25      0.03%     93.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37504-37511            1      0.00%     93.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37632-37639            9      0.01%     93.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37888-37895          142      0.19%     93.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37952-37959            1      0.00%     93.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38144-38151           22      0.03%     93.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38400-38407           79      0.11%     93.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38656-38663           11      0.01%     93.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38912-38919           85      0.11%     93.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38976-38983            1      0.00%     93.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39104-39111            1      0.00%     93.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39168-39175           73      0.10%     93.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39232-39239            2      0.00%     93.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39424-39431           96      0.13%     94.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39680-39687           14      0.02%     94.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39936-39943           27      0.04%     94.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40192-40199          131      0.17%     94.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40320-40327            1      0.00%     94.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40448-40455           24      0.03%     94.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40512-40519            1      0.00%     94.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40704-40711           75      0.10%     94.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40768-40775            1      0.00%     94.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40960-40967           23      0.03%     94.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41152-41159            1      0.00%     94.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41216-41223           72      0.10%     94.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41344-41351            1      0.00%     94.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41472-41479           24      0.03%     94.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41728-41735          130      0.17%     94.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41984-41991           25      0.03%     94.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42240-42247           15      0.02%     94.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42496-42503          101      0.13%     94.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42752-42759           70      0.09%     95.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42944-42951            1      0.00%     95.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43008-43015           85      0.11%     95.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43264-43271            8      0.01%     95.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43520-43527           78      0.10%     95.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples        74428                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean     5819.401301                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     396.636644                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev   13081.491079                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-71          25728     34.57%     34.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-135        15292     20.55%     55.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-199         3262      4.38%     59.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-263         2304      3.10%     62.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-327         1614      2.17%     64.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-391         1322      1.78%     66.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-455         1040      1.40%     67.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-519         1190      1.60%     69.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-583          729      0.98%     70.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-647          570      0.77%     71.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-711          569      0.76%     72.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-775          665      0.89%     72.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-839          312      0.42%     73.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-903          285      0.38%     73.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-967          210      0.28%     74.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1031          384      0.52%     74.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1095          194      0.26%     74.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1159          136      0.18%     74.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1223          150      0.20%     75.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1287          155      0.21%     75.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1351          121      0.16%     75.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1415         2260      3.04%     78.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1479          133      0.18%     78.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1543          107      0.14%     78.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1607           57      0.08%     78.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1671           59      0.08%     79.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1735           48      0.06%     79.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1799           56      0.08%     79.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1863           51      0.07%     79.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1927           23      0.03%     79.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1991           16      0.02%     79.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2055          212      0.28%     79.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2119           17      0.02%     79.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2183           23      0.03%     79.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2247           26      0.03%     79.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2311          105      0.14%     79.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2375           15      0.02%     79.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2439           24      0.03%     79.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2503           24      0.03%     79.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2567           92      0.12%     80.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2631           21      0.03%     80.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2695           14      0.02%     80.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2759           18      0.02%     80.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2823           21      0.03%     80.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2887           12      0.02%     80.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2951           19      0.03%     80.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3015            7      0.01%     80.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3079          116      0.16%     80.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3143           25      0.03%     80.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3207            8      0.01%     80.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3271           13      0.02%     80.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3335           99      0.13%     80.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3399            6      0.01%     80.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3463            8      0.01%     80.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3527           17      0.02%     80.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3591           23      0.03%     80.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3655            8      0.01%     80.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3719           15      0.02%     80.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3783           32      0.04%     80.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3847           26      0.03%     80.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3911           18      0.02%     80.76% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::4096-4103          126      0.17%     80.95% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::5440-5447          169      0.23%     81.84% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::36096-36103           78      0.10%     92.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::36352-36359           11      0.01%     92.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::36608-36615           15      0.02%     92.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::36864-36871           99      0.13%     93.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37120-37127           73      0.10%     93.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37312-37319            1      0.00%     93.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37376-37383           31      0.04%     93.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37504-37511            1      0.00%     93.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37632-37639           71      0.10%     93.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37888-37895          147      0.20%     93.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::38144-38151           15      0.02%     93.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::38400-38407           87      0.12%     93.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::38528-38535            1      0.00%     93.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::38656-38663           22      0.03%     93.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::38912-38919           90      0.12%     93.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39104-39111            2      0.00%     93.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39168-39175           24      0.03%     93.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39424-39431           84      0.11%     93.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39488-39495            1      0.00%     93.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39680-39687            9      0.01%     93.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39808-39815            2      0.00%     93.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39936-39943          152      0.20%     94.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40192-40199           74      0.10%     94.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40256-40263            2      0.00%     94.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40448-40455           14      0.02%     94.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40640-40647            1      0.00%     94.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40704-40711           22      0.03%     94.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40768-40775            2      0.00%     94.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40960-40967          160      0.21%     94.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41216-41223           23      0.03%     94.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41472-41479           14      0.02%     94.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41728-41735           72      0.10%     94.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41984-41991          153      0.21%     94.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42112-42119            1      0.00%     94.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42240-42247           11      0.01%     94.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42496-42503           81      0.11%     94.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42752-42759           25      0.03%     95.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42944-42951            1      0.00%     95.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43008-43015           90      0.12%     95.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43136-43143            1      0.00%     95.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43264-43271           18      0.02%     95.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43392-43399            1      0.00%     95.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43520-43527           87      0.12%     95.29% # Bytes accessed per row activation
 system.physmem.bytesPerActivate::43648-43655            1      0.00%     95.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43776-43783           24      0.03%     95.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44032-44039          140      0.19%     95.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44288-44295           12      0.02%     95.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44352-44359            1      0.00%     95.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44416-44423            1      0.00%     95.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44544-44551           23      0.03%     95.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44800-44807           80      0.11%     95.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44928-44935            2      0.00%     95.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45056-45063          165      0.22%     95.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45184-45191            1      0.00%     95.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45248-45255            1      0.00%     95.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45312-45319           38      0.05%     95.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45568-45575           12      0.02%     95.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45824-45831           71      0.09%     96.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45952-45959            1      0.00%     96.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46080-46087          165      0.22%     96.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46144-46151            1      0.00%     96.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46336-46343           15      0.02%     96.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46592-46599           12      0.02%     96.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46720-46727            1      0.00%     96.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46848-46855           31      0.04%     96.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47104-47111          151      0.20%     96.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47168-47175            1      0.00%     96.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47360-47367           87      0.12%     96.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47488-47495            1      0.00%     96.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47616-47623           21      0.03%     96.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47744-47751            1      0.00%     96.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47872-47879           24      0.03%     96.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47936-47943            2      0.00%     96.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48000-48007            1      0.00%     96.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48128-48135          239      0.32%     97.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48192-48199            1      0.00%     97.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48256-48263            1      0.00%     97.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48384-48391           36      0.05%     97.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48640-48647           14      0.02%     97.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48768-48775           14      0.02%     97.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48896-48903            4      0.01%     97.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48960-48967            5      0.01%     97.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49024-49031            3      0.00%     97.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49088-49095            2      0.00%     97.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49152-49159         2125      2.83%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          74963                       # Bytes accessed per row activation
-system.physmem.totQLat                   159518930750                       # Total ticks spent queuing
-system.physmem.totMemAccLat              202571234500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  33271365000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  9780938750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       23972.41                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1469.87                       # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::43776-43783           17      0.02%     95.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44032-44039          146      0.20%     95.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44096-44103            1      0.00%     95.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44288-44295           71      0.10%     95.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44416-44423            1      0.00%     95.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44544-44551           32      0.04%     95.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44608-44615            1      0.00%     95.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44800-44807           75      0.10%     95.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45056-45063           96      0.13%     95.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45120-45127            1      0.00%     95.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45312-45319           16      0.02%     95.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45568-45575            9      0.01%     95.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45824-45831           79      0.11%     96.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45888-45895            1      0.00%     96.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46080-46087           86      0.12%     96.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46336-46343            3      0.00%     96.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46592-46599           79      0.11%     96.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46720-46727            1      0.00%     96.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46784-46791            1      0.00%     96.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46848-46855           84      0.11%     96.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47040-47047            1      0.00%     96.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47104-47111          165      0.22%     96.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47360-47367           25      0.03%     96.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47424-47431            1      0.00%     96.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47488-47495            1      0.00%     96.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47616-47623           19      0.03%     96.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47680-47687            1      0.00%     96.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47744-47751            1      0.00%     96.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47872-47879           18      0.02%     96.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47936-47943            2      0.00%     96.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48128-48135          184      0.25%     96.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48192-48199            1      0.00%     96.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48256-48263            2      0.00%     96.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48320-48327            3      0.00%     96.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48384-48391           42      0.06%     97.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48448-48455            1      0.00%     97.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48640-48647           81      0.11%     97.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48768-48775           11      0.01%     97.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48896-48903           14      0.02%     97.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48960-48967            7      0.01%     97.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49024-49031           10      0.01%     97.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49088-49095            7      0.01%     97.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49152-49159         2105      2.83%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          74428                       # Bytes accessed per row activation
+system.physmem.totQLat                   159442536500                       # Total ticks spent queuing
+system.physmem.totMemAccLat              202459287750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  33270160000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  9746591250                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       23961.79                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                     1464.76                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30442.28                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         356.14                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           6.10                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       51.98                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        5.99                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30426.56                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         356.03                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           6.08                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       51.96                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        5.97                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.83                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.78                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         0.17                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        12.12                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    6598430                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     94836                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        12.52                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    6598367                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     94814                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   99.16                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  83.22                       # Row buffer hit rate for writes
-system.physmem.avgGap                       159948.21                       # Average gap between requests
-system.physmem.pageHitRate                      98.89                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               4.87                       # Percentage of time for which DRAM has all the banks in precharge state
+system.physmem.writeRowHitRate                  83.48                       # Row buffer hit rate for writes
+system.physmem.avgGap                       160004.95                       # Average gap between requests
+system.physmem.pageHitRate                      98.90                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               4.95                       # Percentage of time for which DRAM has all the banks in precharge state
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
@@ -611,286 +610,314 @@
 system.realview.nvmem.bw_total::cpu0.inst           17                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst           40                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              57                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     59983824                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             7703157                       # Transaction distribution
-system.membus.trans_dist::ReadResp            7703157                       # Transaction distribution
-system.membus.trans_dist::WriteReq             767205                       # Transaction distribution
-system.membus.trans_dist::WriteResp            767205                       # Transaction distribution
-system.membus.trans_dist::Writeback             64627                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            27746                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          16446                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           10661                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            137744                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           137297                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382570                       # Packet count per connected master and slave (bytes)
+system.membus.throughput                     59941628                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             7703327                       # Transaction distribution
+system.membus.trans_dist::ReadResp            7703327                       # Transaction distribution
+system.membus.trans_dist::WriteReq             767563                       # Transaction distribution
+system.membus.trans_dist::WriteResp            767563                       # Transaction distribution
+system.membus.trans_dist::Writeback             64262                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            31362                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          17250                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           11807                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            137774                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           137331                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382556                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         8870                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        10302                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          910                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1966729                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4359117                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1971632                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4365438                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     12976128                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     12976128                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               17335245                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2389894                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total               17341566                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2389866                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        17740                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        20604                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1820                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17414132                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     19823662                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17381364                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     19793730                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port     51904512                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total     51904512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            71728174                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               71728174                       # Total data (bytes)
+system.membus.tot_pkt_size::total            71698242                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               71698242                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1224786000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1224728000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               18000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             7986500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             9233500                       # Layer occupancy (ticks)
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 system.l2c.overall_miss_latency::cpu0.itb.walker       149500                       # number of overall miss cycles
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 system.l2c.overall_miss_latency::cpu1.itb.walker        74500                       # number of overall miss cycles
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-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.883782                       # miss rate for UpgradeReq accesses
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 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
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 system.l2c.overall_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
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 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -899,159 +926,171 @@
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
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-system.l2c.UpgradeReq_mshr_miss_rate::total     0.813101                       # mshr miss rate for UpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.579420                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.561332                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000261                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001140                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013474                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.222606                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000747                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000542                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010770                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.279757                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.106790                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000261                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001140                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013474                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.222606                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000747                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000542                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010770                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.279757                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.106790                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59980.237154                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62750.797509                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58768.841591                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61887.663948                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70812.500000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59486.440890                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66057.804233                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 61604.186027                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10009.547900                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.172281                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.948784                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.574742                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.874739                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10013.685121                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56045.714220                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64546.202494                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 58758.594590                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        63625                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60061.894404                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66205.776672                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 61371.473767                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.017846                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10021.629189                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.097379                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10005.436945                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.561077                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10011.035373                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54391.368616                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62609.247888                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 58651.585338                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59980.237154                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56666.917644                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58768.841591                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55174.000958                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70812.500000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59486.440890                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64607.662938                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 59152.393857                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        63625                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60061.894404                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62780.286049                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 59025.268693                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59980.237154                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56666.917644                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58768.841591                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55174.000958                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70812.500000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59486.440890                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64607.662938                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 59152.393857                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60061.894404                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62780.286049                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 59025.268693                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -1072,62 +1111,62 @@
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                   118330469                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2505274                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2505274                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            767205                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           767205                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           576138                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           27005                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         16807                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          43812                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           262415                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          262415                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       993978                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2951141                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side         5841                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        14926                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       753985                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      2879812                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side         6193                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        12022                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7617898                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     31385016                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     53721240                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side         5780                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        18120                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     24096780                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     27936146                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side         7468                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        15168                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          137185718                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             137185718                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus         4312904                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4765712727                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                   119504988                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2535165                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2535165                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq            767563                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp           767563                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           570845                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           30638                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         17564                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          48202                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           260860                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          260860                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       864640                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1226897                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side         6150                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        12700                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       939820                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4600271                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side         6172                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        15273                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7671923                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     27252536                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     41401460                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side         7016                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        15324                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     30051724                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     39586058                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side         7384                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        21416                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          138342918                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             138342918                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         4601108                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         4758624958                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2217854478                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1926201968                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        2469983321                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy        1755625353                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
 system.toL2Bus.respLayer2.occupancy           4396000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          10396000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy           8869000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy        1698669462                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy        2208533441                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy        2116407722                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization             0.2                       # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy        2924723840                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer5.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy           4326000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy           4326499                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy           8230499                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy           9919749                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer7.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      45404559                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq              7671403                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             7671403                       # Transaction distribution
+system.iobus.throughput                      45391537                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq              7671396                       # Transaction distribution
+system.iobus.trans_dist::ReadResp             7671396                       # Transaction distribution
 system.iobus.trans_dist::WriteReq                7946                       # Transaction distribution
 system.iobus.trans_dist::WriteResp               7946                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30448                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8066                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8052                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          742                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
@@ -1149,12 +1188,12 @@
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2382570                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2382556                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     12976128                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::total     12976128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                15358698                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                15358684                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40166                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16132                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16104                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         1484                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
@@ -1176,14 +1215,14 @@
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2389894                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2389866                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side     51904512                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::total     51904512                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total             54294406                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                54294406                       # Total data (bytes)
+system.iobus.tot_pkt_size::total             54294378                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                54294378                       # Total data (bytes)
 system.iobus.reqLayer0.occupancy             21350000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              4039000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              4032000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -1229,32 +1268,32 @@
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy          6488064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.5                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374624000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2374610000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.2                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         17777853001                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy         17778098751                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     9652640                       # DTB read hits
-system.cpu0.dtb.read_misses                      3742                       # DTB read misses
-system.cpu0.dtb.write_hits                    7596858                       # DTB write hits
-system.cpu0.dtb.write_misses                     1582                       # DTB write misses
+system.cpu0.dtb.read_hits                     7069308                       # DTB read hits
+system.cpu0.dtb.read_misses                      3747                       # DTB read misses
+system.cpu0.dtb.write_hits                    5655300                       # DTB write hits
+system.cpu0.dtb.write_misses                      806                       # DTB write misses
 system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    1811                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    1799                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   138                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   142                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 9656382                       # DTB read accesses
-system.cpu0.dtb.write_accesses                7598440                       # DTB write accesses
+system.cpu0.dtb.read_accesses                 7073055                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5656106                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         17249498                       # DTB hits
-system.cpu0.dtb.misses                           5324                       # DTB misses
-system.cpu0.dtb.accesses                     17254822                       # DTB accesses
-system.cpu0.itb.inst_hits                    43298691                       # ITB inst hits
+system.cpu0.dtb.hits                         12724608                       # DTB hits
+system.cpu0.dtb.misses                           4553                       # DTB misses
+system.cpu0.dtb.accesses                     12729161                       # DTB accesses
+system.cpu0.itb.inst_hits                    29565201                       # ITB inst hits
 system.cpu0.itb.inst_misses                      2205                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
@@ -1271,79 +1310,87 @@
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                43300896                       # ITB inst accesses
-system.cpu0.itb.hits                         43298691                       # DTB hits
+system.cpu0.itb.inst_accesses                29567406                       # ITB inst accesses
+system.cpu0.itb.hits                         29565201                       # DTB hits
 system.cpu0.itb.misses                           2205                       # DTB misses
-system.cpu0.itb.accesses                     43300896                       # DTB accesses
-system.cpu0.numCycles                      2391583901                       # number of cpu cycles simulated
+system.cpu0.itb.accesses                     29567406                       # DTB accesses
+system.cpu0.numCycles                      2392268776                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   42571767                       # Number of instructions committed
-system.cpu0.committedOps                     53302041                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             48059042                       # Number of integer alu accesses
+system.cpu0.committedInsts                   28867316                       # Number of instructions committed
+system.cpu0.committedOps                     37205643                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             33092917                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                  3860                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1403630                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      5582817                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    48059042                       # number of integer instructions
+system.cpu0.num_func_calls                    1241596                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4372519                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    33092917                       # number of integer instructions
 system.cpu0.num_fp_insts                         3860                       # number of float instructions
-system.cpu0.num_int_register_reads          272441604                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          52270515                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          190017972                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          36219842                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                3022                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                840                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     18019009                       # number of memory refs
-system.cpu0.num_load_insts                   10036503                       # Number of load instructions
-system.cpu0.num_store_insts                   7982506                       # Number of store instructions
-system.cpu0.num_idle_cycles              2151142905.888201                       # Number of idle cycles
-system.cpu0.num_busy_cycles              240440995.111799                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.100536                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.899464                       # Percentage of idle cycles
+system.cpu0.num_mem_refs                     13392372                       # number of memory refs
+system.cpu0.num_load_insts                    7406786                       # Number of load instructions
+system.cpu0.num_store_insts                   5985586                       # Number of store instructions
+system.cpu0.num_idle_cycles              2246456550.382122                       # Number of idle cycles
+system.cpu0.num_busy_cycles              145812225.617878                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.060951                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.939049                       # Percentage of idle cycles
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   51319                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           490213                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          509.358566                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           42807948                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           490725                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            87.234088                       # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce                   46712                       # number of quiesce instructions executed
+system.cpu0.icache.tags.replacements           425445                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          509.359322                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           29139226                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           425957                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            68.408844                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle      76218358000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.358566                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.994841                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.994841                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst     42807948                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       42807948                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     42807948                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        42807948                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     42807948                       # number of overall hits
-system.cpu0.icache.overall_hits::total       42807948                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       490726                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       490726                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       490726                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        490726                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       490726                       # number of overall misses
-system.cpu0.icache.overall_misses::total       490726                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   6824885728                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6824885728                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   6824885728                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   6824885728                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   6824885728                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   6824885728                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     43298674                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     43298674                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     43298674                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     43298674                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     43298674                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     43298674                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011334                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.011334                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011334                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.011334                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011334                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.011334                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13907.732070                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13907.732070                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13907.732070                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13907.732070                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13907.732070                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13907.732070                       # average overall miss latency
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.359322                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.994842                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.994842                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          266                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses         29991142                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        29991142                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     29139226                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       29139226                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     29139226                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        29139226                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     29139226                       # number of overall hits
+system.cpu0.icache.overall_hits::total       29139226                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       425958                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       425958                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       425958                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        425958                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       425958                       # number of overall misses
+system.cpu0.icache.overall_misses::total       425958                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5905644218                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   5905644218                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   5905644218                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   5905644218                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   5905644218                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   5905644218                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     29565184                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     29565184                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     29565184                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     29565184                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     29565184                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     29565184                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014407                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014407                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014407                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014407                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014407                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014407                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13864.381507                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13864.381507                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13864.381507                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13864.381507                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13864.381507                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13864.381507                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1352,120 +1399,128 @@
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       490726                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       490726                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       490726                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       490726                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       490726                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       490726                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5840816272                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   5840816272                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5840816272                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   5840816272                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5840816272                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   5840816272                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       425958                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       425958                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       425958                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       425958                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       425958                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       425958                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5051503782                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5051503782                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5051503782                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   5051503782                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5051503782                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5051503782                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    436393750                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    436393750                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    436393750                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    436393750                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.011334                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.011334                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.011334                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.011334                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.011334                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.011334                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11902.398226                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11902.398226                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11902.398226                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11902.398226                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11902.398226                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11902.398226                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014407                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014407                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014407                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014407                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014407                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014407                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11859.159311                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11859.159311                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11859.159311                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11859.159311                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11859.159311                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11859.159311                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           406717                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          471.656866                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           15966646                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           407229                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            39.208028                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements           330301                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          454.615886                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           12269300                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           330813                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            37.088325                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle        666436250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   471.656866                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.921205                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.921205                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      9136610                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        9136610                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      6494353                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       6494353                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       156522                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       156522                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       158977                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       158977                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     15630963                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        15630963                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     15630963                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       15630963                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       263803                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       263803                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       176623                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       176623                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9911                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         9911                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7399                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7399                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       440426                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        440426                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       440426                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       440426                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3917573248                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   3917573248                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   7906184046                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   7906184046                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     99581999                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     99581999                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     40689888                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     40689888                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  11823757294                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  11823757294                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  11823757294                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  11823757294                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      9400413                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      9400413                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      6670976                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      6670976                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       166433                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       166433                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       166376                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       166376                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     16071389                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     16071389                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     16071389                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     16071389                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.028063                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.028063                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.026476                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.026476                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059549                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059549                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.044472                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.044472                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.027404                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.027404                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.027404                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.027404                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14850.374135                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14850.374135                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44763.049240                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 44763.049240                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10047.623751                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10047.623751                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5499.376673                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5499.376673                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26846.183681                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 26846.183681                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26846.183681                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 26846.183681                       # average overall miss latency
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   454.615886                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.887922                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.887922                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          343                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           97                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         50897043                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        50897043                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6599288                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6599288                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5350353                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5350353                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       147935                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       147935                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149626                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       149626                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     11949641                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        11949641                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     11949641                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       11949641                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       227704                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       227704                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       141542                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       141542                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9305                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         9305                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7516                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7516                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       369246                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        369246                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       369246                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       369246                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3302919746                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   3302919746                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5684238795                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   5684238795                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     91447249                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total     91447249                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     44459563                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     44459563                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data   8987158541                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total   8987158541                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data   8987158541                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total   8987158541                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6826992                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      6826992                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5491895                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5491895                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157240                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       157240                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       157142                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       157142                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12318887                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12318887                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12318887                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12318887                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033353                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.033353                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025773                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.025773                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059177                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059177                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.047829                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.047829                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029974                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.029974                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029974                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.029974                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14505.321584                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14505.321584                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40159.378806                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 40159.378806                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data  9827.753788                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9827.753788                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5915.322379                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5915.322379                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24339.217056                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 24339.217056                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24339.217056                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 24339.217056                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1474,66 +1529,66 @@
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       376546                       # number of writebacks
-system.cpu0.dcache.writebacks::total           376546                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       263803                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       263803                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       176623                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       176623                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9911                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9911                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7395                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         7395                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       440426                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       440426                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       440426                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       440426                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   3387671752                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   3387671752                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   7508595954                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   7508595954                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     79710001                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     79710001                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     25901112                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     25901112                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.writebacks::writebacks       305829                       # number of writebacks
+system.cpu0.dcache.writebacks::total           305829                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       227704                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       227704                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       141542                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       141542                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9305                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9305                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7514                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         7514                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       369246                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       369246                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       369246                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       369246                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2845576254                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2845576254                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5370172205                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5370172205                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     72789751                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     72789751                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     29432437                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     29432437                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         1000                       # number of StoreCondFailReq MSHR miss cycles
 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  10896267706                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  10896267706                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  10896267706                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10896267706                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13765830000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13765830000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  25807312360                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  25807312360                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  39573142360                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  39573142360                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.028063                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.028063                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.026476                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.026476                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059549                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059549                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.044448                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.044448                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.027404                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.027404                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.027404                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.027404                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12841.672581                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12841.672581                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42511.994214                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42511.994214                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8042.579054                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8042.579054                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  3502.516836                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  3502.516836                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   8215748459                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   8215748459                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8215748459                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   8215748459                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13558596000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13558596000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1167114500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1167114500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14725710500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14725710500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033353                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033353                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025773                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.025773                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059177                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059177                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.047817                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.047817                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029974                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.029974                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029974                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.029974                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12496.821549                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12496.821549                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37940.485545                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37940.485545                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7822.649221                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7822.649221                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  3917.013175                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  3917.013175                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24740.291686                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24740.291686                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24740.291686                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24740.291686                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22250.067595                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22250.067595                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22250.067595                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22250.067595                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1543,26 +1598,26 @@
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     5706417                       # DTB read hits
-system.cpu1.dtb.read_misses                      3586                       # DTB read misses
-system.cpu1.dtb.write_hits                    3873093                       # DTB write hits
-system.cpu1.dtb.write_misses                      644                       # DTB write misses
+system.cpu1.dtb.read_hits                     8311308                       # DTB read hits
+system.cpu1.dtb.read_misses                      3642                       # DTB read misses
+system.cpu1.dtb.write_hits                    5827742                       # DTB write hits
+system.cpu1.dtb.write_misses                     1438                       # DTB write misses
 system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1989                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1964                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   148                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   139                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 5710003                       # DTB read accesses
-system.cpu1.dtb.write_accesses                3873737                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 8314950                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5829180                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          9579510                       # DTB hits
-system.cpu1.dtb.misses                           4230                       # DTB misses
-system.cpu1.dtb.accesses                      9583740                       # DTB accesses
-system.cpu1.itb.inst_hits                    19379017                       # ITB inst hits
+system.cpu1.dtb.hits                         14139050                       # DTB hits
+system.cpu1.dtb.misses                           5080                       # DTB misses
+system.cpu1.dtb.accesses                     14144130                       # DTB accesses
+system.cpu1.itb.inst_hits                    33191969                       # ITB inst hits
 system.cpu1.itb.inst_misses                      2171                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
@@ -1579,79 +1634,86 @@
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                19381188                       # ITB inst accesses
-system.cpu1.itb.hits                         19379017                       # DTB hits
+system.cpu1.itb.inst_accesses                33194140                       # ITB inst accesses
+system.cpu1.itb.hits                         33191969                       # DTB hits
 system.cpu1.itb.misses                           2171                       # DTB misses
-system.cpu1.itb.accesses                     19381188                       # DTB accesses
-system.cpu1.numCycles                      2390136116                       # number of cpu cycles simulated
+system.cpu1.itb.accesses                     33194140                       # DTB accesses
+system.cpu1.numCycles                      2390799575                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   18798461                       # Number of instructions committed
-system.cpu1.committedOps                     24902767                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             22266699                       # Number of integer alu accesses
+system.cpu1.committedInsts                   32581389                       # Number of instructions committed
+system.cpu1.committedOps                     41092068                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             37316324                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                  6793                       # Number of float alu accesses
-system.cpu1.num_func_calls                     796691                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2514546                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    22266699                       # number of integer instructions
+system.cpu1.num_func_calls                     962102                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      3732829                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    37316324                       # number of integer instructions
 system.cpu1.num_fp_insts                         6793                       # number of float instructions
-system.cpu1.num_int_register_reads          130767489                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          23318960                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          213681333                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          39457808                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                4535                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes               2260                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     10014870                       # number of memory refs
-system.cpu1.num_load_insts                    5983067                       # Number of load instructions
-system.cpu1.num_store_insts                   4031803                       # Number of store instructions
-system.cpu1.num_idle_cycles              1969216562.004314                       # Number of idle cycles
-system.cpu1.num_busy_cycles              420919553.995686                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.176107                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.823893                       # Percentage of idle cycles
+system.cpu1.num_mem_refs                     14676854                       # number of memory refs
+system.cpu1.num_load_insts                    8633232                       # Number of load instructions
+system.cpu1.num_store_insts                   6043622                       # Number of store instructions
+system.cpu1.num_idle_cycles              1874349488.166457                       # Number of idle cycles
+system.cpu1.num_busy_cycles              516450086.833543                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.216016                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.783984                       # Percentage of idle cycles
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   39069                       # number of quiesce instructions executed
-system.cpu1.icache.tags.replacements           376769                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          474.890792                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           19001732                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           377281                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            50.364932                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     327211938000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   474.890792                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.927521                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.927521                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst     19001732                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       19001732                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     19001732                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        19001732                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     19001732                       # number of overall hits
-system.cpu1.icache.overall_hits::total       19001732                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       377281                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       377281                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       377281                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        377281                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       377281                       # number of overall misses
-system.cpu1.icache.overall_misses::total       377281                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5163865212                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   5163865212                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   5163865212                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   5163865212                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   5163865212                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   5163865212                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     19379013                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     19379013                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     19379013                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     19379013                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     19379013                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     19379013                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.019469                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.019469                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.019469                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.019469                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.019469                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.019469                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13687.053448                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13687.053448                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13687.053448                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13687.053448                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13687.053448                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13687.053448                       # average overall miss latency
+system.cpu1.kern.inst.quiesce                   43916                       # number of quiesce instructions executed
+system.cpu1.icache.tags.replacements           469558                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          478.567582                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           32721895                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           470070                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            69.610686                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      93987592500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   478.567582                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.934702                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.934702                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          448                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           63                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses         33662035                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        33662035                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     32721895                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       32721895                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     32721895                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        32721895                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     32721895                       # number of overall hits
+system.cpu1.icache.overall_hits::total       32721895                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       470070                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       470070                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       470070                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        470070                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       470070                       # number of overall misses
+system.cpu1.icache.overall_misses::total       470070                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6444934971                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   6444934971                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   6444934971                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   6444934971                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   6444934971                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   6444934971                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     33191965                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     33191965                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     33191965                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     33191965                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     33191965                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     33191965                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014162                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.014162                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014162                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.014162                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014162                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.014162                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13710.585596                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13710.585596                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13710.585596                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13710.585596                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13710.585596                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13710.585596                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1660,120 +1722,126 @@
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       377281                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       377281                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       377281                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       377281                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       377281                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       377281                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4407732788                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   4407732788                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4407732788                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   4407732788                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4407732788                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   4407732788                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       470070                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       470070                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       470070                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       470070                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       470070                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       470070                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5502849027                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   5502849027                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5502849027                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   5502849027                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5502849027                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   5502849027                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6483750                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6483750                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6483750                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total      6483750                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.019469                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.019469                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.019469                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.019469                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.019469                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.019469                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11682.890970                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11682.890970                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11682.890970                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11682.890970                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11682.890970                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11682.890970                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014162                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.014162                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.014162                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.014162                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.014162                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.014162                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11706.445906                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11706.445906                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11706.445906                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11706.445906                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11706.445906                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11706.445906                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           220436                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          471.379597                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            8230755                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           220801                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            37.276801                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle     106418022500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   471.379597                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.920663                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.920663                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      4389351                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        4389351                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      3673214                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       3673214                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        73456                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        73456                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        73714                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        73714                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      8062565                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         8062565                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      8062565                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        8062565                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       133803                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       133803                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       112797                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       112797                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         9752                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         9752                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         9418                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         9418                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       246600                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        246600                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       246600                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       246600                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1647983739                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   1647983739                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4345457226                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   4345457226                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     77502998                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     77502998                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     49351478                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     49351478                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   5993440965                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   5993440965                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   5993440965                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   5993440965                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      4523154                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      4523154                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      3786011                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      3786011                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        83208                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        83208                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        83132                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        83132                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      8309165                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      8309165                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      8309165                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      8309165                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.029582                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.029582                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.029793                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.029793                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.117200                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.117200                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.113290                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.113290                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.029678                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.029678                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.029678                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.029678                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12316.493195                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12316.493195                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38524.581558                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 38524.581558                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  7947.395201                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  7947.395201                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5240.122956                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5240.122956                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24304.302372                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 24304.302372                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24304.302372                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 24304.302372                       # average overall miss latency
+system.cpu1.dcache.tags.replacements           292078                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          471.633961                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           11962120                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           292453                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            40.902709                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      85275256250                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   471.633961                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.921160                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.921160                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          375                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          361                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3           14                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.732422                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         49437007                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        49437007                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      6946722                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        6946722                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      4827432                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       4827432                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        81845                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        81845                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        82747                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        82747                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     11774154                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        11774154                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     11774154                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       11774154                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       170562                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       170562                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       149956                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       149956                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11055                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        11055                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10053                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        10053                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       320518                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        320518                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       320518                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       320518                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2219519248                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2219519248                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   6569366202                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   6569366202                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     92844750                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     92844750                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     52203482                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     52203482                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   8788885450                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   8788885450                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   8788885450                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   8788885450                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      7117284                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      7117284                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      4977388                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      4977388                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        92900                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        92900                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        92800                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        92800                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     12094672                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     12094672                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     12094672                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     12094672                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.023964                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.023964                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030127                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.030127                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.118999                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.118999                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108330                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108330                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026501                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.026501                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.026501                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.026501                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13012.976208                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13012.976208                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 43808.625210                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 43808.625210                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  8398.439620                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8398.439620                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5192.826221                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5192.826221                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27420.879483                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 27420.879483                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27420.879483                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 27420.879483                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1782,66 +1850,66 @@
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       199592                       # number of writebacks
-system.cpu1.dcache.writebacks::total           199592                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       133803                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       133803                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       112797                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       112797                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         9752                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         9752                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         9415                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         9415                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       246600                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       246600                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       246600                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       246600                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1380025261                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1380025261                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   4109897774                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   4109897774                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     57992002                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     57992002                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     30524522                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     30524522                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         2000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         2000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   5489923035                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   5489923035                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5489923035                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   5489923035                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168387761500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168387761500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    531061000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    531061000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168918822500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168918822500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.029582                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.029582                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.029793                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.029793                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.117200                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.117200                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.113254                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.113254                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029678                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.029678                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.029678                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.029678                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10313.858890                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10313.858890                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36436.233003                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36436.233003                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  5946.677810                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  5946.677810                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3242.115985                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3242.115985                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       265016                       # number of writebacks
+system.cpu1.dcache.writebacks::total           265016                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       170562                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       170562                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       149956                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       149956                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11055                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11055                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10052                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        10052                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       320518                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       320518                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       320518                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       320518                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1877722752                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1877722752                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   6246095798                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   6246095798                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     70722250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     70722250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     32100518                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     32100518                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         1000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   8123818550                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   8123818550                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   8123818550                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   8123818550                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168605274000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168605274000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25182596842                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25182596842                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193787870842                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193787870842                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.023964                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.023964                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.030127                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.030127                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.118999                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.118999                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108319                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108319                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026501                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.026501                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026501                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.026501                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11009.033384                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11009.033384                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41652.856825                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41652.856825                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6397.308910                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6397.308910                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3193.445881                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3193.445881                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22262.461618                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22262.461618                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22262.461618                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22262.461618                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25345.904286                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25345.904286                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25345.904286                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25345.904286                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1855,6 +1923,8 @@
 system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
+system.iocache.tags.data_accesses                   0                       # Number of data accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -1863,10 +1933,10 @@
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651879453001                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 651879453001                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651879453001                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 651879453001                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651789578751                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 651789578751                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651789578751                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 651789578751                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 925b863..ea47afb 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini

@@ -12,7 +12,7 @@
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -23,7 +23,7 @@
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
@@ -75,7 +75,7 @@
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-arm-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -130,6 +130,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.dcache.tags
@@ -146,6 +147,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.dtb]
@@ -178,6 +180,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.icache.tags
@@ -194,6 +197,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.interrupts]
@@ -248,6 +252,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.cpu.l2cache.tags
@@ -264,6 +269,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.cpu.toL2Bus]
@@ -317,6 +323,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -333,6 +340,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.membus]

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
index eda827f..4174229 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr

@@ -1,7 +1,6 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
-warn: DTB file specified, but no device tree support in kernel
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
@@ -14,4 +13,3 @@
 warn: LCD dual screen mode not supported
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr bpiallis' unimplemented
-hack: be nice to actually delete the event here

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index b95a8c3..866b5bc 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout

@@ -1,14 +1,12 @@
-Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:14:19
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 17:31:30
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2615716222000 because m5_exit instruction encountered
+Exiting @ tick 2616536483000 because m5_exit instruction encountered

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index df8a2be..9c56004 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                2616536483000                       # Number of ticks simulated
 final_tick                               2616536483000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 343075                       # Simulator instruction rate (inst/s)
-host_op_rate                                   436578                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            14912044248                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 444348                       # Number of bytes of host memory used
-host_seconds                                   175.46                       # Real time elapsed on the host
+host_inst_rate                                 577538                       # Simulator instruction rate (inst/s)
+host_op_rate                                   734941                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            25103147507                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 400220                       # Number of bytes of host memory used
+host_seconds                                   104.23                       # Real time elapsed on the host
 sim_insts                                    60197580                       # Number of instructions simulated
 sim_ops                                      76603973                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    122683392                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
@@ -811,6 +813,7 @@
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy         42035380750                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                     14995644                       # DTB read hits
@@ -886,6 +889,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   510.868538                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.997790                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.997790                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          267                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          62348185                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         62348185                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     60634641                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        60634641                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      60634641                       # number of demand (read+write) hits
@@ -980,6 +991,18 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.106711                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.092147                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.774455                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65378                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2163                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6898                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56267                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997589                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         17137304                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        17137304                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         8705                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3532                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.inst       844551                       # number of ReadReq hits
@@ -1210,6 +1233,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.876746                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999759                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999759                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           74                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          109                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          97755015                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         97755015                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     13195741                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        13195741                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      9972594                       # number of WriteReq hits
@@ -1375,6 +1405,8 @@
 system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
+system.iocache.tags.data_accesses                   0                       # Number of data accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
index 44d2483..4f02f4a 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini

@@ -12,7 +12,7 @@
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -23,12 +23,12 @@
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
 mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -75,7 +75,7 @@
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-arm-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -137,6 +137,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.dcache.tags
@@ -153,6 +154,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.dtb]
@@ -185,6 +187,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.icache.tags
@@ -201,6 +204,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.interrupts]
@@ -366,6 +370,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -382,6 +387,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.l2c]
@@ -399,6 +405,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.l2c.tags
@@ -415,6 +422,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.membus]

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
index 06edbeb..38a4253 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr

@@ -1,7 +1,6 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
-warn: DTB file specified, but no device tree support in kernel
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
@@ -11,7 +10,6 @@
 warn: 	instruction 'mcr dccimvac' unimplemented
 warn: 	instruction 'mcr dccmvau' unimplemented
 warn: 	instruction 'mcr icimvau' unimplemented
-hack: be nice to actually delete the event here
 warn: LCD dual screen mode not supported
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr bpiallis' unimplemented

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
index 9b6e360..312a2d8 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout

@@ -1,9349 +1,8 @@
-Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 07:58:36
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 17:32:17
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-info: Using bootloader at address 0x80000000
-info: Entering event queue @ 0.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1000000000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2000000000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 3000000000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 4000000000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 5000000000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 6000000000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 6000003500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 7000003500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 8000003500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 9000003500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 9000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 10000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 11000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 12000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 13000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 14000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 15000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 16000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 17000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 18000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 19000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 20000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 21000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 22000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 23000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 24000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 25000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 26000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 27000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 28000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 29000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 30000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 31000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 32000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 33000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 34000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 35000006500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 36000006500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 36000007000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 37000007000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 38000007000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 39000007000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 40000007000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 41000007000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 42000007000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 43000007000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 44000007000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 44000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 45000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 46000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 47000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 48000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 49000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 50000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 51000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 52000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 53000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 54000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 55000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 56000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 57000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 58000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 59000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 60000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 61000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 62000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 63000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 64000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 65000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 66000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 67000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 68000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 69000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 70000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 71000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 72000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 73000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 74000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 75000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 76000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 77000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 78000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 79000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 80000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 81000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 82000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 83000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 84000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 85000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 86000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 87000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 88000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 89000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 90000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 91000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 92000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 93000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 94000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 95000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 96000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 97000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 98000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 99000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 100000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 101000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 102000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 103000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 104000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 105000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 106000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 107000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 108000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 109000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 110000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 111000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 112000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 113000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 114000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 115000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 116000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 117000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 118000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 119000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 120000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 121000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 122000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 123000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 124000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 125000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 126000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 127000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 128000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 129000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 130000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 131000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 132000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 133000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 134000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 135000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 136000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 137000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 138000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 139000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 140000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 141000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 142000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 143000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 144000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 145000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 146000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 147000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 148000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 149000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 150000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 151000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 152000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 153000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 154000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 155000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 156000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 157000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 158000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 159000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 160000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 161000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 162000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 163000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 164000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 165000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 166000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 167000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 168000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 169000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 170000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 171000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 172000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 173000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 174000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 175000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 176000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 177000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 178000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 179000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 180000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 181000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 182000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 183000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 184000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 185000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 186000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 187000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 188000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 189000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 190000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 191000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 192000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 193000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 194000010500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 195000010500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 195000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 196000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 197000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 198000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 199000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 200000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 201000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 202000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 203000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 204000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 205000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 206000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 207000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 208000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 209000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 210000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 211000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 212000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 213000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 214000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 215000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 216000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 217000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 218000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 219000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 220000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 221000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 222000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 223000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 224000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 225000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 226000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 227000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 228000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 229000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 230000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 231000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 232000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 233000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 234000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 235000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 236000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 237000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 238000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 239000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 240000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 241000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 242000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 243000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 244000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 245000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 246000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 247000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 248000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 249000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 250000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 251000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 252000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 253000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 254000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 255000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 256000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 257000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 258000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 259000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 260000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 261000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 262000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 263000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 264000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 265000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 266000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 267000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 268000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 269000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 270000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 271000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 272000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 273000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 274000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 275000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 276000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 277000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 278000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 279000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 280000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 281000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 282000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 283000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 284000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 285000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 286000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 287000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 288000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 289000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 290000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 291000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 292000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 293000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 294000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 295000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 296000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 297000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 298000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 299000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 300000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 301000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 302000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 303000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 304000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 305000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 306000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 307000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 308000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 309000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 310000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 311000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 312000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 313000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 314000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 315000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 316000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 317000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 318000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 319000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 320000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 321000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 322000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 323000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 324000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 325000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 326000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 327000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 328000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 329000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 330000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 331000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 332000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 333000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 334000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 335000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 336000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 337000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 338000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 339000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 340000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 341000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 342000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 343000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 344000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 345000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 346000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 347000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 348000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 349000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 350000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 351000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 352000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 353000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 354000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 355000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 356000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 357000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 358000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 359000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 360000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 361000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 362000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 363000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 364000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 365000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 366000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 367000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 368000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 369000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 370000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 371000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 372000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 373000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 374000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 375000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 376000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 377000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 378000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 379000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 380000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 381000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 382000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 383000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 384000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 385000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 386000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 387000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 388000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 389000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 390000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 391000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 392000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 393000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 394000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 395000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 396000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 397000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 398000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 399000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 400000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 401000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 402000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 403000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 404000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 405000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 406000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 407000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 408000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 409000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 410000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 411000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 412000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 413000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 414000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 415000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 416000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 417000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 418000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 419000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 420000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 421000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 422000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 423000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 424000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 425000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 426000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 427000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 428000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 429000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 430000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 431000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 432000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 433000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 434000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 435000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 436000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 437000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 438000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 439000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 440000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 441000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 442000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 443000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 444000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 445000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 446000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 447000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 448000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 449000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 450000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 451000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 452000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 453000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 454000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 455000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 456000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 457000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 458000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 459000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 460000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 461000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 462000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 463000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 464000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 465000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 466000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 467000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 468000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 469000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 470000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 471000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 472000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 473000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 474000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 475000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 476000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 477000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 478000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 479000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 480000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 481000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 482000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 483000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 484000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 485000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 486000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 487000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 488000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 489000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 490000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 491000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 492000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 493000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 494000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 495000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 496000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 497000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 498000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 499000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 500000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 501000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 502000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 503000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 504000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 505000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 506000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 507000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 508000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 509000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 510000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 511000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 512000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 513000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 514000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 515000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 516000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 517000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 518000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 519000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 520000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 521000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 522000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 523000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 524000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 525000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 526000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 527000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 528000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 529000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 530000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 531000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 532000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 533000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 534000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 535000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 536000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 537000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 538000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 539000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 540000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 541000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 542000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 543000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 544000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 545000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 546000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 547000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 548000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 549000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 550000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 551000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 552000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 553000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 554000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 555000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 556000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 557000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 558000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 559000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 560000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 561000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 562000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 563000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 564000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 565000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 566000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 567000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 568000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 569000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 570000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 571000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 572000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 573000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 574000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 575000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 576000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 577000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 578000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 579000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 580000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 581000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 582000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 583000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 584000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 585000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 586000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 587000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 588000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 589000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 590000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 591000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 592000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 593000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 594000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 595000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 596000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 597000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 598000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 599000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 600000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 601000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 602000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 603000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 604000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 605000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 606000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 607000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 608000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 609000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 610000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 611000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 612000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 613000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 614000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 615000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 616000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 617000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 618000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 619000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 620000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 621000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 622000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 623000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 624000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 625000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 626000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 627000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 628000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 629000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 630000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 631000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 632000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 633000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 634000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 635000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 636000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 637000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 638000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 639000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 640000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 641000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 642000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 643000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 644000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 645000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 646000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 647000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 648000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 649000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 650000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 651000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 652000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 653000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 654000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 655000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 656000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 657000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 658000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 659000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 660000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 661000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 662000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 663000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 664000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 665000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 666000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 667000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 668000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 669000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 670000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 671000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 672000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 673000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 674000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 675000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 676000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 677000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 678000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 679000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 680000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 681000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 682000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 683000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 684000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 685000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 686000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 687000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 688000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 689000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 690000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 691000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 692000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 693000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 694000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 695000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 696000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 697000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 698000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 699000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 700000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 701000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 702000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 703000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 704000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 705000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 706000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 707000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 708000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 709000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 710000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 711000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 712000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 713000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 714000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 715000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 716000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 717000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 718000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 719000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 720000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 721000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 722000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 723000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 724000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 725000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 726000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 727000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 728000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 729000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 730000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 731000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 732000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 733000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 734000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 735000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 736000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 737000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 738000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 739000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 740000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 741000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 742000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 743000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 744000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 745000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 746000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 747000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 748000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 749000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 750000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 751000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 752000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 753000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 754000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 755000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 756000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 757000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 758000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 759000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 760000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 761000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 762000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 763000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 764000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 765000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 766000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 767000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 768000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 769000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 770000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 771000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 772000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 773000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 774000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 775000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 776000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 777000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 778000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 779000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 780000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 781000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 782000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 783000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 784000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 785000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 786000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 787000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 788000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 789000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 790000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 791000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 792000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 793000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 794000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 795000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 796000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 797000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 798000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 799000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 800000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 801000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 802000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 803000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 804000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 805000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 806000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 807000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 808000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 809000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 810000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 811000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 812000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 813000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 814000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 815000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 816000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 817000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 818000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 819000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 820000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 821000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 822000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 823000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 824000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 825000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 826000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 827000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 828000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 829000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 830000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 831000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 832000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 833000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 834000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 835000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 836000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 837000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 838000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 839000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 840000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 841000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 842000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 843000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 844000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 845000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 846000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 847000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 848000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 849000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 850000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 851000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 852000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 853000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 854000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 855000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 856000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 857000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 858000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 859000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 860000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 861000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 862000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 863000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 864000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 865000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 866000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 867000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 868000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 869000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 870000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 871000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 872000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 873000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 874000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 875000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 876000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 877000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 878000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 879000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 880000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 881000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 882000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 883000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 884000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 885000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 886000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 887000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 888000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 889000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 890000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 891000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 892000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 893000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 894000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 895000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 896000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 897000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 898000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 899000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 900000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 901000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 902000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 903000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 904000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 905000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 906000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 907000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 908000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 909000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 910000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 911000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 912000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 913000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 914000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 915000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 916000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 917000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 918000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 919000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 920000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 921000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 922000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 923000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 924000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 925000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 926000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 927000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 928000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 929000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 930000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 931000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 932000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 933000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 934000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 935000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 936000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 937000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 938000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 939000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 940000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 941000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 942000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 943000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 944000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 945000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 946000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 947000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 948000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 949000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 950000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 951000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 952000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 953000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 954000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 955000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 956000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 957000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 958000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 959000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 960000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 961000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 962000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 963000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 964000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 965000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 966000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 967000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 968000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 969000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 970000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 971000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 972000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 973000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 974000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 975000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 976000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 977000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 978000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 979000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 980000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 981000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 982000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 983000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 984000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 985000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 986000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 987000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 988000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 989000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 990000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 991000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 992000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 993000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 994000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 995000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 996000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 997000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 998000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 999000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1000000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1001000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1002000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1003000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1004000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1005000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1006000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1007000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1008000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1009000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1010000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1011000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1012000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1013000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1014000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1015000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1016000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1017000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1018000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1019000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1020000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1021000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1022000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1023000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1024000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1025000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1026000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1027000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1028000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1029000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1030000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1031000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1032000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1033000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1034000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1035000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1036000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1037000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1038000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1039000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1040000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1041000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1042000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1043000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1044000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1045000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1046000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1047000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1048000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1049000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1050000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1051000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1052000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1053000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1054000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1055000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1056000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1057000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1058000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1059000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1060000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1061000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1062000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1063000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1064000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1065000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1066000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1067000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1068000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1069000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1070000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1071000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1072000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1073000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1074000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1075000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1076000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1077000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1078000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1079000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1080000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1081000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1082000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1083000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1084000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1085000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1086000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1087000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1088000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1089000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1090000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1091000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1092000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1093000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1094000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1095000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1096000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1097000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1098000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1099000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1100000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1101000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1102000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1103000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1104000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1105000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1106000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1107000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1108000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1109000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1110000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1111000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1112000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1113000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1114000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1115000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1116000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1117000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1118000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1119000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1120000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1121000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1122000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1123000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1124000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1125000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1126000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1127000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1128000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1129000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1130000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1131000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1132000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1133000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1134000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1135000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1136000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1137000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1138000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1139000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1140000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1141000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1142000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1143000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1144000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1145000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1146000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1147000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1148000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1149000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1150000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1151000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1152000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1153000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1154000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1155000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1156000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1157000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1158000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1159000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1160000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1161000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1162000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1163000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1164000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1165000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1166000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1167000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1168000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1169000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1170000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1171000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1172000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1173000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1174000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1175000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1176000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1177000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1178000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1179000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1180000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1181000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1182000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1183000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1184000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1185000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1186000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1187000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1188000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1189000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1190000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1191000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1192000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1193000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1194000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1195000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1196000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1197000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1198000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1199000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1200000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1201000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1202000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1203000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1204000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1205000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1206000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1207000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1208000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1209000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1210000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1211000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1212000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1213000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1214000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1215000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1216000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1217000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1218000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1219000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1220000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1221000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1222000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1223000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1224000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1225000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1226000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1227000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1228000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1229000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1230000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1231000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1232000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1233000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1234000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1235000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1236000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1237000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1238000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1239000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1240000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1241000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1242000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1243000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1244000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1245000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1246000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1247000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1248000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1249000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1250000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1251000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1252000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1253000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1254000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1255000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1256000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1257000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1258000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1259000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1260000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1261000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1262000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1263000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1264000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1265000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1266000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1267000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1268000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1269000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1270000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1271000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1272000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1273000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1274000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1275000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1276000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1277000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1278000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1279000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1280000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1281000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1282000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1283000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1284000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1285000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1286000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1287000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1288000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1289000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1290000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1291000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1292000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1293000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1294000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1295000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1296000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1297000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1298000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1299000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1300000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1301000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1302000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1303000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1304000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1305000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1306000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1307000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1308000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1309000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1310000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1311000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1312000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1313000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1314000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1315000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1316000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1317000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1318000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1319000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1320000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1321000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1322000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1323000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1324000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1325000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1326000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1327000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1328000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1329000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1330000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1331000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1332000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1333000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1334000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1335000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1336000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1337000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1338000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1339000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1340000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1341000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1342000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1343000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1344000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1345000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1346000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1347000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1348000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1349000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1350000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1351000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1352000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1353000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1354000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1355000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1356000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1357000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1358000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1359000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1360000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1361000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1362000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1363000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1364000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1365000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1366000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1367000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1368000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1369000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1370000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1371000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1372000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1373000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1374000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1375000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1376000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1377000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1378000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1379000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1380000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1381000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1382000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1383000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1384000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1385000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1386000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1387000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1388000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1389000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1390000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1391000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1392000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1393000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1394000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1395000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1396000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1397000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1398000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1399000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1400000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1401000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1402000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1403000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1404000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1405000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1406000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1407000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1408000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1409000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1410000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1411000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1412000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1413000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1414000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1415000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1416000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1417000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1418000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1419000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1420000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1421000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1422000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1423000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1424000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1425000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1426000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1427000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1428000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1429000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1430000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1431000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1432000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1433000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1434000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1435000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1436000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1437000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1438000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1439000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1440000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1441000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1442000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1443000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1444000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1445000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1446000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1447000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1448000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1449000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1450000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1451000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1452000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1453000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1454000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1455000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1456000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1457000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1458000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1459000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1460000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1461000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1462000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1463000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1464000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1465000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1466000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1467000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1468000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1469000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1470000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1471000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1472000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1473000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1474000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1475000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1476000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1477000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1478000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1479000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1480000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1481000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1482000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1483000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1484000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1485000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1486000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1487000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1488000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1489000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1490000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1491000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1492000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1493000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1494000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1495000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1496000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1497000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1498000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1499000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1500000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1501000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1502000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1503000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1504000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1505000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1506000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1507000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1508000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1509000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1510000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1511000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1512000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1513000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1514000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1515000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1516000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1517000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1518000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1519000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1520000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1521000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1522000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1523000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1524000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1525000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1526000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1527000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1528000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1529000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1530000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1531000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1532000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1533000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1534000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1535000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1536000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1537000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1538000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1539000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1540000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1541000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1542000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1543000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1544000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1545000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1546000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1547000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1548000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1549000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1550000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1551000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1552000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1553000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1554000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1555000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1556000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1557000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1558000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1559000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1560000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1561000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1562000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1563000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1564000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1565000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1566000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1567000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1568000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1569000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1570000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1571000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1572000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1573000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1574000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1575000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1576000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1577000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1578000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1579000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1580000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1581000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1582000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1583000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1584000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1585000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1586000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1587000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1588000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1589000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1590000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1591000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1592000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1593000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1594000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1595000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1596000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1597000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1598000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1599000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1600000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1601000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1602000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1603000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1604000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1605000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1606000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1607000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1608000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1609000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1610000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1611000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1612000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1613000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1614000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1615000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1616000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1617000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1618000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1619000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1620000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1621000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1622000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1623000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1624000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1625000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1626000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1627000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1628000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1629000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1630000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1631000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1632000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1633000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1634000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1635000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1636000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1637000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1638000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1639000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1640000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1641000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1642000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1643000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1644000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1645000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1646000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1647000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1648000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1649000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1650000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1651000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1652000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1653000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1654000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1655000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1656000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1657000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1658000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1659000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1660000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1661000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1662000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1663000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1664000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1665000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1666000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1667000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1668000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1669000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1670000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1671000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1672000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1673000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1674000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1675000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1676000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1677000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1678000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1679000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1680000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1681000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1682000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1683000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1684000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1685000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1686000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1687000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1688000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1689000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1690000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1691000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1692000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1693000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1694000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1695000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1696000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1697000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1698000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1699000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1700000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1701000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1702000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1703000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1704000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1705000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1706000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1707000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1708000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1709000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1710000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1711000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1712000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1713000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1714000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1715000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1716000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1717000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1718000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1719000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1720000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1721000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1722000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1723000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1724000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1725000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1726000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1727000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1728000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1729000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1730000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1731000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1732000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1733000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1734000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1735000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1736000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1737000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1738000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1739000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1740000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1741000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1742000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1743000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1744000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1745000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1746000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1747000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1748000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1749000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1750000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1751000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1752000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1753000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1754000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1755000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1756000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1757000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1758000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1759000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1760000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1761000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1762000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1763000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1764000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1765000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1766000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1767000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1768000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1769000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1770000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1771000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1772000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1773000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1774000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1775000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1776000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1777000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1778000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1779000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1780000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1781000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1782000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1783000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1784000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1785000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1786000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1787000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1788000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1789000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1790000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1791000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1792000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1793000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1794000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1795000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1796000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1797000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1798000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1799000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1800000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1801000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1802000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1803000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1804000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1805000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1806000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1807000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1808000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1809000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1810000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1811000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1812000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1813000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1814000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1815000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1816000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1817000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1818000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1819000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1820000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1821000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1822000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1823000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1824000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1825000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1826000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1827000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1828000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1829000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1830000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1831000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1832000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1833000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1834000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1835000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1836000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1837000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1838000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1839000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1840000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1841000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1842000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1843000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1844000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1845000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1846000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1847000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1848000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1849000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1850000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1851000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1852000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1853000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1854000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1855000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1856000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1857000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1858000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1859000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1860000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1861000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1862000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1863000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1864000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1865000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1866000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1867000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1868000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1869000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1870000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1871000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1872000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1873000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1874000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1875000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1876000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1877000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1878000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1879000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1880000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1881000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1882000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1883000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1884000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1885000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1886000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1887000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1888000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1889000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1890000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1891000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1892000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1893000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1894000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1895000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1896000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1897000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1898000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1899000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1900000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1901000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1902000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1903000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1904000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1905000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1906000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1907000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1908000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1909000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1910000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1911000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1912000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1913000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1914000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1915000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1916000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1917000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1918000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1919000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1920000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1921000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1922000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1923000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1924000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1925000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1926000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1927000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1928000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1929000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1930000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1931000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1932000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1933000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1934000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1935000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1936000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1937000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1938000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1939000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1940000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1941000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1942000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1943000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1944000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1945000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1946000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1947000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1948000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1949000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1950000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1951000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1952000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1953000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1954000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1955000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1956000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1957000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1958000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1959000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1960000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1961000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1962000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1963000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1964000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1965000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1966000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1967000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1968000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1969000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1970000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1971000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1972000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1973000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1974000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1975000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1976000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1977000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1978000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1979000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1980000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1981000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1982000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1983000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1984000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1985000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1986000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1987000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1988000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1989000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1990000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1991000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1992000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1993000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1994000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1995000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1996000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1997000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1998000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 1999000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2000000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2001000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2002000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2003000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2004000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2005000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2006000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2007000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2008000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2009000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2010000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2011000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2012000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2013000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2014000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2015000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2016000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2017000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2018000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2019000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2020000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2021000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2022000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2023000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2024000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2025000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2026000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2027000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2028000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2029000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2030000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2031000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2032000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2033000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2034000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2035000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2036000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2037000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2038000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2039000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2040000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2041000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2042000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2043000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2044000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2045000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2046000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2047000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2048000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2049000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2050000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2051000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2052000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2053000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2054000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2055000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2056000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2057000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2058000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2059000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2060000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2061000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2062000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2063000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2064000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2065000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2066000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2067000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2068000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2069000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2070000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2071000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2072000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2073000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2074000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2075000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2076000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2077000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2078000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2079000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2080000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2081000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2082000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2083000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2084000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2085000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2086000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2087000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2088000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2089000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2090000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2091000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2092000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2093000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2094000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2095000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2096000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2097000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2098000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2099000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2100000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2101000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2102000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2103000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2104000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2105000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2106000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2107000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2108000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2109000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2110000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2111000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2112000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2113000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2114000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2115000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2116000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2117000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2118000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2119000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2120000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2121000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2122000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2123000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2124000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2125000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2126000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2127000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2128000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2129000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2130000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2131000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2132000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2133000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2134000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2135000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2136000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2137000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2138000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2139000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2140000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2141000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2142000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2143000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2144000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2145000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2146000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2147000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2148000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2149000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2150000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2151000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2152000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2153000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2154000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2155000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2156000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2157000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2158000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2159000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2160000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2161000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2162000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2163000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2164000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2165000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2166000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2167000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2168000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2169000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2170000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2171000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2172000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2173000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2174000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2175000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2176000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2177000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2178000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2179000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2180000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2181000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2182000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2183000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2184000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2185000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2186000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2187000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2188000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2189000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2190000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2191000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2192000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2193000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2194000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2195000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2196000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2197000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2198000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2199000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2200000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2201000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2202000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2203000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2204000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2205000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2206000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2207000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2208000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2209000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2210000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2211000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2212000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2213000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2214000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2215000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2216000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2217000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2218000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2219000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2220000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2221000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2222000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2223000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2224000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2225000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2226000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2227000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2228000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2229000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2230000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2231000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2232000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2233000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2234000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2235000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2236000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2237000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2238000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2239000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2240000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2241000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2242000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2243000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2244000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2245000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2246000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2247000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2248000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2249000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2250000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2251000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2252000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2253000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2254000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2255000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2256000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2257000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2258000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2259000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2260000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2261000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2262000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2263000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2264000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2265000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2266000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2267000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2268000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2269000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2270000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2271000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2272000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2273000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2274000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2275000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2276000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2277000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2278000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2279000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2280000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2281000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2282000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2283000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2284000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2285000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2286000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2287000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2288000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2289000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2290000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2291000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2292000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2293000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2294000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2295000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2296000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2297000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2298000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2299000013500.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2300000013500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2300000016000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2301000016000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2302000016000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2303000016000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2304000016000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2305000016000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2306000016000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2307000016000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2308000016000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2309000016000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2310000016000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2311000016000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2312000016000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2313000016000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2313000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2314000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2315000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2316000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2317000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2318000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2319000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2320000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2321000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2322000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2323000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2324000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2325000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2326000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2327000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2328000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2329000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2330000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-switching cpus
-info: Entering event queue @ 2331000020000.  Starting simulation...
-Switching CPUs...
-Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2332000020000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2332000020500.  Starting simulation...

diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
index 7eb9125..af2c309 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt

@@ -4,25 +4,15 @@
 sim_ticks                                2332810264000                       # Number of ticks simulated
 final_tick                               2332810264000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 840369                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1080663                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            32452660609                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 444352                       # Number of bytes of host memory used
-host_seconds                                    71.88                       # Real time elapsed on the host
+host_inst_rate                                1583722                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2036569                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            61158803315                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 399324                       # Number of bytes of host memory used
+host_seconds                                    38.14                       # Real time elapsed on the host
 sim_insts                                    60408639                       # Number of instructions simulated
 sim_ops                                      77681819                       # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst            9                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                9                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst            9                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            9                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst            9                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               9                       # Total bandwidth to/from this memory (bytes/s)
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    111673344                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker          128                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
@@ -74,9 +64,22 @@
 system.physmem.bw_total::cpu1.inst              91056                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.data            1794913                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               54942145                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst            9                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                9                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst            9                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            9                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst            9                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               9                       # Total bandwidth to/from this memory (bytes/s)
 system.membus.throughput                     55969561                       # Throughput (bytes/s)
 system.membus.data_through_bus              130566366                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                    62242                       # number of replacements
 system.l2c.tags.tagsinuse                50006.300222                       # Cycle average of tags in use
 system.l2c.tags.total_refs                    1678485                       # Total number of references to valid blocks.
@@ -98,6 +101,18 @@
 system.l2c.tags.occ_percent::cpu1.inst       0.032004                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.044807                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.763036                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023            2                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65383                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3589                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         9187                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        52391                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000031                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.997665                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 17104735                       # Number of tag accesses
+system.l2c.tags.data_accesses                17104735                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.dtb.walker         9005                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.itb.walker         3277                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.inst             473134                       # number of ReadReq hits
@@ -321,6 +336,14 @@
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.868184                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::cpu1.inst     0.131188                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.999372                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           78                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          255                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses         62285702                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        62285702                       # Number of data accesses
 system.cpu0.icache.ReadReq_hits::cpu0.inst     32064735                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::cpu1.inst     28518763                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total       60583498                       # number of ReadReq hits
@@ -377,6 +400,13 @@
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.881443                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::cpu1.data     0.118551                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          278                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         97632366                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        97632366                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data      6995590                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::cpu1.data      6184430                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total       13180020                       # number of ReadReq hits
@@ -526,6 +556,8 @@
 system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
+system.iocache.tags.data_accesses                   0                       # Number of data accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked

diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index 299ddfd..9b76462 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini

@@ -20,7 +20,7 @@
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=atomic
 mem_ranges=0:134217727
@@ -144,6 +144,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.dcache.tags
@@ -160,6 +161,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.dtb]
@@ -192,6 +194,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=1024
 system=system
 tags=system.cpu.dtb_walker_cache.tags
@@ -208,6 +211,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=1024
 
 [system.cpu.icache]
@@ -225,6 +229,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.icache.tags
@@ -241,6 +246,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.interrupts]
@@ -289,6 +295,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=1024
 system=system
 tags=system.cpu.itb_walker_cache.tags
@@ -305,6 +312,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=1024
 
 [system.cpu.l2cache]
@@ -322,6 +330,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.cpu.l2cache.tags
@@ -338,6 +347,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.cpu.toL2Bus]
@@ -804,6 +814,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -820,6 +831,7 @@
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.membus]
@@ -1149,7 +1161,7 @@
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1172,7 +1184,7 @@
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]

diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
index 347fa32..bb1874a 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr

@@ -1,4 +1,3 @@
-warn: add_child('terminal'): child 'terminal' already has parent
 warn: Sockets disabled, not accepting terminal connections
 warn: Reading current count from inactive timer.
 warn: Sockets disabled, not accepting gdb connections
@@ -7,4 +6,3 @@
 warn: Tried to clear PCI interrupt 14
 warn: Unknown mouse command 0xe1.
 warn: instruction 'wbinvd' unimplemented
-hack: be nice to actually delete the event here

diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
index bbf756d..04f5d28 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout

@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:42:07
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 17:30:13
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5112126311000 because m5_exit instruction encountered
+Exiting @ tick 5112126264500 because m5_exit instruction encountered

diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 8eed6a1..168ad24 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                5112126264500                       # Number of ticks simulated
 final_tick                               5112126264500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1049292                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2148359                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            26829969216                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 634884                       # Number of bytes of host memory used
-host_seconds                                   190.54                       # Real time elapsed on the host
+host_inst_rate                                1777208                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3638722                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            45442487875                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 590176                       # Number of bytes of host memory used
+host_seconds                                   112.50                       # Real time elapsed on the host
 sim_insts                                   199929810                       # Number of instructions simulated
 sim_ops                                     409343850                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::pc.south_bridge.ide      2421184                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
@@ -58,6 +60,11 @@
 system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.042448                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::pc.south_bridge.ide     0.002653                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.002653                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               428616                       # Number of tag accesses
+system.iocache.tags.data_accesses              428616                       # Number of data accesses
 system.iocache.ReadReq_misses::pc.south_bridge.ide          904                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              904                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
@@ -107,6 +114,8 @@
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
 system.iobus.throughput                       2555207                       # Throughput (bytes/s)
 system.iobus.data_through_bus                13062542                       # Total data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.numCycles                      10224253904                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -142,6 +151,13 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   510.665021                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.997393                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.997393                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           87                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          134                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          291                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         245107932                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        245107932                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    243525778                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       243525778                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     243525778                       # number of demand (read+write) hits
@@ -184,6 +200,13 @@
 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.026303                       # Average occupied blocks per requestor
 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.189144                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_percent::total     0.189144                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           12                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            5                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.750000                       # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses        28774                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        28774                       # Number of data accesses
 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7887                       # number of ReadReq hits
 system.cpu.itb_walker_cache.ReadReq_hits::total         7887                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
@@ -232,6 +255,13 @@
 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.014181                       # Average occupied blocks per requestor
 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.313386                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_percent::total     0.313386                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           12                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            5                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.750000                       # Percentage of cache occupancy per task id
+system.cpu.dtb_walker_cache.tags.tag_accesses        52398                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses        52398                       # Number of data accesses
 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12963                       # number of ReadReq hits
 system.cpu.dtb_walker_cache.ReadReq_hits::total        12963                       # number of ReadReq hits
 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12963                       # number of demand (read+write) hits
@@ -276,6 +306,13 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.999424                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999999                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          226                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          259                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           27                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          88813841                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88813841                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     12077531                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        12077531                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      8095378                       # number of WriteReq hits
@@ -339,6 +376,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.038003                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.159035                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.989106                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        64128                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          282                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3455                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        20892                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        39453                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978516                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         32198887                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        32198887                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6504                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2802                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.inst       777739                       # number of ReadReq hits

diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 4c88876..d9f4700 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=true
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -14,10 +16,11 @@
 cache_line_size=64
 clk_domain=system.clk_domain
 e820_table=system.e820_table
+eventq_index=0
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=timing
 mem_ranges=0:134217727
@@ -38,6 +41,7 @@
 [system.acpi_description_table_pointer]
 type=X86ACPIRSDP
 children=xsdt
+eventq_index=0
 oem_id=
 revision=2
 rsdt=Null
@@ -48,6 +52,7 @@
 creator_id=
 creator_revision=0
 entries=
+eventq_index=0
 oem_id=
 oem_revision=0
 oem_table_id=
@@ -56,6 +61,7 @@
 type=Bridge
 clk_domain=system.clk_domain
 delay=50000
+eventq_index=0
 ranges=11529215046068469760:11529215046068473855
 req_size=16
 resp_size=16
@@ -66,6 +72,7 @@
 type=Bridge
 clk_domain=system.clk_domain
 delay=50000
+eventq_index=0
 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
 req_size=16
 resp_size=16
@@ -75,6 +82,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -87,6 +95,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -111,6 +120,7 @@
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dcache]
 type=BaseCache
@@ -118,6 +128,7 @@
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -126,6 +137,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.dcache.tags
@@ -140,18 +152,22 @@
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.dtb_walker_cache.cpu_side
@@ -162,6 +178,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -170,6 +187,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=1024
 system=system
 tags=system.cpu.dtb_walker_cache.tags
@@ -184,7 +202,9 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=1024
 
 [system.cpu.icache]
@@ -193,6 +213,7 @@
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -201,6 +222,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.icache.tags
@@ -215,12 +237,15 @@
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -231,16 +256,19 @@
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.itb_walker_cache.cpu_side
@@ -251,6 +279,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -259,6 +288,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=1024
 system=system
 tags=system.cpu.itb_walker_cache.tags
@@ -273,7 +303,9 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=1024
 
 [system.cpu.l2cache]
@@ -282,6 +314,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -290,6 +323,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.cpu.l2cache.tags
@@ -304,12 +338,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -319,44 +356,52 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.e820_table]
 type=X86E820Table
 children=entries0 entries1 entries2 entries3
 entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
+eventq_index=0
 
 [system.e820_table.entries0]
 type=X86E820Entry
 addr=0
+eventq_index=0
 range_type=1
 size=654336
 
 [system.e820_table.entries1]
 type=X86E820Entry
 addr=654336
+eventq_index=0
 range_type=2
 size=394240
 
 [system.e820_table.entries2]
 type=X86E820Entry
 addr=1048576
+eventq_index=0
 range_type=1
 size=133169152
 
 [system.e820_table.entries3]
 type=X86E820Entry
 addr=4294901760
+eventq_index=0
 range_type=2
 size=65536
 
 [system.intel_mp_pointer]
 type=X86IntelMPFloatingPointer
 default_config=0
+eventq_index=0
 imcr_present=true
 spec_rev=4
 
@@ -364,6 +409,7 @@
 type=X86IntelMPConfigTable
 children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 ext_entries
 base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32
+eventq_index=0
 ext_entries=system.intel_mp_table.ext_entries
 local_apic=4276092928
 oem_id=
@@ -376,6 +422,7 @@
 type=X86IntelMPProcessor
 bootstrap=true
 enable=true
+eventq_index=0
 family=0
 feature_flags=0
 local_apic_id=0
@@ -387,6 +434,7 @@
 type=X86IntelMPIOAPIC
 address=4273995776
 enable=true
+eventq_index=0
 id=1
 version=17
 
@@ -394,16 +442,19 @@
 type=X86IntelMPBus
 bus_id=0
 bus_type=ISA
+eventq_index=0
 
 [system.intel_mp_table.base_entries03]
 type=X86IntelMPBus
 bus_id=1
 bus_type=PCI
+eventq_index=0
 
 [system.intel_mp_table.base_entries04]
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=16
+eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
 source_bus_id=1
@@ -414,6 +465,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=0
+eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
 source_bus_id=0
@@ -424,6 +476,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=2
+eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
 source_bus_id=0
@@ -434,6 +487,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=0
+eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
 source_bus_id=0
@@ -444,6 +498,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=1
+eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
 source_bus_id=0
@@ -454,6 +509,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=0
+eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
 source_bus_id=0
@@ -464,6 +520,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=3
+eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
 source_bus_id=0
@@ -474,6 +531,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=0
+eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
 source_bus_id=0
@@ -484,6 +542,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=4
+eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
 source_bus_id=0
@@ -494,6 +553,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=0
+eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
 source_bus_id=0
@@ -504,6 +564,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=5
+eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
 source_bus_id=0
@@ -514,6 +575,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=0
+eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
 source_bus_id=0
@@ -524,6 +586,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=6
+eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
 source_bus_id=0
@@ -534,6 +597,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=0
+eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
 source_bus_id=0
@@ -544,6 +608,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=7
+eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
 source_bus_id=0
@@ -554,6 +619,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=0
+eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
 source_bus_id=0
@@ -564,6 +630,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=8
+eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
 source_bus_id=0
@@ -574,6 +641,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=0
+eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
 source_bus_id=0
@@ -584,6 +652,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=9
+eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
 source_bus_id=0
@@ -594,6 +663,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=0
+eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
 source_bus_id=0
@@ -604,6 +674,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=10
+eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
 source_bus_id=0
@@ -614,6 +685,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=0
+eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
 source_bus_id=0
@@ -624,6 +696,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=11
+eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
 source_bus_id=0
@@ -634,6 +707,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=0
+eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
 source_bus_id=0
@@ -644,6 +718,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=12
+eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
 source_bus_id=0
@@ -654,6 +729,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=0
+eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
 source_bus_id=0
@@ -664,6 +740,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=13
+eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
 source_bus_id=0
@@ -674,6 +751,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=0
+eventq_index=0
 interrupt_type=ExtInt
 polarity=ConformPolarity
 source_bus_id=0
@@ -684,6 +762,7 @@
 type=X86IntelMPIOIntAssignment
 dest_io_apic_id=1
 dest_io_apic_intin=14
+eventq_index=0
 interrupt_type=INT
 polarity=ConformPolarity
 source_bus_id=0
@@ -693,16 +772,19 @@
 [system.intel_mp_table.ext_entries]
 type=X86IntelMPBusHierarchy
 bus_id=0
+eventq_index=0
 parent_bus=1
 subtractive_decode=true
 
 [system.intrctrl]
 type=IntrControl
+eventq_index=0
 sys=system
 
 [system.iobus]
 type=NoncoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 use_default_range=true
 width=8
@@ -716,6 +798,7 @@
 addr_ranges=0:134217727
 assoc=8
 clk_domain=system.clk_domain
+eventq_index=0
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -724,6 +807,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -738,13 +822,16 @@
 assoc=8
 block_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -756,6 +843,7 @@
 [system.membus.badaddr_responder]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -772,13 +860,15 @@
 
 [system.pc]
 type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal
+children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge
+eventq_index=0
 intrctrl=system.intrctrl
 system=system
 
 [system.pc.behind_pci]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=9223372036854779128
 pio_latency=100000
@@ -797,6 +887,7 @@
 type=Uart8250
 children=terminal
 clk_domain=system.clk_domain
+eventq_index=0
 pio_addr=9223372036854776824
 pio_latency=100000
 platform=system.pc
@@ -806,13 +897,7 @@
 
 [system.pc.com_1.terminal]
 type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.com_1.terminal]
-type=Terminal
+eventq_index=0
 intr_control=system.intrctrl
 number=0
 output=true
@@ -821,6 +906,7 @@
 [system.pc.fake_com_2]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=9223372036854776568
 pio_latency=100000
@@ -838,6 +924,7 @@
 [system.pc.fake_com_3]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=9223372036854776808
 pio_latency=100000
@@ -855,6 +942,7 @@
 [system.pc.fake_com_4]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=9223372036854776552
 pio_latency=100000
@@ -872,6 +960,7 @@
 [system.pc.fake_floppy]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=9223372036854776818
 pio_latency=100000
@@ -889,6 +978,7 @@
 [system.pc.i_dont_exist]
 type=IsaFake
 clk_domain=system.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=9223372036854775936
 pio_latency=100000
@@ -907,6 +997,7 @@
 type=PciConfigAll
 bus=0
 clk_domain=system.clk_domain
+eventq_index=0
 pio_addr=0
 pio_latency=30000
 platform=system.pc
@@ -919,6 +1010,7 @@
 children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
 cmos=system.pc.south_bridge.cmos
 dma1=system.pc.south_bridge.dma1
+eventq_index=0
 io_apic=system.pc.south_bridge.io_apic
 keyboard=system.pc.south_bridge.keyboard
 pic1=system.pc.south_bridge.pic1
@@ -931,6 +1023,7 @@
 type=Cmos
 children=int_pin
 clk_domain=system.clk_domain
+eventq_index=0
 int_pin=system.pc.south_bridge.cmos.int_pin
 pio_addr=9223372036854775920
 pio_latency=100000
@@ -940,10 +1033,12 @@
 
 [system.pc.south_bridge.cmos.int_pin]
 type=X86IntSourcePin
+eventq_index=0
 
 [system.pc.south_bridge.dma1]
 type=I8237
 clk_domain=system.clk_domain
+eventq_index=0
 pio_addr=9223372036854775808
 pio_latency=100000
 system=system
@@ -972,6 +1067,7 @@
 BAR5Size=0
 BIST=0
 CacheLineSize=0
+CapabilityPtr=0
 CardbusCIS=0
 ClassCode=1
 Command=0
@@ -981,8 +1077,40 @@
 InterruptLine=14
 InterruptPin=1
 LatencyTimer=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
 MaximumLatency=0
 MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
 ProgIF=128
 Revision=0
 Status=640
@@ -994,6 +1122,7 @@
 config_latency=20000
 ctrl_offset=0
 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
+eventq_index=0
 io_shift=0
 pci_bus=0
 pci_dev=4
@@ -1010,19 +1139,22 @@
 children=image
 delay=1000000
 driveID=master
+eventq_index=0
 image=system.pc.south_bridge.ide.disks0.image
 
 [system.pc.south_bridge.ide.disks0.image]
 type=CowDiskImage
 children=child
 child=system.pc.south_bridge.ide.disks0.image.child
+eventq_index=0
 image_file=
 read_only=false
 table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
+eventq_index=0
+image_file=/dist/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1030,102 +1162,120 @@
 children=image
 delay=1000000
 driveID=master
+eventq_index=0
 image=system.pc.south_bridge.ide.disks1.image
 
 [system.pc.south_bridge.ide.disks1.image]
 type=CowDiskImage
 children=child
 child=system.pc.south_bridge.ide.disks1.image.child
+eventq_index=0
 image_file=
 read_only=false
 table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+eventq_index=0
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
 type=X86IntLine
 children=sink
+eventq_index=0
 sink=system.pc.south_bridge.int_lines0.sink
 source=system.pc.south_bridge.pic1.output
 
 [system.pc.south_bridge.int_lines0.sink]
 type=X86IntSinkPin
 device=system.pc.south_bridge.io_apic
+eventq_index=0
 number=0
 
 [system.pc.south_bridge.int_lines1]
 type=X86IntLine
 children=sink
+eventq_index=0
 sink=system.pc.south_bridge.int_lines1.sink
 source=system.pc.south_bridge.pic2.output
 
 [system.pc.south_bridge.int_lines1.sink]
 type=X86IntSinkPin
 device=system.pc.south_bridge.pic1
+eventq_index=0
 number=2
 
 [system.pc.south_bridge.int_lines2]
 type=X86IntLine
 children=sink
+eventq_index=0
 sink=system.pc.south_bridge.int_lines2.sink
 source=system.pc.south_bridge.cmos.int_pin
 
 [system.pc.south_bridge.int_lines2.sink]
 type=X86IntSinkPin
 device=system.pc.south_bridge.pic2
+eventq_index=0
 number=0
 
 [system.pc.south_bridge.int_lines3]
 type=X86IntLine
 children=sink
+eventq_index=0
 sink=system.pc.south_bridge.int_lines3.sink
 source=system.pc.south_bridge.pit.int_pin
 
 [system.pc.south_bridge.int_lines3.sink]
 type=X86IntSinkPin
 device=system.pc.south_bridge.pic1
+eventq_index=0
 number=0
 
 [system.pc.south_bridge.int_lines4]
 type=X86IntLine
 children=sink
+eventq_index=0
 sink=system.pc.south_bridge.int_lines4.sink
 source=system.pc.south_bridge.pit.int_pin
 
 [system.pc.south_bridge.int_lines4.sink]
 type=X86IntSinkPin
 device=system.pc.south_bridge.io_apic
+eventq_index=0
 number=2
 
 [system.pc.south_bridge.int_lines5]
 type=X86IntLine
 children=sink
+eventq_index=0
 sink=system.pc.south_bridge.int_lines5.sink
 source=system.pc.south_bridge.keyboard.keyboard_int_pin
 
 [system.pc.south_bridge.int_lines5.sink]
 type=X86IntSinkPin
 device=system.pc.south_bridge.io_apic
+eventq_index=0
 number=1
 
 [system.pc.south_bridge.int_lines6]
 type=X86IntLine
 children=sink
+eventq_index=0
 sink=system.pc.south_bridge.int_lines6.sink
 source=system.pc.south_bridge.keyboard.mouse_int_pin
 
 [system.pc.south_bridge.int_lines6.sink]
 type=X86IntSinkPin
 device=system.pc.south_bridge.io_apic
+eventq_index=0
 number=12
 
 [system.pc.south_bridge.io_apic]
 type=I82094AA
 apic_id=1
 clk_domain=system.clk_domain
+eventq_index=0
 external_int_pic=system.pc.south_bridge.pic1
 int_latency=1000
 pio_addr=4273995776
@@ -1140,6 +1290,7 @@
 clk_domain=system.clk_domain
 command_port=9223372036854775908
 data_port=9223372036854775904
+eventq_index=0
 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
 mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
 pio_addr=0
@@ -1149,14 +1300,17 @@
 
 [system.pc.south_bridge.keyboard.keyboard_int_pin]
 type=X86IntSourcePin
+eventq_index=0
 
 [system.pc.south_bridge.keyboard.mouse_int_pin]
 type=X86IntSourcePin
+eventq_index=0
 
 [system.pc.south_bridge.pic1]
 type=I8259
 children=output
 clk_domain=system.clk_domain
+eventq_index=0
 mode=I8259Master
 output=system.pc.south_bridge.pic1.output
 pio_addr=9223372036854775840
@@ -1167,11 +1321,13 @@
 
 [system.pc.south_bridge.pic1.output]
 type=X86IntSourcePin
+eventq_index=0
 
 [system.pc.south_bridge.pic2]
 type=I8259
 children=output
 clk_domain=system.clk_domain
+eventq_index=0
 mode=I8259Slave
 output=system.pc.south_bridge.pic2.output
 pio_addr=9223372036854775968
@@ -1182,11 +1338,13 @@
 
 [system.pc.south_bridge.pic2.output]
 type=X86IntSourcePin
+eventq_index=0
 
 [system.pc.south_bridge.pit]
 type=I8254
 children=int_pin
 clk_domain=system.clk_domain
+eventq_index=0
 int_pin=system.pc.south_bridge.pit.int_pin
 pio_addr=9223372036854775872
 pio_latency=100000
@@ -1195,10 +1353,12 @@
 
 [system.pc.south_bridge.pit.int_pin]
 type=X86IntSourcePin
+eventq_index=0
 
 [system.pc.south_bridge.speaker]
 type=PcSpeaker
 clk_domain=system.clk_domain
+eventq_index=0
 i8254=system.pc.south_bridge.pit
 pio_addr=9223372036854775905
 pio_latency=100000
@@ -1217,6 +1377,7 @@
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -1228,19 +1389,23 @@
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[3]
 
 [system.smbios_table]
 type=X86SMBiosSMBiosTable
 children=structures
+eventq_index=0
 major_version=2
 minor_version=5
 structures=system.smbios_table.structures
@@ -1251,6 +1416,7 @@
 characteristics=
 emb_cont_firmware_major=0
 emb_cont_firmware_minor=0
+eventq_index=0
 major=0
 minor=0
 release_date=06/08/2008
@@ -1261,5 +1427,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
index 347fa32..bb1874a 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr

@@ -1,4 +1,3 @@
-warn: add_child('terminal'): child 'terminal' already has parent
 warn: Sockets disabled, not accepting terminal connections
 warn: Reading current count from inactive timer.
 warn: Sockets disabled, not accepting gdb connections
@@ -7,4 +6,3 @@
 warn: Tried to clear PCI interrupt 14
 warn: Unknown mouse command 0xe1.
 warn: instruction 'wbinvd' unimplemented
-hack: be nice to actually delete the event here

diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index 3c12ad3..f1feb2e 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout

@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:55:08
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 17:30:19
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5192277855000 because m5_exit instruction encountered
+Exiting @ tick 5196390180000 because m5_exit instruction encountered

diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 79d47dc..b371db5 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                5196390180000                       # Number of ticks simulated
 final_tick                               5196390180000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 893068                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1721530                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            36161085452                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 586592                       # Number of bytes of host memory used
-host_seconds                                   143.70                       # Real time elapsed on the host
+host_inst_rate                                 991078                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1910460                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            40129605273                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 591204                       # Number of bytes of host memory used
+host_seconds                                   129.49                       # Real time elapsed on the host
 sim_insts                                   128334813                       # Number of instructions simulated
 sim_ops                                     247385808                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::pc.south_bridge.ide      2883712                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker          128                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
@@ -419,6 +421,11 @@
 system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.113099                       # Average occupied blocks per requestor
 system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007069                       # Average percentage of cache occupancy
 system.iocache.tags.occ_percent::total       0.007069                       # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses               428004                       # Number of tag accesses
+system.iocache.tags.data_accesses              428004                       # Number of data accesses
 system.iocache.ReadReq_misses::pc.south_bridge.ide          836                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              836                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
@@ -616,6 +623,8 @@
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer2.occupancy             1655000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.numCycles                      10392780360                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -651,6 +660,14 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   510.351939                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.996781                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.996781                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          299                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         146161971                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        146161971                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst    144584753                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       144584753                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     144584753                       # number of demand (read+write) hits
@@ -729,6 +746,14 @@
 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.069761                       # Average occupied blocks per requestor
 system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.191860                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_percent::total     0.191860                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           11                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.687500                       # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses        29050                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        29050                       # Number of data accesses
 system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7617                       # number of ReadReq hits
 system.cpu.itb_walker_cache.ReadReq_hits::total         7617                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
@@ -813,6 +838,14 @@
 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.052475                       # Average occupied blocks per requestor
 system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.315780                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_percent::total     0.315780                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           13                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
+system.cpu.dtb_walker_cache.tags.tag_accesses        53026                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses        53026                       # Number of data accesses
 system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12806                       # number of ReadReq hits
 system.cpu.dtb_walker_cache.ReadReq_hits::total        12806                       # number of ReadReq hits
 system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12806                       # number of demand (read+write) hits
@@ -893,6 +926,14 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.997026                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          333                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           78                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          88253354                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88253354                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     11993197                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        11993197                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      8040328                       # number of WriteReq hits
@@ -1047,6 +1088,15 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.052573                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.170366                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.987720                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        64716                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2864                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4951                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56789                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987488                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         32180081                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        32180081                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6740                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2903                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.inst       775712                       # number of ReadReq hits

diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index 0062dcb..71b238f 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini

@@ -5,16 +5,17 @@
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=drivesys.clk_domain
-console=/dist/m5/system/binaries/console
+console=/dist/binaries/console
+eventq_index=0
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
 mem_ranges=0:134217727
 memories=drivesys.physmem
 num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
-readfile=/z/m5/regression/zizzer/gem5/configs/boot/netperf-server.rcS
+pal=/dist/binaries/ts_osfpal
+readfile=/work/gem5.ext/configs/boot/netperf-server.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -31,6 +32,7 @@
 type=Bridge
 clk_domain=drivesys.clk_domain
 delay=50000
+eventq_index=0
 ranges=8796093022208:18446744073709551615
 req_size=16
 resp_size=16
@@ -40,6 +42,7 @@
 [drivesys.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=drivesys.voltage_domain
 
 [drivesys.cpu]
@@ -52,6 +55,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=drivesys.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -82,43 +86,53 @@
 [drivesys.cpu.clk_domain]
 type=SrcClockDomain
 clock=250
+eventq_index=0
 voltage_domain=drivesys.voltage_domain
 
 [drivesys.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [drivesys.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [drivesys.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=drivesys
 
 [drivesys.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [drivesys.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [drivesys.disk0]
 type=IdeDisk
 children=image
 delay=1000000
 driveID=master
+eventq_index=0
 image=drivesys.disk0.image
 
 [drivesys.disk0.image]
 type=CowDiskImage
 children=child
 child=drivesys.disk0.image.child
+eventq_index=0
 image_file=
 read_only=false
 table_size=65536
 
 [drivesys.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+eventq_index=0
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [drivesys.disk2]
@@ -126,29 +140,34 @@
 children=image
 delay=1000000
 driveID=master
+eventq_index=0
 image=drivesys.disk2.image
 
 [drivesys.disk2.image]
 type=CowDiskImage
 children=child
 child=drivesys.disk2.image.child
+eventq_index=0
 image_file=
 read_only=false
 table_size=65536
 
 [drivesys.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+eventq_index=0
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [drivesys.intrctrl]
 type=IntrControl
+eventq_index=0
 sys=drivesys
 
 [drivesys.iobridge]
 type=Bridge
 clk_domain=drivesys.clk_domain
 delay=50000
+eventq_index=0
 ranges=0:134217727
 req_size=16
 resp_size=16
@@ -158,6 +177,7 @@
 [drivesys.iobus]
 type=NoncoherentBus
 clk_domain=drivesys.clk_domain
+eventq_index=0
 header_cycles=1
 use_default_range=true
 width=8
@@ -169,6 +189,7 @@
 type=CoherentBus
 children=badaddr_responder
 clk_domain=drivesys.clk_domain
+eventq_index=0
 header_cycles=1
 system=drivesys
 use_default_range=false
@@ -180,6 +201,7 @@
 [drivesys.membus.badaddr_responder]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -199,6 +221,7 @@
 bandwidth=73.000000
 clk_domain=drivesys.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -210,15 +233,18 @@
 type=SimpleDisk
 children=disk
 disk=drivesys.simple_disk.disk
+eventq_index=0
 system=drivesys
 
 [drivesys.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+eventq_index=0
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [drivesys.terminal]
 type=Terminal
+eventq_index=0
 intr_control=drivesys.intrctrl
 number=0
 output=true
@@ -227,6 +253,7 @@
 [drivesys.tsunami]
 type=Tsunami
 children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+eventq_index=0
 intrctrl=drivesys.intrctrl
 system=drivesys
 
@@ -235,6 +262,7 @@
 clk_domain=drivesys.clk_domain
 cpu=drivesys.cpu
 disk=drivesys.simple_disk
+eventq_index=0
 pio_addr=8804682956800
 pio_latency=100000
 platform=drivesys.tsunami
@@ -245,6 +273,7 @@
 [drivesys.tsunami.cchip]
 type=TsunamiCChip
 clk_domain=drivesys.clk_domain
+eventq_index=0
 pio_addr=8803072344064
 pio_latency=100000
 system=drivesys
@@ -274,6 +303,7 @@
 BAR5Size=0
 BIST=0
 CacheLineSize=0
+CapabilityPtr=0
 CardbusCIS=0
 ClassCode=2
 Command=0
@@ -283,8 +313,40 @@
 InterruptLine=30
 InterruptPin=1
 LatencyTimer=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
 MaximumLatency=52
 MinimumGrant=176
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
 ProgIF=0
 Revision=0
 Status=656
@@ -301,6 +363,7 @@
 dma_read_factor=0
 dma_write_delay=0
 dma_write_factor=0
+eventq_index=0
 hardware_address=00:90:00:00:00:02
 intr_delay=10000000
 pci_bus=0
@@ -325,11 +388,13 @@
 [drivesys.tsunami.ethernet.clk_domain]
 type=SrcClockDomain
 clock=2000
+eventq_index=0
 voltage_domain=drivesys.voltage_domain
 
 [drivesys.tsunami.fake_OROM]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8796093677568
 pio_latency=100000
@@ -347,6 +412,7 @@
 [drivesys.tsunami.fake_ata0]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848432
 pio_latency=100000
@@ -364,6 +430,7 @@
 [drivesys.tsunami.fake_ata1]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848304
 pio_latency=100000
@@ -381,6 +448,7 @@
 [drivesys.tsunami.fake_pnp_addr]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848569
 pio_latency=100000
@@ -398,6 +466,7 @@
 [drivesys.tsunami.fake_pnp_read0]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848451
 pio_latency=100000
@@ -415,6 +484,7 @@
 [drivesys.tsunami.fake_pnp_read1]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848515
 pio_latency=100000
@@ -432,6 +502,7 @@
 [drivesys.tsunami.fake_pnp_read2]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848579
 pio_latency=100000
@@ -449,6 +520,7 @@
 [drivesys.tsunami.fake_pnp_read3]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848643
 pio_latency=100000
@@ -466,6 +538,7 @@
 [drivesys.tsunami.fake_pnp_read4]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848707
 pio_latency=100000
@@ -483,6 +556,7 @@
 [drivesys.tsunami.fake_pnp_read5]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848771
 pio_latency=100000
@@ -500,6 +574,7 @@
 [drivesys.tsunami.fake_pnp_read6]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848835
 pio_latency=100000
@@ -517,6 +592,7 @@
 [drivesys.tsunami.fake_pnp_read7]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848899
 pio_latency=100000
@@ -534,6 +610,7 @@
 [drivesys.tsunami.fake_pnp_write]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615850617
 pio_latency=100000
@@ -551,6 +628,7 @@
 [drivesys.tsunami.fake_ppc]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848891
 pio_latency=100000
@@ -568,6 +646,7 @@
 [drivesys.tsunami.fake_sm_chip]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848816
 pio_latency=100000
@@ -585,6 +664,7 @@
 [drivesys.tsunami.fake_uart1]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848696
 pio_latency=100000
@@ -602,6 +682,7 @@
 [drivesys.tsunami.fake_uart2]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848936
 pio_latency=100000
@@ -619,6 +700,7 @@
 [drivesys.tsunami.fake_uart3]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848680
 pio_latency=100000
@@ -636,6 +718,7 @@
 [drivesys.tsunami.fake_uart4]
 type=IsaFake
 clk_domain=drivesys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848944
 pio_latency=100000
@@ -654,6 +737,7 @@
 type=BadDevice
 clk_domain=drivesys.clk_domain
 devicename=FrameBuffer
+eventq_index=0
 pio_addr=8804615848912
 pio_latency=100000
 system=drivesys
@@ -681,6 +765,7 @@
 BAR5Size=0
 BIST=0
 CacheLineSize=0
+CapabilityPtr=0
 CardbusCIS=0
 ClassCode=1
 Command=0
@@ -690,8 +775,40 @@
 InterruptLine=31
 InterruptPin=1
 LatencyTimer=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
 MaximumLatency=0
 MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
 ProgIF=133
 Revision=0
 Status=640
@@ -703,6 +820,7 @@
 config_latency=20000
 ctrl_offset=0
 disks=drivesys.disk0 drivesys.disk2
+eventq_index=0
 io_shift=0
 pci_bus=0
 pci_dev=0
@@ -717,6 +835,7 @@
 [drivesys.tsunami.io]
 type=TsunamiIO
 clk_domain=drivesys.clk_domain
+eventq_index=0
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=100000
@@ -729,6 +848,7 @@
 [drivesys.tsunami.pchip]
 type=TsunamiPChip
 clk_domain=drivesys.clk_domain
+eventq_index=0
 pio_addr=8802535473152
 pio_latency=100000
 system=drivesys
@@ -739,6 +859,7 @@
 type=PciConfigAll
 bus=0
 clk_domain=drivesys.clk_domain
+eventq_index=0
 pio_addr=0
 pio_latency=30000
 platform=drivesys.tsunami
@@ -749,6 +870,7 @@
 [drivesys.tsunami.uart]
 type=Uart8250
 clk_domain=drivesys.clk_domain
+eventq_index=0
 pio_addr=8804615848952
 pio_latency=100000
 platform=drivesys.tsunami
@@ -758,10 +880,12 @@
 
 [drivesys.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
 [etherdump]
 type=EtherDump
+eventq_index=0
 file=ethertrace
 maxlen=96
 
@@ -770,6 +894,7 @@
 delay=0
 delay_var=0
 dump=etherdump
+eventq_index=0
 speed=8000.000000
 int0=testsys.tsunami.ethernet.interface
 int1=drivesys.tsunami.ethernet.interface
@@ -777,7 +902,9 @@
 [root]
 type=Root
 children=drivesys etherdump etherlink testsys
+eventq_index=0
 full_system=true
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -789,16 +916,17 @@
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=testsys.clk_domain
-console=/dist/m5/system/binaries/console
+console=/dist/binaries/console
+eventq_index=0
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
 mem_ranges=0:134217727
 memories=testsys.physmem
 num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
-readfile=/z/m5/regression/zizzer/gem5/configs/boot/netperf-stream-client.rcS
+pal=/dist/binaries/ts_osfpal
+readfile=/work/gem5.ext/configs/boot/netperf-stream-client.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -815,6 +943,7 @@
 type=Bridge
 clk_domain=testsys.clk_domain
 delay=50000
+eventq_index=0
 ranges=8796093022208:18446744073709551615
 req_size=16
 resp_size=16
@@ -824,6 +953,7 @@
 [testsys.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=testsys.voltage_domain
 
 [testsys.cpu]
@@ -836,6 +966,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=testsys.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -866,43 +997,53 @@
 [testsys.cpu.clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=testsys.voltage_domain
 
 [testsys.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [testsys.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [testsys.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=testsys
 
 [testsys.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [testsys.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [testsys.disk0]
 type=IdeDisk
 children=image
 delay=1000000
 driveID=master
+eventq_index=0
 image=testsys.disk0.image
 
 [testsys.disk0.image]
 type=CowDiskImage
 children=child
 child=testsys.disk0.image.child
+eventq_index=0
 image_file=
 read_only=false
 table_size=65536
 
 [testsys.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+eventq_index=0
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [testsys.disk2]
@@ -910,29 +1051,34 @@
 children=image
 delay=1000000
 driveID=master
+eventq_index=0
 image=testsys.disk2.image
 
 [testsys.disk2.image]
 type=CowDiskImage
 children=child
 child=testsys.disk2.image.child
+eventq_index=0
 image_file=
 read_only=false
 table_size=65536
 
 [testsys.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+eventq_index=0
+image_file=/dist/disks/linux-bigswap2.img
 read_only=true
 
 [testsys.intrctrl]
 type=IntrControl
+eventq_index=0
 sys=testsys
 
 [testsys.iobridge]
 type=Bridge
 clk_domain=testsys.clk_domain
 delay=50000
+eventq_index=0
 ranges=0:134217727
 req_size=16
 resp_size=16
@@ -942,6 +1088,7 @@
 [testsys.iobus]
 type=NoncoherentBus
 clk_domain=testsys.clk_domain
+eventq_index=0
 header_cycles=1
 use_default_range=true
 width=8
@@ -953,6 +1100,7 @@
 type=CoherentBus
 children=badaddr_responder
 clk_domain=testsys.clk_domain
+eventq_index=0
 header_cycles=1
 system=testsys
 use_default_range=false
@@ -964,6 +1112,7 @@
 [testsys.membus.badaddr_responder]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -983,6 +1132,7 @@
 bandwidth=73.000000
 clk_domain=testsys.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -994,15 +1144,18 @@
 type=SimpleDisk
 children=disk
 disk=testsys.simple_disk.disk
+eventq_index=0
 system=testsys
 
 [testsys.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+eventq_index=0
+image_file=/dist/disks/linux-latest.img
 read_only=true
 
 [testsys.terminal]
 type=Terminal
+eventq_index=0
 intr_control=testsys.intrctrl
 number=0
 output=true
@@ -1011,6 +1164,7 @@
 [testsys.tsunami]
 type=Tsunami
 children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+eventq_index=0
 intrctrl=testsys.intrctrl
 system=testsys
 
@@ -1019,6 +1173,7 @@
 clk_domain=testsys.clk_domain
 cpu=testsys.cpu
 disk=testsys.simple_disk
+eventq_index=0
 pio_addr=8804682956800
 pio_latency=100000
 platform=testsys.tsunami
@@ -1029,6 +1184,7 @@
 [testsys.tsunami.cchip]
 type=TsunamiCChip
 clk_domain=testsys.clk_domain
+eventq_index=0
 pio_addr=8803072344064
 pio_latency=100000
 system=testsys
@@ -1058,6 +1214,7 @@
 BAR5Size=0
 BIST=0
 CacheLineSize=0
+CapabilityPtr=0
 CardbusCIS=0
 ClassCode=2
 Command=0
@@ -1067,8 +1224,40 @@
 InterruptLine=30
 InterruptPin=1
 LatencyTimer=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
 MaximumLatency=52
 MinimumGrant=176
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
 ProgIF=0
 Revision=0
 Status=656
@@ -1085,6 +1274,7 @@
 dma_read_factor=0
 dma_write_delay=0
 dma_write_factor=0
+eventq_index=0
 hardware_address=00:90:00:00:00:01
 intr_delay=10000000
 pci_bus=0
@@ -1109,11 +1299,13 @@
 [testsys.tsunami.ethernet.clk_domain]
 type=SrcClockDomain
 clock=2000
+eventq_index=0
 voltage_domain=testsys.voltage_domain
 
 [testsys.tsunami.fake_OROM]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8796093677568
 pio_latency=100000
@@ -1131,6 +1323,7 @@
 [testsys.tsunami.fake_ata0]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848432
 pio_latency=100000
@@ -1148,6 +1341,7 @@
 [testsys.tsunami.fake_ata1]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848304
 pio_latency=100000
@@ -1165,6 +1359,7 @@
 [testsys.tsunami.fake_pnp_addr]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848569
 pio_latency=100000
@@ -1182,6 +1377,7 @@
 [testsys.tsunami.fake_pnp_read0]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848451
 pio_latency=100000
@@ -1199,6 +1395,7 @@
 [testsys.tsunami.fake_pnp_read1]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848515
 pio_latency=100000
@@ -1216,6 +1413,7 @@
 [testsys.tsunami.fake_pnp_read2]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848579
 pio_latency=100000
@@ -1233,6 +1431,7 @@
 [testsys.tsunami.fake_pnp_read3]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848643
 pio_latency=100000
@@ -1250,6 +1449,7 @@
 [testsys.tsunami.fake_pnp_read4]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848707
 pio_latency=100000
@@ -1267,6 +1467,7 @@
 [testsys.tsunami.fake_pnp_read5]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848771
 pio_latency=100000
@@ -1284,6 +1485,7 @@
 [testsys.tsunami.fake_pnp_read6]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848835
 pio_latency=100000
@@ -1301,6 +1503,7 @@
 [testsys.tsunami.fake_pnp_read7]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848899
 pio_latency=100000
@@ -1318,6 +1521,7 @@
 [testsys.tsunami.fake_pnp_write]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615850617
 pio_latency=100000
@@ -1335,6 +1539,7 @@
 [testsys.tsunami.fake_ppc]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848891
 pio_latency=100000
@@ -1352,6 +1557,7 @@
 [testsys.tsunami.fake_sm_chip]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848816
 pio_latency=100000
@@ -1369,6 +1575,7 @@
 [testsys.tsunami.fake_uart1]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848696
 pio_latency=100000
@@ -1386,6 +1593,7 @@
 [testsys.tsunami.fake_uart2]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848936
 pio_latency=100000
@@ -1403,6 +1611,7 @@
 [testsys.tsunami.fake_uart3]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848680
 pio_latency=100000
@@ -1420,6 +1629,7 @@
 [testsys.tsunami.fake_uart4]
 type=IsaFake
 clk_domain=testsys.clk_domain
+eventq_index=0
 fake_mem=false
 pio_addr=8804615848944
 pio_latency=100000
@@ -1438,6 +1648,7 @@
 type=BadDevice
 clk_domain=testsys.clk_domain
 devicename=FrameBuffer
+eventq_index=0
 pio_addr=8804615848912
 pio_latency=100000
 system=testsys
@@ -1465,6 +1676,7 @@
 BAR5Size=0
 BIST=0
 CacheLineSize=0
+CapabilityPtr=0
 CardbusCIS=0
 ClassCode=1
 Command=0
@@ -1474,8 +1686,40 @@
 InterruptLine=31
 InterruptPin=1
 LatencyTimer=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
 MaximumLatency=0
 MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
 ProgIF=133
 Revision=0
 Status=640
@@ -1487,6 +1731,7 @@
 config_latency=20000
 ctrl_offset=0
 disks=testsys.disk0 testsys.disk2
+eventq_index=0
 io_shift=0
 pci_bus=0
 pci_dev=0
@@ -1501,6 +1746,7 @@
 [testsys.tsunami.io]
 type=TsunamiIO
 clk_domain=testsys.clk_domain
+eventq_index=0
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=100000
@@ -1513,6 +1759,7 @@
 [testsys.tsunami.pchip]
 type=TsunamiPChip
 clk_domain=testsys.clk_domain
+eventq_index=0
 pio_addr=8802535473152
 pio_latency=100000
 system=testsys
@@ -1523,6 +1770,7 @@
 type=PciConfigAll
 bus=0
 clk_domain=testsys.clk_domain
+eventq_index=0
 pio_addr=0
 pio_latency=30000
 platform=testsys.tsunami
@@ -1533,6 +1781,7 @@
 [testsys.tsunami.uart]
 type=Uart8250
 clk_domain=testsys.clk_domain
+eventq_index=0
 pio_addr=8804615848952
 pio_latency=100000
 platform=testsys.tsunami
@@ -1542,5 +1791,6 @@
 
 [testsys.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
index 22a941a..c0d08bd 100755
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr

@@ -1,8 +1,5 @@
 warn: Sockets disabled, not accepting terminal connections
-warn: CoherentBus testsys.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
-warn: CoherentBus drivesys.membus has no snooping ports attached!
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 warn: Obsolete M5 ivlb instruction encountered.
-hack: be nice to actually delete the event here

diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
index af627b8..75ac3eb 100755
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout

@@ -1,16 +1,14 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:52
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:25:12
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /dist/binaries/vmlinux
       0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /dist/binaries/vmlinux
       0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 4321621592000 because checkpoint

diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
index 4ccc9d7..cf63db3 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                200409284500                       # Number of ticks simulated
 final_tick                               4321214250500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                               21337245                       # Simulator instruction rate (inst/s)
-host_op_rate                                 21337231                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8163912733                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 473328                       # Number of bytes of host memory used
-host_seconds                                    24.55                       # Real time elapsed on the host
+host_inst_rate                               22333008                       # Simulator instruction rate (inst/s)
+host_op_rate                                 22332995                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             8544906534                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 473604                       # Number of bytes of host memory used
+host_seconds                                    23.45                       # Real time elapsed on the host
 sim_insts                                   523790075                       # Number of instructions simulated
 sim_ops                                     523790075                       # Number of ops (including micro ops) simulated
+testsys.voltage_domain.voltage                      1                       # Voltage in Volts
+testsys.clk_domain.clock                         1000                       # Clock period in ticks
 testsys.physmem.bytes_read::cpu.inst         81046720                       # Number of bytes read from this memory
 testsys.physmem.bytes_read::cpu.data         27826276                       # Number of bytes read from this memory
 testsys.physmem.bytes_read::tsunami.ethernet     57260496                       # Number of bytes read from this memory
@@ -55,6 +57,7 @@
 testsys.disk2.dma_write_full_pages                  0                       # Number of full page size DMA writes.
 testsys.disk2.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
 testsys.disk2.dma_write_txs                         0                       # Number of DMA write transactions.
+testsys.cpu.clk_domain.clock                      500                       # Clock period in ticks
 testsys.cpu.dtb.fetch_hits                          0                       # ITB hits
 testsys.cpu.dtb.fetch_misses                        0                       # ITB misses
 testsys.cpu.dtb.fetch_acv                           0                       # ITB acv
@@ -178,6 +181,7 @@
 testsys.cpu.kern.mode_ticks::user           533068000     32.16%     92.17% # number of ticks spent at the given mode
 testsys.cpu.kern.mode_ticks::idle           129740500      7.83%    100.00% # number of ticks spent at the given mode
 testsys.cpu.kern.swap_context                     438                       # number of times the context was actually changed
+testsys.tsunami.ethernet.clk_domain.clock         2000                       # Clock period in ticks
 testsys.tsunami.ethernet.txBytes                  960                       # Bytes Transmitted
 testsys.tsunami.ethernet.rxBytes                  798                       # Bytes Received
 testsys.tsunami.ethernet.txPackets                  8                       # Number of Packets Transmitted
@@ -229,6 +233,8 @@
 testsys.tsunami.ethernet.droppedPackets             0                       # number of packets dropped
 testsys.iobus.throughput                    290423421                       # Throughput (bytes/s)
 testsys.iobus.data_through_bus               58203550                       # Total data (bytes)
+drivesys.voltage_domain.voltage                     1                       # Voltage in Volts
+drivesys.clk_domain.clock                        1000                       # Clock period in ticks
 drivesys.physmem.bytes_read::cpu.inst        76205572                       # Number of bytes read from this memory
 drivesys.physmem.bytes_read::cpu.data        26284292                       # Number of bytes read from this memory
 drivesys.physmem.bytes_read::tsunami.ethernet     57260526                       # Number of bytes read from this memory
@@ -273,6 +279,7 @@
 drivesys.disk2.dma_write_full_pages                 0                       # Number of full page size DMA writes.
 drivesys.disk2.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
 drivesys.disk2.dma_write_txs                        0                       # Number of DMA write transactions.
+drivesys.cpu.clk_domain.clock                     250                       # Clock period in ticks
 drivesys.cpu.dtb.fetch_hits                         0                       # ITB hits
 drivesys.cpu.dtb.fetch_misses                       0                       # ITB misses
 drivesys.cpu.dtb.fetch_acv                          0                       # ITB acv
@@ -386,6 +393,7 @@
 drivesys.cpu.kern.mode_ticks::user          319668250     10.78%     13.41% # number of ticks spent at the given mode
 drivesys.cpu.kern.mode_ticks::idle         2567942000     86.59%    100.00% # number of ticks spent at the given mode
 drivesys.cpu.kern.swap_context                     72                       # number of times the context was actually changed
+drivesys.tsunami.ethernet.clk_domain.clock         2000                       # Clock period in ticks
 drivesys.tsunami.ethernet.txBytes                 798                       # Bytes Transmitted
 drivesys.tsunami.ethernet.rxBytes                 960                       # Bytes Received
 drivesys.tsunami.ethernet.txPackets                 5                       # Number of Packets Transmitted
@@ -445,13 +453,15 @@
 sim_ticks                                   407341500                       # Number of ticks simulated
 final_tick                               4321621592000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                            10977168844                       # Simulator instruction rate (inst/s)
-host_op_rate                              10973505866                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             8529941400                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 473328                       # Number of bytes of host memory used
+host_inst_rate                            11306223920                       # Simulator instruction rate (inst/s)
+host_op_rate                              11302970418                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             8786485437                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 473604                       # Number of bytes of host memory used
 host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                   523862353                       # Number of instructions simulated
 sim_ops                                     523862353                       # Number of ops (including micro ops) simulated
+testsys.voltage_domain.voltage                      1                       # Voltage in Volts
+testsys.clk_domain.clock                         1000                       # Clock period in ticks
 testsys.physmem.bytes_read::cpu.inst           144504                       # Number of bytes read from this memory
 testsys.physmem.bytes_read::cpu.data            49936                       # Number of bytes read from this memory
 testsys.physmem.bytes_read::tsunami.ethernet       116376                       # Number of bytes read from this memory
@@ -493,6 +503,7 @@
 testsys.disk2.dma_write_full_pages                  0                       # Number of full page size DMA writes.
 testsys.disk2.dma_write_bytes                       0                       # Number of bytes transfered via DMA writes.
 testsys.disk2.dma_write_txs                         0                       # Number of DMA write transactions.
+testsys.cpu.clk_domain.clock                      500                       # Clock period in ticks
 testsys.cpu.dtb.fetch_hits                          0                       # ITB hits
 testsys.cpu.dtb.fetch_misses                        0                       # ITB misses
 testsys.cpu.dtb.fetch_acv                           0                       # ITB acv
@@ -588,6 +599,7 @@
 testsys.cpu.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
 testsys.cpu.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
 testsys.cpu.kern.swap_context                       0                       # number of times the context was actually changed
+testsys.tsunami.ethernet.clk_domain.clock         2000                       # Clock period in ticks
 testsys.tsunami.ethernet.descDMAReads            4849                       # Number of descriptors the device read w/ DMA
 testsys.tsunami.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
 testsys.tsunami.ethernet.descDmaReadBytes       116376                       # number of descriptor bytes read w/ DMA
@@ -621,6 +633,8 @@
 testsys.tsunami.ethernet.droppedPackets             0                       # number of packets dropped
 testsys.iobus.throughput                    290429529                       # Throughput (bytes/s)
 testsys.iobus.data_through_bus                 118304                       # Total data (bytes)
+drivesys.voltage_domain.voltage                     1                       # Voltage in Volts
+drivesys.clk_domain.clock                        1000                       # Clock period in ticks
 drivesys.physmem.bytes_read::cpu.inst          144608                       # Number of bytes read from this memory
 drivesys.physmem.bytes_read::cpu.data           49952                       # Number of bytes read from this memory
 drivesys.physmem.bytes_read::tsunami.ethernet       116400                       # Number of bytes read from this memory
@@ -662,6 +676,7 @@
 drivesys.disk2.dma_write_full_pages                 0                       # Number of full page size DMA writes.
 drivesys.disk2.dma_write_bytes                      0                       # Number of bytes transfered via DMA writes.
 drivesys.disk2.dma_write_txs                        0                       # Number of DMA write transactions.
+drivesys.cpu.clk_domain.clock                     250                       # Clock period in ticks
 drivesys.cpu.dtb.fetch_hits                         0                       # ITB hits
 drivesys.cpu.dtb.fetch_misses                       0                       # ITB misses
 drivesys.cpu.dtb.fetch_acv                          0                       # ITB acv
@@ -757,6 +772,7 @@
 drivesys.cpu.kern.mode_ticks::user                  0                       # number of ticks spent at the given mode
 drivesys.cpu.kern.mode_ticks::idle                  0                       # number of ticks spent at the given mode
 drivesys.cpu.kern.swap_context                      0                       # number of times the context was actually changed
+drivesys.tsunami.ethernet.clk_domain.clock         2000                       # Clock period in ticks
 drivesys.tsunami.ethernet.descDMAReads           4850                       # Number of descriptors the device read w/ DMA
 drivesys.tsunami.ethernet.descDMAWrites             0                       # Number of descriptors the device wrote w/ DMA
 drivesys.tsunami.ethernet.descDmaReadBytes       116400                       # number of descriptor bytes read w/ DMA

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
index 8be59c8..38d5b70 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -56,6 +60,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fetchBuffSize=4
 function_trace=false
 function_trace_start=0
@@ -90,6 +95,7 @@
 RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
+eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
 instShiftAmt=2
@@ -105,6 +111,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -113,6 +120,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -127,11 +135,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -140,6 +151,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -148,6 +160,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -162,17 +175,23 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -181,6 +200,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -189,6 +209,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -203,12 +224,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -218,6 +242,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -227,7 +252,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -241,11 +267,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -265,6 +293,7 @@
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -276,17 +305,21 @@
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
index b50e34b..b1e32f7 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout

@@ -1,14 +1,12 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:26
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:08
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 25046000 because target called exit()
+Exiting @ tick 25485000 because target called exit()

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
index 3b67933..116ba4c 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    25485000                       # Number of ticks simulated
 final_tick                                   25485000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  27492                       # Simulator instruction rate (inst/s)
-host_op_rate                                    27490                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              109632626                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225100                       # Number of bytes of host memory used
-host_seconds                                     0.23                       # Real time elapsed on the host
+host_inst_rate                                  24806                       # Simulator instruction rate (inst/s)
+host_op_rate                                    24805                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               98922905                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229760                       # Number of bytes of host memory used
+host_seconds                                     0.26                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             19200                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data             10752                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                29952                       # Number of bytes read from this memory
@@ -214,6 +216,7 @@
 system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            4374750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             17.2                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    1632                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1160                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               706                       # Number of conditional branches incorrect
@@ -325,6 +328,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   142.311081                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.069488                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.069488                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          301                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          175                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.146973                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              2131                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             2131                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst          560                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total             560                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst           560                       # number of demand (read+write) hits
@@ -430,6 +439,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004344                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001732                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.006076                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          395                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          240                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012054                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4228                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4228                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
@@ -553,6 +568,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data   103.493430                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.025267                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.025267                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          168                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          128                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.041016                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              4264                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4264                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         1086                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1086                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          515                       # number of WriteReq hits

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
index 07eaff0..6e7555e 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini

@@ -159,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -504,6 +506,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -520,6 +523,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -529,6 +533,7 @@
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -550,6 +555,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -566,6 +572,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -592,7 +599,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
index 589b57e..5b34c94 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout

@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 16 2013 01:34:33
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:08
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 20671000 because target called exit()
+Exiting @ tick 21065000 because target called exit()

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index cfed150..7833bae 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    21065000                       # Number of ticks simulated
 final_tick                                   21065000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  36663                       # Simulator instruction rate (inst/s)
-host_op_rate                                    36659                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              121177991                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 273132                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
+host_inst_rate                                  40027                       # Simulator instruction rate (inst/s)
+host_op_rate                                    40023                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              132300521                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 230780                       # Number of bytes of host memory used
+host_seconds                                     0.16                       # Real time elapsed on the host
 sim_insts                                        6372                       # Number of instructions simulated
 sim_ops                                          6372                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             20032                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data             11136                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                31168                       # Number of bytes read from this memory
@@ -214,6 +216,7 @@
 system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            4556000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             21.6                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    2883                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1697                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               511                       # Number of conditional branches incorrect
@@ -544,6 +547,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   159.548856                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.077905                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.077905                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          314                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          143                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.153320                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              5078                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             5078                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         1893                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            1893                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          1893                       # number of demand (read+write) hits
@@ -630,6 +639,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004872                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001825                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.006696                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          414                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          232                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012634                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4399                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4399                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
@@ -753,6 +768,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data   107.351368                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.026209                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.026209                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          174                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.042480                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              5692                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5692                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         1724                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1724                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          506                       # number of WriteReq hits

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
index 3d9687a..06ea191 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,26 @@
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +108,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +123,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +142,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +152,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
index 7edd901..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr

@@ -1,3 +1 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
index 1fb01db..1ccb735 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:26
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:08
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
index 469297f..26873a7 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                     3208000                       # Number of ticks simulated
 final_tick                                    3208000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                   2502                       # Simulator instruction rate (inst/s)
-host_op_rate                                     2502                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1255935                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215792                       # Number of bytes of host memory used
-host_seconds                                     2.55                       # Real time elapsed on the host
+host_inst_rate                                  44230                       # Simulator instruction rate (inst/s)
+host_op_rate                                    44225                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               22200446                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220024                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             25600                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8788                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                34388                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                  12806733167                       # Throughput (bytes/s)
 system.membus.data_through_bus                  41084                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
index 0a3882b..1d40a69 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini

@@ -88,6 +88,7 @@
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -107,7 +108,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
index bbc0c79..86244d4 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr

@@ -3,4 +3,3 @@
 warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
index 5fac9bc..703a818 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout

@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:27:02
-gem5 started Sep 22 2013 05:27:12
-gem5 executing on zizzer
-command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
+gem5 compiled Jan 22 2014 16:37:52
+gem5 started Jan 22 2014 17:25:49
+gem5 executing on u200540-lin
+command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
index dd7fe91..9dc55b6 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt

@@ -4,13 +4,16 @@
 sim_ticks                                      138616                       # Number of ticks simulated
 final_tick                                     138616                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  20823                       # Simulator instruction rate (inst/s)
-host_op_rate                                    20821                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 451640                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 170972                       # Number of bytes of host memory used
-host_seconds                                     0.31                       # Real time elapsed on the host
+host_inst_rate                                  26295                       # Simulator instruction rate (inst/s)
+host_op_rate                                    26294                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 570348                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 126360                       # Number of bytes of host memory used
+host_seconds                                     0.24                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
 system.ruby.delayHist::samples                   9645                       # delay histogram for all message
@@ -100,6 +103,7 @@
 system.ruby.network.routers1.msg_bytes.Writeback_Data::0        10440                      
 system.ruby.network.routers1.msg_bytes.Writeback_Data::1        10152                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::0         2328                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.dir_cntrl0.memBuffer.memReq          1737                       # Total number of memory requests
 system.ruby.dir_cntrl0.memBuffer.memRead         1460                       # Number of memory reads
 system.ruby.dir_cntrl0.memBuffer.memWrite          277                       # Number of memory writes
@@ -149,6 +153,7 @@
 system.ruby.network.msg_byte.Response_Control       114288                      
 system.ruby.network.msg_byte.Writeback_Data        61776                      
 system.ruby.network.msg_byte.Writeback_Control         6984                      
+system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 454f386..055a078 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -68,24 +73,31 @@
 [system.cpu.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -95,7 +107,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,6 +124,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -119,18 +133,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=1
 random_seed=1234
 randomization=false
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -138,9 +156,10 @@
 children=directory memBuffer
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=2
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=6
+eventq_index=0
 memBuffer=system.ruby.dir_cntrl0.memBuffer
 number_of_TBEs=256
 peer=Null
@@ -151,6 +170,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -167,6 +187,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -186,7 +207,8 @@
 L1Icache=system.ruby.l1_cntrl0.L1Icache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
 l2_select_num_bits=0
 number_of_TBEs=256
 peer=Null
@@ -204,6 +226,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -218,6 +241,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -233,6 +257,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -250,7 +275,8 @@
 L2cache=system.ruby.l2_cntrl0.L2cache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
+eventq_index=0
 number_of_TBEs=256
 peer=Null
 recycle_latency=10
@@ -265,6 +291,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
@@ -278,6 +305,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -287,6 +315,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
 number_of_virtual_networks=10
@@ -297,6 +326,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -306,6 +336,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l2_cntrl0
 int_node=system.ruby.network.routers1
 latency=1
@@ -315,6 +346,7 @@
 [system.ruby.network.ext_links2]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers2
 latency=1
@@ -324,6 +356,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=3
 node_a=system.ruby.network.routers0
@@ -333,6 +366,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=4
 node_a=system.ruby.network.routers1
@@ -342,6 +376,7 @@
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=5
 node_a=system.ruby.network.routers2
@@ -351,38 +386,36 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
 [system.ruby.network.routers3]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=3
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -394,5 +427,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
index bbc0c79..86244d4 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr

@@ -3,4 +3,3 @@
 warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
index 7aebf91..e446403 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:36:12
-gem5 started Sep 22 2013 05:36:34
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:42:56
+gem5 started Jan 22 2014 17:26:22
+gem5 executing on u200540-lin
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 6769cc2..97b9e8b 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt

@@ -4,13 +4,16 @@
 sim_ticks                                      117611                       # Number of ticks simulated
 final_tick                                     117611                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  18637                       # Simulator instruction rate (inst/s)
-host_op_rate                                    18636                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 342978                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 174220                       # Number of bytes of host memory used
-host_seconds                                     0.34                       # Real time elapsed on the host
+host_inst_rate                                  23182                       # Simulator instruction rate (inst/s)
+host_op_rate                                    23181                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 426626                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 130676                       # Number of bytes of host memory used
+host_seconds                                     0.28                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            1                      
 system.ruby.outstanding_req_hist::max_bucket            9                      
 system.ruby.outstanding_req_hist::samples         8449                      
@@ -82,6 +85,7 @@
 system.ruby.network.routers1.msg_bytes.Writeback_Control::1        17488                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::2         7192                      
 system.ruby.network.routers1.msg_bytes.Unblock_Control::2        19768                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.dir_cntrl0.memBuffer.memReq          1303                       # Total number of memory requests
 system.ruby.dir_cntrl0.memBuffer.memRead         1109                       # Number of memory reads
 system.ruby.dir_cntrl0.memBuffer.memWrite          194                       # Number of memory writes
@@ -139,6 +143,7 @@
 system.ruby.network.msg_byte.Writeback_Data       334368                      
 system.ruby.network.msg_byte.Writeback_Control       139032                      
 system.ruby.network.msg_byte.Unblock_Control        59304                      
+system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index 98cbedd..c839235 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -68,24 +73,31 @@
 [system.cpu.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -95,7 +107,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,6 +124,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -119,18 +133,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=1
 random_seed=1234
 randomization=false
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -138,10 +156,11 @@
 children=directory memBuffer
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=2
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=5
 distributed_persistent=true
+eventq_index=0
 fixed_timeout_latency=100
 l2_select_num_bits=0
 memBuffer=system.ruby.dir_cntrl0.memBuffer
@@ -155,6 +174,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -171,6 +191,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -191,8 +212,9 @@
 N_tokens=2
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
 dynamic_timeout_enabled=true
+eventq_index=0
 fixed_timeout_latency=300
 l1_request_latency=2
 l1_response_latency=2
@@ -215,6 +237,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -229,6 +252,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -244,6 +268,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -262,7 +287,8 @@
 N_tokens=2
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
+eventq_index=0
 filtering_enabled=true
 l2_request_latency=5
 l2_response_latency=5
@@ -278,6 +304,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
@@ -291,6 +318,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -300,6 +328,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
 number_of_virtual_networks=10
@@ -310,6 +339,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -319,6 +349,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l2_cntrl0
 int_node=system.ruby.network.routers1
 latency=1
@@ -328,6 +359,7 @@
 [system.ruby.network.ext_links2]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers2
 latency=1
@@ -337,6 +369,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=3
 node_a=system.ruby.network.routers0
@@ -346,6 +379,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=4
 node_a=system.ruby.network.routers1
@@ -355,6 +389,7 @@
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=5
 node_a=system.ruby.network.routers2
@@ -364,38 +399,36 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
 [system.ruby.network.routers3]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=3
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -407,5 +440,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
index bbc0c79..86244d4 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr

@@ -3,4 +3,3 @@
 warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
index 972ce6e..05cd140 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:44:48
-gem5 started Sep 22 2013 05:44:59
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:47:59
+gem5 started Jan 22 2014 17:27:26
+gem5 executing on u200540-lin
 command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 5443611..47e7c5b 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt

@@ -4,13 +4,16 @@
 sim_ticks                                      113627                       # Number of ticks simulated
 final_tick                                     113627                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  15419                       # Simulator instruction rate (inst/s)
-host_op_rate                                    15419                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 274163                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 171088                       # Number of bytes of host memory used
-host_seconds                                     0.41                       # Real time elapsed on the host
+host_inst_rate                                  25426                       # Simulator instruction rate (inst/s)
+host_op_rate                                    25424                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 452072                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 127540                       # Number of bytes of host memory used
+host_seconds                                     0.25                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            1                      
 system.ruby.outstanding_req_hist::max_bucket            9                      
 system.ruby.outstanding_req_hist::samples         8449                      
@@ -76,6 +79,7 @@
 system.ruby.network.routers1.msg_bytes.Response_Control::4            8                      
 system.ruby.network.routers1.msg_bytes.Writeback_Data::4       113976                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::4         7736                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.dir_cntrl0.memBuffer.memReq          1407                       # Total number of memory requests
 system.ruby.dir_cntrl0.memBuffer.memRead         1178                       # Number of memory reads
 system.ruby.dir_cntrl0.memBuffer.memWrite          229                       # Number of memory writes
@@ -125,6 +129,7 @@
 system.ruby.network.msg_byte.Response_Control           24                      
 system.ruby.network.msg_byte.Writeback_Data       341928                      
 system.ruby.network.msg_byte.Writeback_Control        23208                      
+system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index 5efa528..bbaaafb 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -68,24 +73,31 @@
 [system.cpu.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -95,7 +107,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,6 +124,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -119,18 +133,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=1
 random_seed=1234
 randomization=false
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -138,8 +156,9 @@
 children=directory memBuffer probeFilter
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
+eventq_index=0
 full_bit_dir_enabled=false
 memBuffer=system.ruby.dir_cntrl0.memBuffer
 memory_controller_latency=2
@@ -154,6 +173,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -170,6 +190,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -187,6 +208,7 @@
 assoc=4
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=1
 replacement_policy=PSEUDO_LRU
@@ -205,7 +227,8 @@
 buffer_size=0
 cache_response_latency=10
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
 issue_latency=2
 l2_cache_hit_latency=10
 no_mig_atomic=true
@@ -223,6 +246,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -237,6 +261,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -251,6 +276,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
@@ -266,6 +292,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -281,6 +308,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -290,6 +318,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
 number_of_virtual_networks=10
@@ -300,6 +329,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -309,6 +339,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers1
 latency=1
@@ -318,6 +349,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=2
 node_a=system.ruby.network.routers0
@@ -327,6 +359,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=3
 node_a=system.ruby.network.routers1
@@ -336,32 +369,29 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -373,5 +403,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
index bbc0c79..86244d4 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr

@@ -3,4 +3,3 @@
 warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
index 2f946fb..74d9e58 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:17:28
-gem5 started Sep 22 2013 05:18:00
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:32:54
+gem5 started Jan 22 2014 17:25:16
+gem5 executing on u200540-lin
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index da74554..afdd49a 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt

@@ -4,13 +4,16 @@
 sim_ticks                                       93341                       # Number of ticks simulated
 final_tick                                      93341                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  30230                       # Simulator instruction rate (inst/s)
-host_op_rate                                    30227                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 441501                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 171020                       # Number of bytes of host memory used
-host_seconds                                     0.21                       # Real time elapsed on the host
+host_inst_rate                                  34391                       # Simulator instruction rate (inst/s)
+host_op_rate                                    34389                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 502293                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 127476                       # Number of bytes of host memory used
+host_seconds                                     0.19                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            1                      
 system.ruby.outstanding_req_hist::max_bucket            9                      
 system.ruby.outstanding_req_hist::samples         8449                      
@@ -43,6 +46,7 @@
 system.ruby.miss_latency_hist            |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |        1098     94.74%     94.74% |           9      0.78%     95.51% |          24      2.07%     97.58% |           0      0.00%     97.58% |          27      2.33%     99.91% |           1      0.09%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total             1159                      
 system.ruby.Directory.incomplete_times           1158                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.l1_cntrl0.L1Dcache.demand_hits         1332                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          716                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Dcache.demand_accesses         2048                       # Number of cache demand accesses
@@ -124,6 +128,7 @@
 system.ruby.network.msg_byte.Writeback_Data        47520                      
 system.ruby.network.msg_byte.Writeback_Control        77016                      
 system.ruby.network.msg_byte.Unblock_Control        27816                      
+system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index 5c6bf17..080d250 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -68,24 +73,31 @@
 [system.cpu.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -95,7 +107,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,6 +124,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -119,18 +133,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=1
 random_seed=1234
 randomization=false
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -138,9 +156,10 @@
 children=directory memBuffer
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
+eventq_index=0
 memBuffer=system.ruby.dir_cntrl0.memBuffer
 number_of_TBEs=256
 peer=Null
@@ -151,6 +170,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -167,6 +187,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -186,7 +207,8 @@
 cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
 issue_latency=2
 number_of_TBEs=256
 peer=Null
@@ -202,6 +224,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -217,6 +240,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.cacheMemory
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -232,6 +256,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -241,6 +266,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
 number_of_virtual_networks=10
@@ -251,6 +277,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -260,6 +287,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers1
 latency=1
@@ -269,6 +297,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=2
 node_a=system.ruby.network.routers0
@@ -278,6 +307,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=3
 node_a=system.ruby.network.routers1
@@ -287,32 +317,29 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -324,5 +351,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
index bbc0c79..86244d4 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr

@@ -3,4 +3,3 @@
 warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
index cedef18..e7d414e 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:27
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:20
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index 6d4e698..19e4fff 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt

@@ -4,13 +4,16 @@
 sim_ticks                                      143853                       # Number of ticks simulated
 final_tick                                     143853                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  26416                       # Simulator instruction rate (inst/s)
-host_op_rate                                    26414                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 594577                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 170576                       # Number of bytes of host memory used
-host_seconds                                     0.24                       # Real time elapsed on the host
+host_inst_rate                                  41580                       # Simulator instruction rate (inst/s)
+host_op_rate                                    41576                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 935887                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 126996                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
 system.ruby.delayHist::samples                   3456                       # delay histogram for all message
@@ -47,6 +50,7 @@
 system.ruby.miss_latency_hist            |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         336     19.42%     19.42% |        1251     72.31%     91.73% |         136      7.86%     99.60% |           5      0.29%     99.88% |           2      0.12%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total             1730                      
 system.ruby.Directory.incomplete_times           1729                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         6718                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses         1730                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses         8448                       # Number of cache demand accesses
@@ -99,6 +103,7 @@
 system.ruby.network.msg_byte.Data              372816                      
 system.ruby.network.msg_byte.Response_Data       373680                      
 system.ruby.network.msg_byte.Writeback_Control        41424                      
+system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
index 595a815..b0e615a 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,23 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -147,6 +165,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +174,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +189,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +207,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +217,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +232,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +251,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +261,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
index b5f87b7..03ecf72 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:26
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:16
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
index 6038d0a..84f056a 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    32544000                       # Number of ticks simulated
 final_tick                                   32544000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  27670                       # Simulator instruction rate (inst/s)
-host_op_rate                                    27667                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              140894748                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224272                       # Number of bytes of host memory used
-host_seconds                                     0.23                       # Real time elapsed on the host
+host_inst_rate                                  61527                       # Simulator instruction rate (inst/s)
+host_op_rate                                    61510                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              313188739                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228704                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             17792                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data             10752                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                28544                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@
 system.membus.reqLayer0.utilization               1.4                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            4014000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             12.3                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -106,6 +109,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   127.998991                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.062500                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.062500                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          279                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          103                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.136230                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses             13081                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            13081                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         6122                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            6122                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          6122                       # number of demand (read+write) hits
@@ -186,6 +195,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003907                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001724                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.005630                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          373                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          122                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          251                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011383                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4022                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4022                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
@@ -309,6 +324,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data   103.762109                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.025333                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.025333                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          168                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          141                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.041016                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              4264                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4264                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         1088                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1088                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          792                       # number of WriteReq hits

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index b9dbe7d..15208c0 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -64,6 +68,8 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
+fetchBufferSize=64
 fetchToDecodeDelay=1
 fetchTrapLatency=1
 fetchWidth=8
@@ -128,6 +134,7 @@
 RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
+eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
 instShiftAmt=2
@@ -143,6 +150,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -151,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -165,26 +174,32 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.fuPool]
 type=FUPool
 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+eventq_index=0
 
 [system.cpu.fuPool.FUList0]
 type=FUDesc
 children=opList
 count=6
+eventq_index=0
 opList=system.cpu.fuPool.FUList0.opList
 
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=IntAlu
 opLat=1
@@ -193,16 +208,19 @@
 type=FUDesc
 children=opList0 opList1
 count=2
+eventq_index=0
 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=IntMult
 opLat=3
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=19
 opClass=IntDiv
 opLat=20
@@ -211,22 +229,26 @@
 type=FUDesc
 children=opList0 opList1 opList2
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatAdd
 opLat=2
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatCmp
 opLat=2
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatCvt
 opLat=2
@@ -235,22 +257,26 @@
 type=FUDesc
 children=opList0 opList1 opList2
 count=2
+eventq_index=0
 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatMult
 opLat=4
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=12
 opClass=FloatDiv
 opLat=12
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
+eventq_index=0
 issueLat=24
 opClass=FloatSqrt
 opLat=24
@@ -259,10 +285,12 @@
 type=FUDesc
 children=opList
 count=0
+eventq_index=0
 opList=system.cpu.fuPool.FUList4.opList
 
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemRead
 opLat=1
@@ -271,124 +299,145 @@
 type=FUDesc
 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAdd
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAddAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAlu
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdCmp
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdCvt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMisc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMult
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMultAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdShift
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdShiftAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdSqrt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatAdd
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatAlu
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatCmp
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatCvt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatDiv
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMisc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMult
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
@@ -397,10 +446,12 @@
 type=FUDesc
 children=opList
 count=0
+eventq_index=0
 opList=system.cpu.fuPool.FUList6.opList
 
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemWrite
 opLat=1
@@ -409,16 +460,19 @@
 type=FUDesc
 children=opList0 opList1
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemRead
 opLat=1
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemWrite
 opLat=1
@@ -427,10 +481,12 @@
 type=FUDesc
 children=opList
 count=1
+eventq_index=0
 opList=system.cpu.fuPool.FUList8.opList
 
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
+eventq_index=0
 issueLat=3
 opClass=IprAccess
 opLat=3
@@ -441,6 +497,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -449,6 +506,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -463,17 +521,23 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -482,6 +546,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -490,6 +555,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -504,12 +570,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -519,6 +588,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -528,7 +598,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -542,11 +613,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -566,6 +639,7 @@
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -577,17 +651,21 @@
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
index 27f858d..62976a8 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr

@@ -1,4 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: Prefetch instructions in Alpha do not do anything
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
index 4cf5ca9..da1484d 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout

@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 16 2013 01:34:33
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:20
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 11933500 because target called exit()
+Exiting @ tick 11990500 because target called exit()

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index 5e19e4b..baea5f5 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    11990500                       # Number of ticks simulated
 final_tick                                   11990500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  47015                       # Simulator instruction rate (inst/s)
-host_op_rate                                    46988                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              235942636                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225832                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                  21306                       # Simulator instruction rate (inst/s)
+host_op_rate                                    21301                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              106974940                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229436                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 sim_ops                                          2387                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             12032                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              5440                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                17472                       # Number of bytes read from this memory
@@ -211,6 +213,7 @@
 system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            2551500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             21.3                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    1176                       # Number of BP lookups
 system.cpu.branchPred.condPredicted               619                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               258                       # Number of conditional branches incorrect
@@ -541,6 +544,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst    93.236237                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.045526                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.045526                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          188                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           27                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.091797                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              2318                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             2318                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst          815                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total             815                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst           815                       # number of demand (read+write) hits
@@ -627,6 +636,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002851                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000875                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.003727                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          249                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          211                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.007599                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             2457                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            2457                       # Number of data accesses
 system.cpu.l2cache.ReadReq_misses::cpu.inst          188                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           61                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total          249                       # number of ReadReq misses
@@ -744,6 +759,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data    45.667407                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.011149                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.011149                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              1989                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             1989                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data          545                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             545                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          213                       # number of WriteReq hits

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index b66459c..aca9f49 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,26 @@
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +108,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +123,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +142,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +152,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
index bcbfa54..32998f2 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr

@@ -1,4 +1,2 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
index 034bc58..33ba2e7 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:27
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:20
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
index aec79b9..04acc5c 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                     1297500                       # Number of ticks simulated
 final_tick                                    1297500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 388869                       # Simulator instruction rate (inst/s)
-host_op_rate                                   388153                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              195100518                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215488                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                  31206                       # Simulator instruction rate (inst/s)
+host_op_rate                                    31196                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               15701703                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219708                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             10340                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              3016                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                13356                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                  11879768786                       # Throughput (bytes/s)
 system.membus.data_through_bus                  15414                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
index f2dc4f3..8168c28 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini

@@ -88,6 +88,7 @@
 [system.cpu.isa]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -107,7 +108,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
index 492f3e6..a30a2a9 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr

@@ -4,4 +4,3 @@
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
index 5722711..f35dc86 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout

@@ -1,14 +1,12 @@
-Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:27:02
-gem5 started Sep 22 2013 05:27:13
-gem5 executing on zizzer
-command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
+gem5 compiled Jan 22 2014 16:37:52
+gem5 started Jan 22 2014 17:26:00
+gem5 executing on u200540-lin
+command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 52575 because target called exit()
+Exiting @ tick 52548 because target called exit()

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
index 1d9a455..96547c7 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt

@@ -4,13 +4,16 @@
 sim_ticks                                       52548                       # Number of ticks simulated
 final_tick                                      52548                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  16682                       # Simulator instruction rate (inst/s)
-host_op_rate                                    16680                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 340078                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 169540                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
+host_inst_rate                                  25744                       # Simulator instruction rate (inst/s)
+host_op_rate                                    25740                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 524809                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 124924                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
 system.ruby.delayHist::samples                   3612                       # delay histogram for all message
@@ -100,6 +103,7 @@
 system.ruby.network.routers1.msg_bytes.Writeback_Data::0         3240                      
 system.ruby.network.routers1.msg_bytes.Writeback_Data::1         4464                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::0          632                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.dir_cntrl0.memBuffer.memReq           650                       # Total number of memory requests
 system.ruby.dir_cntrl0.memBuffer.memRead          547                       # Number of memory reads
 system.ruby.dir_cntrl0.memBuffer.memWrite          103                       # Number of memory writes
@@ -148,6 +152,7 @@
 system.ruby.network.msg_byte.Response_Control        41760                      
 system.ruby.network.msg_byte.Writeback_Data        23112                      
 system.ruby.network.msg_byte.Writeback_Control         1896                      
+system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 1cc4792..647bb1e 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -68,24 +73,31 @@
 [system.cpu.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -95,7 +107,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,6 +124,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -119,18 +133,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=1
 random_seed=1234
 randomization=false
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -138,9 +156,10 @@
 children=directory memBuffer
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=2
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=6
+eventq_index=0
 memBuffer=system.ruby.dir_cntrl0.memBuffer
 number_of_TBEs=256
 peer=Null
@@ -151,6 +170,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -167,6 +187,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -186,7 +207,8 @@
 L1Icache=system.ruby.l1_cntrl0.L1Icache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
 l2_select_num_bits=0
 number_of_TBEs=256
 peer=Null
@@ -204,6 +226,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -218,6 +241,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -233,6 +257,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -250,7 +275,8 @@
 L2cache=system.ruby.l2_cntrl0.L2cache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
+eventq_index=0
 number_of_TBEs=256
 peer=Null
 recycle_latency=10
@@ -265,6 +291,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
@@ -278,6 +305,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -287,6 +315,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
 number_of_virtual_networks=10
@@ -297,6 +326,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -306,6 +336,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l2_cntrl0
 int_node=system.ruby.network.routers1
 latency=1
@@ -315,6 +346,7 @@
 [system.ruby.network.ext_links2]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers2
 latency=1
@@ -324,6 +356,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=3
 node_a=system.ruby.network.routers0
@@ -333,6 +366,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=4
 node_a=system.ruby.network.routers1
@@ -342,6 +376,7 @@
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=5
 node_a=system.ruby.network.routers2
@@ -351,38 +386,36 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
 [system.ruby.network.routers3]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=3
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -394,5 +427,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
index 492f3e6..a30a2a9 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr

@@ -4,4 +4,3 @@
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index e2683dd..c37233c 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:36:12
-gem5 started Sep 22 2013 05:36:23
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:42:56
+gem5 started Jan 22 2014 17:26:33
+gem5 executing on u200540-lin
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 5ece97b..b355345 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt

@@ -4,13 +4,16 @@
 sim_ticks                                       44968                       # Number of ticks simulated
 final_tick                                      44968                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  16150                       # Simulator instruction rate (inst/s)
-host_op_rate                                    16148                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 281738                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 171884                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
+host_inst_rate                                  17948                       # Simulator instruction rate (inst/s)
+host_op_rate                                    17946                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 313128                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 128348                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            1                      
 system.ruby.outstanding_req_hist::max_bucket            9                      
 system.ruby.outstanding_req_hist::samples         3295                      
@@ -82,6 +85,7 @@
 system.ruby.network.routers1.msg_bytes.Writeback_Control::1         6512                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::2         2648                      
 system.ruby.network.routers1.msg_bytes.Unblock_Control::2         7464                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.dir_cntrl0.memBuffer.memReq           499                       # Total number of memory requests
 system.ruby.dir_cntrl0.memBuffer.memRead          423                       # Number of memory reads
 system.ruby.dir_cntrl0.memBuffer.memWrite           76                       # Number of memory writes
@@ -139,6 +143,7 @@
 system.ruby.network.msg_byte.Writeback_Data       124848                      
 system.ruby.network.msg_byte.Writeback_Control        51576                      
 system.ruby.network.msg_byte.Unblock_Control        22384                      
+system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index 57448e3..2bf0001 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -68,24 +73,31 @@
 [system.cpu.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -95,7 +107,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,6 +124,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -119,18 +133,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=1
 random_seed=1234
 randomization=false
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -138,10 +156,11 @@
 children=directory memBuffer
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=2
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=5
 distributed_persistent=true
+eventq_index=0
 fixed_timeout_latency=100
 l2_select_num_bits=0
 memBuffer=system.ruby.dir_cntrl0.memBuffer
@@ -155,6 +174,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -171,6 +191,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -191,8 +212,9 @@
 N_tokens=2
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
 dynamic_timeout_enabled=true
+eventq_index=0
 fixed_timeout_latency=300
 l1_request_latency=2
 l1_response_latency=2
@@ -215,6 +237,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -229,6 +252,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -244,6 +268,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -262,7 +287,8 @@
 N_tokens=2
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
+eventq_index=0
 filtering_enabled=true
 l2_request_latency=5
 l2_response_latency=5
@@ -278,6 +304,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
@@ -291,6 +318,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -300,6 +328,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
 number_of_virtual_networks=10
@@ -310,6 +339,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -319,6 +349,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l2_cntrl0
 int_node=system.ruby.network.routers1
 latency=1
@@ -328,6 +359,7 @@
 [system.ruby.network.ext_links2]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers2
 latency=1
@@ -337,6 +369,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=3
 node_a=system.ruby.network.routers0
@@ -346,6 +379,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=4
 node_a=system.ruby.network.routers1
@@ -355,6 +389,7 @@
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=5
 node_a=system.ruby.network.routers2
@@ -364,38 +399,36 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
 [system.ruby.network.routers3]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=3
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -407,5 +440,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
index 492f3e6..a30a2a9 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr

@@ -4,4 +4,3 @@
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index 76c77f4..b3289a2 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:44:48
-gem5 started Sep 22 2013 05:45:00
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:47:59
+gem5 started Jan 22 2014 17:27:30
+gem5 executing on u200540-lin
 command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 17ea987..0c82e32 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt

@@ -4,13 +4,16 @@
 sim_ticks                                       43073                       # Number of ticks simulated
 final_tick                                      43073                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                   7100                       # Simulator instruction rate (inst/s)
-host_op_rate                                     7100                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 118667                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 169652                       # Number of bytes of host memory used
-host_seconds                                     0.36                       # Real time elapsed on the host
+host_inst_rate                                  26553                       # Simulator instruction rate (inst/s)
+host_op_rate                                    26550                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 443703                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 126100                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            1                      
 system.ruby.outstanding_req_hist::max_bucket            9                      
 system.ruby.outstanding_req_hist::samples         3295                      
@@ -76,6 +79,7 @@
 system.ruby.network.routers1.msg_bytes.Response_Control::4            8                      
 system.ruby.network.routers1.msg_bytes.Writeback_Data::4        42192                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::4         2920                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.dir_cntrl0.memBuffer.memReq           532                       # Total number of memory requests
 system.ruby.dir_cntrl0.memBuffer.memRead          448                       # Number of memory reads
 system.ruby.dir_cntrl0.memBuffer.memWrite           84                       # Number of memory writes
@@ -125,6 +129,7 @@
 system.ruby.network.msg_byte.Response_Control           24                      
 system.ruby.network.msg_byte.Writeback_Data       126576                      
 system.ruby.network.msg_byte.Writeback_Control         8760                      
+system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index fed15fe..1829ec0 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -68,24 +73,31 @@
 [system.cpu.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -95,7 +107,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,6 +124,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -119,18 +133,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=1
 random_seed=1234
 randomization=false
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -138,8 +156,9 @@
 children=directory memBuffer probeFilter
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
+eventq_index=0
 full_bit_dir_enabled=false
 memBuffer=system.ruby.dir_cntrl0.memBuffer
 memory_controller_latency=2
@@ -154,6 +173,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -170,6 +190,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -187,6 +208,7 @@
 assoc=4
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=1
 replacement_policy=PSEUDO_LRU
@@ -205,7 +227,8 @@
 buffer_size=0
 cache_response_latency=10
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
 issue_latency=2
 l2_cache_hit_latency=10
 no_mig_atomic=true
@@ -223,6 +246,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -237,6 +261,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -251,6 +276,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
@@ -266,6 +292,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -281,6 +308,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -290,6 +318,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
 number_of_virtual_networks=10
@@ -300,6 +329,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -309,6 +339,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers1
 latency=1
@@ -318,6 +349,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=2
 node_a=system.ruby.network.routers0
@@ -327,6 +359,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=3
 node_a=system.ruby.network.routers1
@@ -336,32 +369,29 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -373,5 +403,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
index 492f3e6..a30a2a9 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr

@@ -4,4 +4,3 @@
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
index fa7b05a..74d6c0f 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:17:28
-gem5 started Sep 22 2013 05:17:49
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:32:54
+gem5 started Jan 22 2014 17:25:27
+gem5 executing on u200540-lin
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index fc4b80a..fe7ac0e 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt

@@ -4,13 +4,16 @@
 sim_ticks                                       35432                       # Number of ticks simulated
 final_tick                                      35432                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  20063                       # Simulator instruction rate (inst/s)
-host_op_rate                                    20060                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 275767                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 169584                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
+host_inst_rate                                  28350                       # Simulator instruction rate (inst/s)
+host_op_rate                                    28346                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 389675                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 126044                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            1                      
 system.ruby.outstanding_req_hist::max_bucket            9                      
 system.ruby.outstanding_req_hist::samples         3295                      
@@ -43,6 +46,7 @@
 system.ruby.miss_latency_hist            |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         421     95.46%     95.46% |           2      0.45%     95.92% |          12      2.72%     98.64% |           0      0.00%     98.64% |           6      1.36%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total              441                      
 system.ruby.Directory.incomplete_times            440                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.l1_cntrl0.L1Dcache.demand_hits          469                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          240                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Dcache.demand_accesses          709                       # Number of cache demand accesses
@@ -123,6 +127,7 @@
 system.ruby.network.msg_byte.Writeback_Data        17496                      
 system.ruby.network.msg_byte.Writeback_Control        28656                      
 system.ruby.network.msg_byte.Unblock_Control        10560                      
+system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 56f1e35..360da34 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -68,24 +73,31 @@
 [system.cpu.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -95,7 +107,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,6 +124,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -119,18 +133,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=1
 random_seed=1234
 randomization=false
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -138,9 +156,10 @@
 children=directory memBuffer
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
+eventq_index=0
 memBuffer=system.ruby.dir_cntrl0.memBuffer
 number_of_TBEs=256
 peer=Null
@@ -151,6 +170,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -167,6 +187,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -186,7 +207,8 @@
 cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
 issue_latency=2
 number_of_TBEs=256
 peer=Null
@@ -202,6 +224,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -217,6 +240,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.cacheMemory
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -232,6 +256,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -241,6 +266,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
 number_of_virtual_networks=10
@@ -251,6 +277,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -260,6 +287,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers1
 latency=1
@@ -269,6 +297,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=2
 node_a=system.ruby.network.routers0
@@ -278,6 +307,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=3
 node_a=system.ruby.network.routers1
@@ -287,32 +317,29 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -324,5 +351,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
index 492f3e6..a30a2a9 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr

@@ -4,4 +4,3 @@
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
index 980ebae..11cc12f 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:38
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:30
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index a74ef31..845b448 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt

@@ -4,13 +4,16 @@
 sim_ticks                                       52498                       # Number of ticks simulated
 final_tick                                      52498                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  27660                       # Simulator instruction rate (inst/s)
-host_op_rate                                    27654                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 563232                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 168112                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                  24935                       # Simulator instruction rate (inst/s)
+host_op_rate                                    24932                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 507835                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 124536                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
 system.ruby.delayHist::samples                   1248                       # delay histogram for all message
@@ -47,6 +50,7 @@
 system.ruby.miss_latency_hist            |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         142     22.68%     22.68% |         448     71.57%     94.25% |          36      5.75%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total              626                      
 system.ruby.Directory.incomplete_times            625                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         2668                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses          626                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses         3294                       # Number of cache demand accesses
@@ -98,6 +102,7 @@
 system.ruby.network.msg_byte.Data              134352                      
 system.ruby.network.msg_byte.Response_Data       135216                      
 system.ruby.network.msg_byte.Writeback_Control        14928                      
+system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 81f2281..7ab4d5c 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=AlphaTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,23 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=AlphaISA
+eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
+eventq_index=0
 size=48
 
 [system.cpu.l2cache]
@@ -147,6 +165,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +174,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +189,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +207,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +217,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +232,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +251,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +261,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
index 31ae36f..32998f2 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr

@@ -1,3 +1,2 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
index f5b60c7..cd7b05e 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:38
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:26
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
index 0eefef0..3fc7cd3 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    16524000                       # Number of ticks simulated
 final_tick                                   16524000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                     70                       # Simulator instruction rate (inst/s)
-host_op_rate                                       70                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 446596                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222964                       # Number of bytes of host memory used
-host_seconds                                    37.00                       # Real time elapsed on the host
+host_inst_rate                                  33204                       # Simulator instruction rate (inst/s)
+host_op_rate                                    33192                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              212757424                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228444                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             10432                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              5248                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                15680                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@
 system.membus.reqLayer0.utilization               1.5                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            2205000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             13.3                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -106,6 +109,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst    80.050296                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.039087                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.039087                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          163                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           61                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.079590                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              5335                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             5335                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         2423                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            2423                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          2423                       # number of demand (read+write) hits
@@ -186,6 +195,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002447                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000824                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.003270                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          218                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           82                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.006653                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             2205                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            2205                       # Number of data accesses
 system.cpu.l2cache.ReadReq_misses::cpu.inst          163                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total          218                       # number of ReadReq misses
@@ -303,6 +318,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data    47.437790                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.011581                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.011581                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024           82                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.020020                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              1500                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             1500                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data          360                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             360                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          267                       # number of WriteReq hits

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
index 91966ea..5c3361f 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -64,6 +68,8 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
+fetchBufferSize=64
 fetchToDecodeDelay=1
 fetchTrapLatency=1
 fetchWidth=8
@@ -128,6 +134,7 @@
 RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
+eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
 instShiftAmt=2
@@ -147,6 +154,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.checker.dtb
+eventq_index=0
 exitOnError=false
 function_trace=false
 function_trace_start=0
@@ -171,18 +179,21 @@
 [system.cpu.checker.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.checker.dtb.walker
 
 [system.cpu.checker.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[5]
 
 [system.cpu.checker.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -201,18 +212,21 @@
 [system.cpu.checker.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.checker.itb.walker
 
 [system.cpu.checker.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[4]
 
 [system.cpu.checker.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.dcache]
 type=BaseCache
@@ -220,6 +234,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -228,6 +243,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -242,18 +258,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -262,15 +282,18 @@
 type=FUPool
 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+eventq_index=0
 
 [system.cpu.fuPool.FUList0]
 type=FUDesc
 children=opList
 count=6
+eventq_index=0
 opList=system.cpu.fuPool.FUList0.opList
 
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=IntAlu
 opLat=1
@@ -279,16 +302,19 @@
 type=FUDesc
 children=opList0 opList1
 count=2
+eventq_index=0
 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=IntMult
 opLat=3
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=19
 opClass=IntDiv
 opLat=20
@@ -297,22 +323,26 @@
 type=FUDesc
 children=opList0 opList1 opList2
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatAdd
 opLat=2
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatCmp
 opLat=2
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatCvt
 opLat=2
@@ -321,22 +351,26 @@
 type=FUDesc
 children=opList0 opList1 opList2
 count=2
+eventq_index=0
 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatMult
 opLat=4
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=12
 opClass=FloatDiv
 opLat=12
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
+eventq_index=0
 issueLat=24
 opClass=FloatSqrt
 opLat=24
@@ -345,10 +379,12 @@
 type=FUDesc
 children=opList
 count=0
+eventq_index=0
 opList=system.cpu.fuPool.FUList4.opList
 
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemRead
 opLat=1
@@ -357,124 +393,145 @@
 type=FUDesc
 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAdd
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAddAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAlu
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdCmp
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdCvt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMisc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMult
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMultAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdShift
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdShiftAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdSqrt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatAdd
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatAlu
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatCmp
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatCvt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatDiv
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMisc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMult
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
@@ -483,10 +540,12 @@
 type=FUDesc
 children=opList
 count=0
+eventq_index=0
 opList=system.cpu.fuPool.FUList6.opList
 
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemWrite
 opLat=1
@@ -495,16 +554,19 @@
 type=FUDesc
 children=opList0 opList1
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemRead
 opLat=1
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemWrite
 opLat=1
@@ -513,10 +575,12 @@
 type=FUDesc
 children=opList
 count=1
+eventq_index=0
 opList=system.cpu.fuPool.FUList8.opList
 
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
+eventq_index=0
 issueLat=3
 opClass=IprAccess
 opLat=3
@@ -527,6 +591,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -535,6 +600,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -549,14 +615,18 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -575,12 +645,14 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -591,6 +663,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -599,6 +672,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -613,12 +687,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -628,6 +705,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -637,7 +715,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -651,11 +730,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -675,6 +756,7 @@
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -686,17 +768,21 @@
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index 47104f0..dc275e0 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout

@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 01:55:20
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 17:30:22
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 16494000 because target called exit()
+Exiting @ tick 16981000 because target called exit()

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index 6f535bc..8e11038 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    16981000                       # Number of ticks simulated
 final_tick                                   16981000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  41552                       # Simulator instruction rate (inst/s)
-host_op_rate                                    51840                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              153628168                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 240508                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                  35724                       # Simulator instruction rate (inst/s)
+host_op_rate                                    44574                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              132106037                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 247896                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             17280                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              7808                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                25088                       # Number of bytes read from this memory
@@ -215,6 +217,7 @@
 system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            3646500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             21.5                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    2481                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1780                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               482                       # Number of conditional branches incorrect
@@ -597,6 +600,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   148.072869                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.072301                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.072301                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          286                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          118                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.139648                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4184                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4184                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         1584                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            1584                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          1584                       # number of demand (read+write) hits
@@ -683,6 +692,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004255                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001438                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.005693                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          157                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010681                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             3887                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            3887                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst           20                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           20                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total             40                       # number of ReadReq hits
@@ -815,6 +830,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data    87.464066                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.021354                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.021354                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              5930                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5930                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         1767                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1767                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          606                       # number of WriteReq hits

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index 507cb57..9b066fd 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -64,6 +68,8 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
+fetchBufferSize=64
 fetchToDecodeDelay=1
 fetchTrapLatency=1
 fetchWidth=8
@@ -128,6 +134,7 @@
 RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
+eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
 instShiftAmt=2
@@ -143,6 +150,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -151,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -165,18 +174,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -185,15 +198,18 @@
 type=FUPool
 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+eventq_index=0
 
 [system.cpu.fuPool.FUList0]
 type=FUDesc
 children=opList
 count=6
+eventq_index=0
 opList=system.cpu.fuPool.FUList0.opList
 
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=IntAlu
 opLat=1
@@ -202,16 +218,19 @@
 type=FUDesc
 children=opList0 opList1
 count=2
+eventq_index=0
 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=IntMult
 opLat=3
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=19
 opClass=IntDiv
 opLat=20
@@ -220,22 +239,26 @@
 type=FUDesc
 children=opList0 opList1 opList2
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatAdd
 opLat=2
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatCmp
 opLat=2
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatCvt
 opLat=2
@@ -244,22 +267,26 @@
 type=FUDesc
 children=opList0 opList1 opList2
 count=2
+eventq_index=0
 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatMult
 opLat=4
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=12
 opClass=FloatDiv
 opLat=12
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
+eventq_index=0
 issueLat=24
 opClass=FloatSqrt
 opLat=24
@@ -268,10 +295,12 @@
 type=FUDesc
 children=opList
 count=0
+eventq_index=0
 opList=system.cpu.fuPool.FUList4.opList
 
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemRead
 opLat=1
@@ -280,124 +309,145 @@
 type=FUDesc
 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAdd
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAddAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAlu
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdCmp
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdCvt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMisc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMult
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMultAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdShift
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdShiftAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdSqrt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatAdd
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatAlu
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatCmp
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatCvt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatDiv
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMisc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMult
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
@@ -406,10 +456,12 @@
 type=FUDesc
 children=opList
 count=0
+eventq_index=0
 opList=system.cpu.fuPool.FUList6.opList
 
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemWrite
 opLat=1
@@ -418,16 +470,19 @@
 type=FUDesc
 children=opList0 opList1
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemRead
 opLat=1
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemWrite
 opLat=1
@@ -436,10 +491,12 @@
 type=FUDesc
 children=opList
 count=1
+eventq_index=0
 opList=system.cpu.fuPool.FUList8.opList
 
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
+eventq_index=0
 issueLat=3
 opClass=IprAccess
 opLat=3
@@ -450,6 +507,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -458,6 +516,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -472,14 +531,18 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -498,12 +561,14 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -514,6 +579,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -522,6 +588,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -536,12 +603,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -551,6 +621,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -560,7 +631,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -574,11 +646,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -598,6 +672,7 @@
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -609,17 +684,21 @@
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
index d3be13c..5df8619 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout

@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 01:55:13
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 17:30:21
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 16494000 because target called exit()
+Exiting @ tick 16981000 because target called exit()

diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index 1007dae..3ffee06 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    16981000                       # Number of ticks simulated
 final_tick                                   16981000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  59313                       # Simulator instruction rate (inst/s)
-host_op_rate                                    73997                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              219275591                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 240508                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  34743                       # Simulator instruction rate (inst/s)
+host_op_rate                                    43351                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              128481440                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 246872                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             17280                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              7808                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                25088                       # Number of bytes read from this memory
@@ -215,6 +217,7 @@
 system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            3646500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             21.5                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    2481                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1780                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               482                       # Number of conditional branches incorrect
@@ -552,6 +555,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   148.072869                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.072301                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.072301                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          286                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          118                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.139648                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4184                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4184                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         1584                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            1584                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          1584                       # number of demand (read+write) hits
@@ -638,6 +647,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004255                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001438                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.005693                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          157                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010681                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             3887                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            3887                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst           20                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           20                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total             40                       # number of ReadReq hits
@@ -770,6 +785,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data    87.464066                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.021354                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.021354                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              5930                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5930                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         1767                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1767                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          606                       # number of WriteReq hits

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
index 05132e4..1158c75 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -82,6 +87,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.checker.dtb
+eventq_index=0
 exitOnError=false
 function_trace=false
 function_trace_start=0
@@ -106,17 +112,20 @@
 [system.cpu.checker.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.checker.dtb.walker
 
 [system.cpu.checker.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 
 [system.cpu.checker.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -135,36 +144,43 @@
 [system.cpu.checker.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.checker.itb.walker
 
 [system.cpu.checker.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 
 [system.cpu.checker.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -183,18 +199,21 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -204,7 +223,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -218,11 +238,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -235,6 +257,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -244,5 +267,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
index 3a9ca0e..7509c2d 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:10:56
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 17:30:32
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
index 05df8ba..4b1e74a 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                     2870500                       # Number of ticks simulated
 final_tick                                    2870500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 686137                       # Simulator instruction rate (inst/s)
-host_op_rate                                   854515                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              427336749                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232512                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                  61907                       # Simulator instruction rate (inst/s)
+host_op_rate                                    77238                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               38693079                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237008                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             18416                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              4491                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                22907                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                   9251001568                       # Throughput (bytes/s)
 system.membus.data_through_bus                  26555                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
 system.cpu.checker.dtb.read_hits                    0                       # DTB read hits

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
index ea8fd73..8e0b67b 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -75,21 +80,25 @@
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -108,18 +117,21 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -129,7 +141,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -143,11 +156,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -160,6 +175,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -169,5 +185,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
index 7cee6c9..618f6d6 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 08:14:08
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 17:30:32
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
index ea8a367..ea0a0e0 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                     2870500                       # Number of ticks simulated
 final_tick                                    2870500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 723203                       # Simulator instruction rate (inst/s)
-host_op_rate                                   900650                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              450384934                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232532                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                  81917                       # Simulator instruction rate (inst/s)
+host_op_rate                                   102184                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               51187301                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236980                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             18416                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              4491                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                22907                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                   9251001568                       # Throughput (bytes/s)
 system.membus.data_through_bus                  26555                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
index aa887d8..bae9efe 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,18 +100,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -115,6 +126,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -123,6 +135,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -137,14 +150,18 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=ArmInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=ArmISA
+eventq_index=0
 fpsid=1090793632
 id_isar0=34607377
 id_isar1=34677009
@@ -163,12 +180,14 @@
 [system.cpu.itb]
 type=ArmTLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
@@ -179,6 +198,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -187,6 +207,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -201,12 +222,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -216,6 +240,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -225,7 +250,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -239,11 +265,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -256,6 +284,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -265,5 +294,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
index db0e6ca..6834abe 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 07:58:15
-gem5 started Sep 22 2013 09:24:32
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 22 2014 17:30:42
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
index 13e2763..a3962cb 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    25969000                       # Number of ticks simulated
 final_tick                                   25969000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 229244                       # Simulator instruction rate (inst/s)
-host_op_rate                                   284503                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1301168988                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 238660                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                  84539                       # Simulator instruction rate (inst/s)
+host_op_rate                                   105013                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              480681007                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 245716                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        4565                       # Number of instructions simulated
 sim_ops                                          5672                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             14400                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8000                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                22400                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@
 system.membus.reqLayer0.utilization               1.3                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            3150000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             12.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
 system.cpu.dtb.read_hits                            0                       # DTB read hits
@@ -116,6 +119,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   114.614391                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.055964                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.055964                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          240                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          107                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          133                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.117188                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              9451                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             9451                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         4364                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            4364                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          4364                       # number of demand (read+write) hits
@@ -196,6 +205,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003231                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001470                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.004702                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          307                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          179                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.009369                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             3406                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            3406                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst           16                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           16                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total             32                       # number of ReadReq hits
@@ -322,6 +337,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data    83.000387                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.020264                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.020264                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          141                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          101                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.034424                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              4303                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4303                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         1048                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1048                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          870                       # number of WriteReq hits

diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
index 2a0a591..734275a 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -56,6 +60,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fetchBuffSize=4
 function_trace=false
 function_trace_start=0
@@ -90,6 +95,7 @@
 RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
+eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
 instShiftAmt=2
@@ -105,6 +111,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -113,6 +120,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -127,11 +135,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=MipsTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -140,6 +151,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -148,6 +160,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -162,19 +175,25 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=MipsInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=MipsISA
+eventq_index=0
 num_threads=1
 num_vpes=1
+system=system
 
 [system.cpu.itb]
 type=MipsTLB
+eventq_index=0
 size=64
 
 [system.cpu.l2cache]
@@ -183,6 +202,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -191,6 +211,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -205,12 +226,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -220,6 +244,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -229,7 +254,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -243,11 +269,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -267,6 +295,7 @@
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -278,17 +307,21 @@
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
index 0184d25..5a8e673 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout

@@ -1,14 +1,12 @@
-Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:51:54
-gem5 started Sep 22 2013 05:52:06
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:53:01
+gem5 started Jan 22 2014 17:27:52
+gem5 executing on u200540-lin
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 24587000 because target called exit()
+Exiting @ tick 24975000 because target called exit()

diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
index 3c2a965..3e4b6f4 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    24975000                       # Number of ticks simulated
 final_tick                                   24975000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  84511                       # Simulator instruction rate (inst/s)
-host_op_rate                                    84494                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              362882134                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 254488                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  42229                       # Simulator instruction rate (inst/s)
+host_op_rate                                    42225                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              181364329                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 230516                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
 sim_insts                                        5814                       # Number of instructions simulated
 sim_ops                                          5814                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             20288                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                29120                       # Number of bytes read from this memory
@@ -212,6 +214,7 @@
 system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            4260750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             17.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    1156                       # Number of BP lookups
 system.cpu.branchPred.condPredicted               861                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               603                       # Number of conditional branches incorrect
@@ -309,6 +312,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   150.636983                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.073553                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.073553                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          306                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.149414                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              1875                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             1875                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst          428                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total             428                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst           428                       # number of demand (read+write) hits
@@ -414,6 +423,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004648                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001712                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.006360                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          404                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          249                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012329                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4111                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4111                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -537,6 +552,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data    90.339752                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.022056                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.022056                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.033691                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              4314                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4314                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         1066                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1066                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          572                       # number of WriteReq hits

diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
index 90b3951..df84ba0 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini

@@ -159,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -504,6 +506,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -520,6 +523,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -531,6 +535,7 @@
 eventq_index=0
 num_threads=1
 num_vpes=1
+system=system
 
 [system.cpu.itb]
 type=MipsTLB
@@ -552,6 +557,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -568,6 +574,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -594,7 +601,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
index a390bcc..3925c48 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout

@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:28:28
-gem5 started Oct 16 2013 01:35:02
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:53:01
+gem5 started Jan 22 2014 17:28:02
+gem5 executing on u200540-lin
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 21805500 because target called exit()
+Exiting @ tick 21898500 because target called exit()

diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index 3589948..b4a7329 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    21898500                       # Number of ticks simulated
 final_tick                                   21898500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  34889                       # Simulator instruction rate (inst/s)
-host_op_rate                                    34885                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              148144968                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 274956                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
+host_inst_rate                                  38049                       # Simulator instruction rate (inst/s)
+host_op_rate                                    38045                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              161516903                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231544                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
 sim_insts                                        5156                       # Number of instructions simulated
 sim_ops                                          5156                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             21440                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              9088                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                30528                       # Number of bytes read from this memory
@@ -212,6 +214,7 @@
 system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            4474750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             20.4                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    2174                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1490                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               438                       # Number of conditional branches incorrect
@@ -526,6 +529,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   161.632436                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.078922                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.078922                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          321                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          149                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          172                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.156738                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4268                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4268                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         1514                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            1514                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          1514                       # number of demand (read+write) hits
@@ -612,6 +621,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005003                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001766                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.006769                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          426                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          188                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.013000                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4317                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4317                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
@@ -735,6 +750,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data    91.712882                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.022391                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.022391                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          142                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.034668                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              5952                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5952                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         1832                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1832                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          563                       # number of WriteReq hits

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
index 917891d..cb74c0e 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,22 +79,28 @@
 
 [system.cpu.dtb]
 type=MipsTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=MipsInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=MipsISA
+eventq_index=0
 num_threads=1
 num_vpes=1
+system=system
 
 [system.cpu.itb]
 type=MipsTLB
+eventq_index=0
 size=64
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -99,7 +110,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -113,11 +125,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -130,6 +144,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -139,5 +154,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr
index 7edd901..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr

@@ -1,3 +1 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
index b1c55ad..4635935 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:51:54
-gem5 started Sep 22 2013 05:52:07
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:53:01
+gem5 started Jan 22 2014 17:28:13
+gem5 executing on u200540-lin
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
index e850cb6..fb6eb71 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                     2907000                       # Number of ticks simulated
 final_tick                                    2907000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 727521                       # Simulator instruction rate (inst/s)
-host_op_rate                                   725084                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              361375060                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216568                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                  88855                       # Simulator instruction rate (inst/s)
+host_op_rate                                    88837                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               44409305                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220784                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5814                       # Number of instructions simulated
 sim_ops                                          5814                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             23260                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              4374                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                27634                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                  10764361885                       # Throughput (bytes/s)
 system.membus.data_through_bus                  31292                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index 793123a..d40656f 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -68,26 +73,33 @@
 [system.cpu.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu.dtb]
 type=MipsTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=MipsInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=MipsISA
+eventq_index=0
 num_threads=1
 num_vpes=1
+system=system
 
 [system.cpu.itb]
 type=MipsTLB
+eventq_index=0
 size=64
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +109,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -113,6 +126,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -121,18 +135,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=1
 random_seed=1234
 randomization=false
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -140,9 +158,10 @@
 children=directory memBuffer
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
+eventq_index=0
 memBuffer=system.ruby.dir_cntrl0.memBuffer
 number_of_TBEs=256
 peer=Null
@@ -153,6 +172,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -169,6 +189,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -188,7 +209,8 @@
 cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
 issue_latency=2
 number_of_TBEs=256
 peer=Null
@@ -204,6 +226,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -219,6 +242,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.cacheMemory
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -234,6 +258,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -243,6 +268,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
 number_of_virtual_networks=10
@@ -253,6 +279,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -262,6 +289,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers1
 latency=1
@@ -271,6 +299,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=2
 node_a=system.ruby.network.routers0
@@ -280,6 +309,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=3
 node_a=system.ruby.network.routers1
@@ -289,32 +319,29 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -326,5 +353,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
index bbc0c79..86244d4 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr

@@ -3,4 +3,3 @@
 warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
index 5beaf82..3e5d01a 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:51:54
-gem5 started Sep 22 2013 05:52:07
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:53:01
+gem5 started Jan 22 2014 17:28:34
+gem5 executing on u200540-lin
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index eabbcdd..f6e1459 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt

@@ -4,13 +4,16 @@
 sim_ticks                                      125334                       # Number of ticks simulated
 final_tick                                     125334                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  30165                       # Simulator instruction rate (inst/s)
-host_op_rate                                    30162                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 650140                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 172408                       # Number of bytes of host memory used
-host_seconds                                     0.19                       # Real time elapsed on the host
+host_inst_rate                                  38153                       # Simulator instruction rate (inst/s)
+host_op_rate                                    38149                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 822314                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 127760                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
 sim_insts                                        5814                       # Number of instructions simulated
 sim_ops                                          5814                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
 system.ruby.delayHist::samples                   2982                       # delay histogram for all message
@@ -47,6 +50,7 @@
 system.ruby.miss_latency_hist            |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         328     21.97%     21.97% |        1088     72.87%     94.84% |          74      4.96%     99.80% |           3      0.20%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total             1493                      
 system.ruby.Directory.incomplete_times           1492                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         6410                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses         1493                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses         7903                       # Number of cache demand accesses
@@ -99,6 +103,7 @@
 system.ruby.network.msg_byte.Data              321624                      
 system.ruby.network.msg_byte.Response_Data       322488                      
 system.ruby.network.msg_byte.Writeback_Control        35736                      
+system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
index aa6f1a1..943508e 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=MipsTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,19 +140,25 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=MipsInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=MipsISA
+eventq_index=0
 num_threads=1
 num_vpes=1
+system=system
 
 [system.cpu.itb]
 type=MipsTLB
+eventq_index=0
 size=64
 
 [system.cpu.l2cache]
@@ -149,6 +167,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -157,6 +176,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -171,12 +191,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -186,6 +209,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -195,7 +219,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -209,11 +234,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -226,6 +253,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -235,5 +263,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
index f65ffe2..fe019aa 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simout
-Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:51:54
-gem5 started Sep 22 2013 05:52:20
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:53:01
+gem5 started Jan 22 2014 17:28:24
+gem5 executing on u200540-lin
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
index d3256ea..bed7402 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    31633000                       # Number of ticks simulated
 final_tick                                   31633000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 304637                       # Simulator instruction rate (inst/s)
-host_op_rate                                   304230                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1653175117                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224940                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                  65946                       # Simulator instruction rate (inst/s)
+host_op_rate                                    65935                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              358688094                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 230484                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        5814                       # Number of instructions simulated
 sim_ops                                          5814                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                28096                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@
 system.membus.reqLayer0.utilization               1.4                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            3951000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             12.5                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -92,6 +95,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   132.545353                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.064719                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.064719                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          290                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          114                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.141602                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses             11935                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            11935                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         5513                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            5513                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          5513                       # number of demand (read+write) hits
@@ -172,6 +181,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004086                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001655                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.005741                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          388                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011841                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             3967                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            3967                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -295,6 +310,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data    87.492114                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.021360                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.021360                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          114                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.033691                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              4314                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4314                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         1076                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1076                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          874                       # number of WriteReq hits

diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
index 3e13ce8..3132353 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -65,6 +69,8 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
+fetchBufferSize=64
 fetchToDecodeDelay=1
 fetchTrapLatency=1
 fetchWidth=8
@@ -129,6 +135,7 @@
 RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
+eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
 instShiftAmt=2
@@ -144,6 +151,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -152,6 +160,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -166,26 +175,32 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=PowerTLB
+eventq_index=0
 size=64
 
 [system.cpu.fuPool]
 type=FUPool
 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+eventq_index=0
 
 [system.cpu.fuPool.FUList0]
 type=FUDesc
 children=opList
 count=6
+eventq_index=0
 opList=system.cpu.fuPool.FUList0.opList
 
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=IntAlu
 opLat=1
@@ -194,16 +209,19 @@
 type=FUDesc
 children=opList0 opList1
 count=2
+eventq_index=0
 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=IntMult
 opLat=3
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=19
 opClass=IntDiv
 opLat=20
@@ -212,22 +230,26 @@
 type=FUDesc
 children=opList0 opList1 opList2
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatAdd
 opLat=2
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatCmp
 opLat=2
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatCvt
 opLat=2
@@ -236,22 +258,26 @@
 type=FUDesc
 children=opList0 opList1 opList2
 count=2
+eventq_index=0
 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatMult
 opLat=4
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=12
 opClass=FloatDiv
 opLat=12
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
+eventq_index=0
 issueLat=24
 opClass=FloatSqrt
 opLat=24
@@ -260,10 +286,12 @@
 type=FUDesc
 children=opList
 count=0
+eventq_index=0
 opList=system.cpu.fuPool.FUList4.opList
 
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemRead
 opLat=1
@@ -272,124 +300,145 @@
 type=FUDesc
 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAdd
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAddAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAlu
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdCmp
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdCvt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMisc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMult
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMultAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdShift
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdShiftAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdSqrt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatAdd
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatAlu
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatCmp
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatCvt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatDiv
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMisc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMult
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
@@ -398,10 +447,12 @@
 type=FUDesc
 children=opList
 count=0
+eventq_index=0
 opList=system.cpu.fuPool.FUList6.opList
 
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemWrite
 opLat=1
@@ -410,16 +461,19 @@
 type=FUDesc
 children=opList0 opList1
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemRead
 opLat=1
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemWrite
 opLat=1
@@ -428,10 +482,12 @@
 type=FUDesc
 children=opList
 count=1
+eventq_index=0
 opList=system.cpu.fuPool.FUList8.opList
 
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
+eventq_index=0
 issueLat=3
 opClass=IprAccess
 opLat=3
@@ -442,6 +498,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -450,6 +507,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -464,17 +522,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=PowerInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=PowerISA
+eventq_index=0
 
 [system.cpu.itb]
 type=PowerTLB
+eventq_index=0
 size=64
 
 [system.cpu.l2cache]
@@ -483,6 +546,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -491,6 +555,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -505,12 +570,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -520,6 +588,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -529,7 +598,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/power/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -543,11 +613,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -567,6 +639,7 @@
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -578,17 +651,21 @@
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
index 92c4525..bf0b025 100755
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout

@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:29:56
-gem5 started Oct 16 2013 01:35:14
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:58:44
+gem5 started Jan 22 2014 17:29:11
+gem5 executing on u200540-lin
 command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 18469500 because target called exit()
+Exiting @ tick 18905500 because target called exit()

diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index 800440e..66a9238 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    18905500                       # Number of ticks simulated
 final_tick                                   18905500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  83485                       # Simulator instruction rate (inst/s)
-host_op_rate                                    83467                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              272386071                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 250488                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                  44009                       # Simulator instruction rate (inst/s)
+host_op_rate                                    44004                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              143620144                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 227496                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        5792                       # Number of instructions simulated
 sim_ops                                          5792                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             22080                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              6464                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                28544                       # Number of bytes read from this memory
@@ -215,6 +217,7 @@
 system.membus.reqLayer0.utilization               3.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            4177750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             22.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    2238                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1804                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               419                       # Number of conditional branches incorrect
@@ -526,6 +529,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   169.362417                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.082696                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.082696                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          351                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          196                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          155                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.171387                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              3979                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             3979                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         1372                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            1372                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          1372                       # number of demand (read+write) hits
@@ -612,6 +621,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005134                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000962                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.006096                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          399                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          216                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          183                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012177                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4070                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4070                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            6                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              7                       # number of ReadReq hits
@@ -738,6 +753,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data    63.784946                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.015572                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.015572                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          102                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.024902                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              5348                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5348                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         1473                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1473                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          715                       # number of WriteReq hits

diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
index 0bfe98e..ab39b14 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -46,6 +50,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -75,20 +80,25 @@
 
 [system.cpu.dtb]
 type=PowerTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=PowerInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=PowerISA
+eventq_index=0
 
 [system.cpu.itb]
 type=PowerTLB
+eventq_index=0
 size=64
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -98,7 +108,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/power/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -112,11 +123,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -129,6 +142,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -138,5 +152,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr
index 7edd901..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr

@@ -1,3 +1 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
index df127b5..b419f1e 100755
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic/simout
-Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:59:47
-gem5 started Sep 22 2013 05:59:59
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:58:44
+gem5 started Jan 22 2014 17:29:13
+gem5 executing on u200540-lin
 command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
index 759fbed..a91187f 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                     2896000                       # Number of ticks simulated
 final_tick                                    2896000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 671850                       # Simulator instruction rate (inst/s)
-host_op_rate                                   669870                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              333940022                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 212612                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                  80864                       # Simulator instruction rate (inst/s)
+host_op_rate                                    80849                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               40410591                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 216708                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5793                       # Number of instructions simulated
 sim_ops                                          5793                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             23172                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              3720                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                26892                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                  10739295580                       # Throughput (bytes/s)
 system.membus.data_through_bus                  31101                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
index 803d2e6..74f6fdc 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -56,6 +60,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fetchBuffSize=4
 function_trace=false
 function_trace_start=0
@@ -90,6 +95,7 @@
 RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
+eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
 instShiftAmt=2
@@ -105,6 +111,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -113,6 +120,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -127,11 +135,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -140,6 +151,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -148,6 +160,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -162,17 +175,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.l2cache]
@@ -181,6 +199,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -189,6 +208,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -203,12 +223,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -218,6 +241,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -227,7 +251,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -241,11 +266,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -265,6 +292,7 @@
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -276,17 +304,21 @@
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
index 5555171..bce99f5 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout

@@ -1,12 +1,10 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:10:26
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 17:29:22
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Hello World!Exiting @ tick 20802500 because target called exit()
+Hello World!Exiting @ tick 20892500 because target called exit()

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
index b34a38a..005c219 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    20892500                       # Number of ticks simulated
 final_tick                                   20892500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  70791                       # Simulator instruction rate (inst/s)
-host_op_rate                                    70777                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              277537926                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 260788                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  24019                       # Simulator instruction rate (inst/s)
+host_op_rate                                    24017                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               94189663                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236900                       # Number of bytes of host memory used
+host_seconds                                     0.22                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             18496                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8576                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                27072                       # Number of bytes read from this memory
@@ -213,6 +215,7 @@
 system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            3930250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             18.8                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    1636                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1090                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               897                       # Number of conditional branches incorrect
@@ -292,6 +295,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   142.907558                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.069779                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.069779                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          291                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          143                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          148                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.142090                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              2807                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             2807                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst          892                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total             892                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst           892                       # number of demand (read+write) hits
@@ -397,6 +406,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004343                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000826                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.005170                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          342                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          171                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010437                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             3831                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            3831                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
@@ -523,6 +538,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data    85.407936                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.020852                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.020852                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          135                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           97                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.032959                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              2911                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             2911                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data          654                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             654                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          260                       # number of WriteReq hits

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
index 5f0f231..ea4a954 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,25 @@
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +107,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +122,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +141,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +151,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr
index 7edd901..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr

@@ -1,3 +1 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
index 3faafe3..c85cb4f 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:09:49
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 17:29:22
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index b27d1e6..a26cb72 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                     2694500                       # Number of ticks simulated
 final_tick                                    2694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 565055                       # Simulator instruction rate (inst/s)
-host_op_rate                                   563581                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              284338324                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222908                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                  53422                       # Simulator instruction rate (inst/s)
+host_op_rate                                    53415                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               27014162                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 227132                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             21480                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              4602                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                26082                       # Number of bytes read from this memory
@@ -36,6 +38,7 @@
 system.membus.throughput                  11559473001                       # Throughput (bytes/s)
 system.membus.data_through_bus                  31147                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                             5390                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index 0e46b88..cb65490 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -68,24 +73,30 @@
 [system.cpu.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -95,7 +106,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,6 +123,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -119,18 +132,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=1
 random_seed=1234
 randomization=false
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -138,9 +155,10 @@
 children=directory memBuffer
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
+eventq_index=0
 memBuffer=system.ruby.dir_cntrl0.memBuffer
 number_of_TBEs=256
 peer=Null
@@ -151,6 +169,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -167,6 +186,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -186,7 +206,8 @@
 cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
 issue_latency=2
 number_of_TBEs=256
 peer=Null
@@ -202,6 +223,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -217,6 +239,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.cacheMemory
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -232,6 +255,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -241,6 +265,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
 number_of_virtual_networks=10
@@ -251,6 +276,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -260,6 +286,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers1
 latency=1
@@ -269,6 +296,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=2
 node_a=system.ruby.network.routers0
@@ -278,6 +306,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=3
 node_a=system.ruby.network.routers1
@@ -287,32 +316,29 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -324,5 +350,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
index bbc0c79..86244d4 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr

@@ -3,4 +3,3 @@
 warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
index fe6ceeb..a7fbcbb 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:10:00
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 17:29:33
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index d8d5f48..ff67fbe 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt

@@ -4,13 +4,16 @@
 sim_ticks                                      107952                       # Number of ticks simulated
 final_tick                                     107952                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                    352                       # Simulator instruction rate (inst/s)
-host_op_rate                                      352                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                   7141                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 177732                       # Number of bytes of host memory used
-host_seconds                                    15.12                       # Real time elapsed on the host
+host_inst_rate                                  32230                       # Simulator instruction rate (inst/s)
+host_op_rate                                    32227                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 653032                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 134144                       # Number of bytes of host memory used
+host_seconds                                     0.17                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
 system.ruby.delayHist::samples                   2574                       # delay histogram for all message
@@ -47,6 +50,7 @@
 system.ruby.miss_latency_hist            |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         306     23.74%     23.74% |         913     70.83%     94.57% |          68      5.28%     99.84% |           1      0.08%     99.92% |           1      0.08%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total             1289                      
 system.ruby.Directory.incomplete_times           1288                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         5469                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses         1289                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses         6758                       # Number of cache demand accesses
@@ -99,6 +103,7 @@
 system.ruby.network.msg_byte.Data              277560                      
 system.ruby.network.msg_byte.Response_Data       278424                      
 system.ruby.network.msg_byte.Writeback_Control        30840                      
+system.cpu.clk_domain.clock                         1                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                           107952                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index 794c187..32f16be 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.l2cache]
@@ -147,6 +164,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +173,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +188,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +206,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +216,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +231,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +250,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +260,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
index c2df024..73a8d61 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:07:31
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 17:29:24
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index b76f909..b7dc82e 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    27800000                       # Number of ticks simulated
 final_tick                                   27800000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 441877                       # Simulator instruction rate (inst/s)
-host_op_rate                                   441389                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2300957264                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230904                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                  44522                       # Simulator instruction rate (inst/s)
+host_op_rate                                    44517                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              232295322                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236896                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             16320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8576                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                24896                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@
 system.membus.reqLayer0.utilization               1.4                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            3501000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             12.6                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            55600                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -74,6 +77,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   117.043638                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.057150                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.057150                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          257                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          148                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.125488                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses             10999                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            10999                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         5114                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            5114                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          5114                       # number of demand (read+write) hits
@@ -154,6 +163,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003556                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000783                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.004339                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          308                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.009399                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             3525                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            3525                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
@@ -280,6 +295,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data    82.118455                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.020048                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.020048                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          135                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.032959                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              2911                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             2911                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data          661                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             661                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          592                       # number of WriteReq hits

diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index 12dff19..b8e6ab8 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -64,6 +68,8 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
+fetchBufferSize=64
 fetchToDecodeDelay=1
 fetchTrapLatency=1
 fetchWidth=8
@@ -125,6 +131,7 @@
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.branchPred]
 type=BranchPredictor
@@ -133,6 +140,7 @@
 RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
+eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
 instShiftAmt=2
@@ -148,6 +156,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -156,6 +165,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -170,18 +180,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
@@ -190,15 +204,18 @@
 type=FUPool
 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+eventq_index=0
 
 [system.cpu.fuPool.FUList0]
 type=FUDesc
 children=opList
 count=6
+eventq_index=0
 opList=system.cpu.fuPool.FUList0.opList
 
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=IntAlu
 opLat=1
@@ -207,16 +224,19 @@
 type=FUDesc
 children=opList0 opList1
 count=2
+eventq_index=0
 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=IntMult
 opLat=3
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=19
 opClass=IntDiv
 opLat=20
@@ -225,22 +245,26 @@
 type=FUDesc
 children=opList0 opList1 opList2
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatAdd
 opLat=2
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatCmp
 opLat=2
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatCvt
 opLat=2
@@ -249,22 +273,26 @@
 type=FUDesc
 children=opList0 opList1 opList2
 count=2
+eventq_index=0
 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatMult
 opLat=4
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=12
 opClass=FloatDiv
 opLat=12
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
+eventq_index=0
 issueLat=24
 opClass=FloatSqrt
 opLat=24
@@ -273,10 +301,12 @@
 type=FUDesc
 children=opList
 count=0
+eventq_index=0
 opList=system.cpu.fuPool.FUList4.opList
 
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemRead
 opLat=1
@@ -285,124 +315,145 @@
 type=FUDesc
 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAdd
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAddAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAlu
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdCmp
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdCvt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMisc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMult
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMultAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdShift
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdShiftAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdSqrt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatAdd
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatAlu
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatCmp
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatCvt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatDiv
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMisc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMult
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
@@ -411,10 +462,12 @@
 type=FUDesc
 children=opList
 count=0
+eventq_index=0
 opList=system.cpu.fuPool.FUList6.opList
 
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemWrite
 opLat=1
@@ -423,16 +476,19 @@
 type=FUDesc
 children=opList0 opList1
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemRead
 opLat=1
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemWrite
 opLat=1
@@ -441,10 +497,12 @@
 type=FUDesc
 children=opList
 count=1
+eventq_index=0
 opList=system.cpu.fuPool.FUList8.opList
 
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
+eventq_index=0
 issueLat=3
 opClass=IprAccess
 opLat=3
@@ -455,6 +513,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -463,6 +522,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -477,12 +537,15 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -493,16 +556,19 @@
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
@@ -513,6 +579,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -521,6 +588,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -535,12 +603,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -550,6 +621,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -559,7 +631,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -573,11 +646,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -597,6 +672,7 @@
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -608,17 +684,21 @@
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
index 6fd8081..7bb858e 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout

@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:54:57
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 17:29:56
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 19639500 because target called exit()
+Exiting @ tick 19970500 because target called exit()

diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index b42a03b..d0b8bca 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    19970500                       # Number of ticks simulated
 final_tick                                   19970500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  37809                       # Simulator instruction rate (inst/s)
-host_op_rate                                    68492                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              140319695                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 243588                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
+host_inst_rate                                   4162                       # Simulator instruction rate (inst/s)
+host_op_rate                                     7540                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               15448311                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 248568                       # Number of bytes of host memory used
+host_seconds                                     1.29                       # Real time elapsed on the host
 sim_insts                                        5380                       # Number of instructions simulated
 sim_ops                                          9747                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             17472                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              9024                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                26496                       # Number of bytes read from this memory
@@ -212,6 +214,7 @@
 system.membus.reqLayer0.utilization               2.5                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            3871500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             19.4                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    3084                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              3084                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               542                       # Number of conditional branches incorrect
@@ -221,6 +224,7 @@
 system.cpu.branchPred.BTBHitPct             31.800263                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     207                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 74                       # Number of incorrect RAS predictions.
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            39942                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -509,6 +513,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   130.946729                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.063939                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.063939                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          274                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          150                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.133789                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              4234                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             4234                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         1609                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            1609                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          1609                       # number of demand (read+write) hits
@@ -595,6 +605,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003998                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000999                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.004998                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          337                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          155                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010284                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             3750                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            3750                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
@@ -721,6 +737,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data    83.239431                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.020322                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.020322                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          142                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           91                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.034668                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              5234                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5234                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         1479                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1479                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          858                       # number of WriteReq hits

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
index 6906721..eb1883c 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -76,16 +81,19 @@
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[4]
@@ -93,6 +101,7 @@
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -103,22 +112,26 @@
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.membus.slave[3]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -128,7 +141,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -142,11 +156,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -159,6 +175,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -168,5 +185,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
index 551fc8a..6330d04 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:45:55
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 17:30:08
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 34f6dae..f285016 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                     5615000                       # Number of ticks simulated
 final_tick                                    5615000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  57992                       # Simulator instruction rate (inst/s)
-host_op_rate                                   105036                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               60491180                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236648                       # Number of bytes of host memory used
+host_inst_rate                                  57117                       # Simulator instruction rate (inst/s)
+host_op_rate                                   103440                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               59566456                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237684                       # Number of bytes of host memory used
 host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             54912                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              7066                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                61978                       # Number of bytes read from this memory
@@ -36,6 +38,8 @@
 system.membus.throughput                  12304541407                       # Throughput (bytes/s)
 system.membus.data_through_bus                  69090                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            11231                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index 3bbe64b..d7786b6 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -69,21 +74,25 @@
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu.clk_domain
+eventq_index=0
 
 [system.cpu.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu.clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.ruby.l1_cntrl0.sequencer.slave[3]
@@ -91,6 +100,7 @@
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1
 pio_addr=2305843009213693952
 pio_latency=100
@@ -101,22 +111,26 @@
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu.clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.ruby.l1_cntrl0.sequencer.slave[2]
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -126,7 +140,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -142,6 +157,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -150,18 +166,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=1
 random_seed=1234
 randomization=false
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -169,9 +189,10 @@
 children=directory memBuffer
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
+eventq_index=0
 memBuffer=system.ruby.dir_cntrl0.memBuffer
 number_of_TBEs=256
 peer=Null
@@ -182,6 +203,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -198,6 +220,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -217,7 +240,8 @@
 cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
 issue_latency=2
 number_of_TBEs=256
 peer=Null
@@ -233,6 +257,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -248,6 +273,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.cacheMemory
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -264,6 +290,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -273,6 +300,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
 number_of_virtual_networks=10
@@ -283,6 +311,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -292,6 +321,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers1
 latency=1
@@ -301,6 +331,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=2
 node_a=system.ruby.network.routers0
@@ -310,6 +341,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=3
 node_a=system.ruby.network.routers1
@@ -319,32 +351,29 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -356,5 +385,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
index bbc0c79..86244d4 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr

@@ -3,4 +3,3 @@
 warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
index 78a38ee..53e9ad0 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:54:46
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 17:30:11
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 1b13654..9b8cf80 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt

@@ -4,13 +4,16 @@
 sim_ticks                                      121759                       # Number of ticks simulated
 final_tick                                     121759                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                   9034                       # Simulator instruction rate (inst/s)
-host_op_rate                                    16364                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 204397                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 189696                       # Number of bytes of host memory used
-host_seconds                                     0.60                       # Real time elapsed on the host
+host_inst_rate                                  33614                       # Simulator instruction rate (inst/s)
+host_op_rate                                    60888                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 760469                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 144688                       # Number of bytes of host memory used
+host_seconds                                     0.16                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                  1                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                   9                       # delay histogram for all message
 system.ruby.delayHist::samples                   2750                       # delay histogram for all message
@@ -47,6 +50,7 @@
 system.ruby.miss_latency_hist            |           0      0.00%      0.00% |           0      0.00%      0.00% |           0      0.00%      0.00% |         329     23.89%     23.89% |         977     70.95%     94.84% |          69      5.01%     99.85% |           1      0.07%     99.93% |           1      0.07%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total             1377                      
 system.ruby.Directory.incomplete_times           1376                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         7475                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses         1377                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses         8852                       # Number of cache demand accesses
@@ -99,6 +103,8 @@
 system.ruby.network.msg_byte.Data              296568                      
 system.ruby.network.msg_byte.Response_Data       297432                      
 system.ruby.network.msg_byte.Writeback_Control        32952                      
+system.cpu.clk_domain.clock                         1                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                   16                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                           121759                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index 2a7188a..b6193f8 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -69,6 +74,7 @@
 type=DerivedClockDomain
 clk_divider=16
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 
 [system.cpu.dcache]
 type=BaseCache
@@ -76,6 +82,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -84,6 +91,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -98,18 +106,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
@@ -120,6 +132,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -128,6 +141,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -142,12 +156,15 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=X86LocalApic
 clk_domain=system.cpu.apic_clk_domain
+eventq_index=0
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -158,16 +175,19 @@
 
 [system.cpu.isa]
 type=X86ISA
+eventq_index=0
 
 [system.cpu.itb]
 type=X86TLB
 children=walker
+eventq_index=0
 size=64
 walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
@@ -178,6 +198,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -186,6 +207,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -200,12 +222,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -215,6 +240,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -224,7 +250,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -238,11 +265,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -255,6 +284,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -264,5 +294,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
index c59dbb1..bb364e5 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:35:57
-gem5 started Oct 16 2013 01:41:56
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:10:34
+gem5 started Jan 22 2014 17:30:10
+gem5 executing on u200540-lin
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index ff37d4b..017ee75 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    28358000                       # Number of ticks simulated
 final_tick                                   28358000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  41834                       # Simulator instruction rate (inst/s)
-host_op_rate                                    75775                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              220409714                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 245252                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
+host_inst_rate                                  44998                       # Simulator instruction rate (inst/s)
+host_op_rate                                    81497                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              237030591                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 247544                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             14528                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8576                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                23104                       # Number of bytes read from this memory
@@ -44,6 +46,8 @@
 system.membus.reqLayer0.utilization               1.3                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            3249000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             11.5                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            56716                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -78,6 +82,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   105.550219                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.051538                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.051538                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          228                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          132                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.111328                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses             13958                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            13958                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         6637                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            6637                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          6637                       # number of demand (read+write) hits
@@ -158,6 +168,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003221                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000869                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.004090                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          282                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          115                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          167                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.008606                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             3257                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            3257                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
@@ -281,6 +297,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data    80.797237                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.019726                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.019726                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          134                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           33                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          101                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.032715                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              4110                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             4110                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data          998                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             998                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          856                       # number of WriteReq hits

diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index 708085c..39d7de9 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini

@@ -159,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -175,6 +176,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
@@ -504,6 +506,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -520,6 +523,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
@@ -529,10 +533,12 @@
 [system.cpu.isa0]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.isa1]
 type=AlphaISA
 eventq_index=0
+system=system
 
 [system.cpu.itb]
 type=AlphaTLB
@@ -554,6 +560,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -570,6 +577,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
@@ -596,7 +604,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -616,7 +624,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864

diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index d74926a..262de06 100755
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 15 2013 18:24:51
-gem5 started Oct 16 2013 01:34:33
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:31
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -11,4 +11,4 @@
 info: Increasing stack size by one page.
 Hello world!
 Hello world!
-Exiting @ tick 24404000 because target called exit()
+Exiting @ tick 24229500 because target called exit()

diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
index b482133..941a3af 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    24229500                       # Number of ticks simulated
 final_tick                                   24229500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  38113                       # Simulator instruction rate (inst/s)
-host_op_rate                                    38111                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               72448291                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 273720                       # Number of bytes of host memory used
-host_seconds                                     0.33                       # Real time elapsed on the host
+host_inst_rate                                  46987                       # Simulator instruction rate (inst/s)
+host_op_rate                                    46985                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               89318295                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231368                       # Number of bytes of host memory used
+host_seconds                                     0.27                       # Real time elapsed on the host
 sim_insts                                       12745                       # Number of instructions simulated
 sim_ops                                         12745                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             39936                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data             22464                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                62400                       # Number of bytes read from this memory
@@ -218,6 +220,7 @@
 system.membus.reqLayer0.utilization               5.1                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            9059500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             37.4                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    6676                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              3772                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect              1441                       # Number of conditional branches incorrect
@@ -656,6 +659,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   312.493120                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.152585                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.152585                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          620                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          263                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          357                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.302734                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses             11364                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            11364                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         4320                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            4320                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          4320                       # number of demand (read+write) hits
@@ -744,6 +753,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009552                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.003667                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.013219                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          829                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          337                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          492                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.025299                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             8791                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            8791                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -869,6 +884,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data   214.018929                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.052251                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.052251                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          351                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          254                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.085693                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses             11365                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses            11365                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         3448                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            3448                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data         1022                       # number of WriteReq hits

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
index 86810fe..a5a69d8 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -56,6 +60,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fetchBuffSize=4
 function_trace=false
 function_trace_start=0
@@ -90,6 +95,7 @@
 RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
+eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
 instShiftAmt=2
@@ -105,6 +111,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -113,6 +120,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -127,11 +135,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -140,6 +151,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -148,6 +160,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -162,17 +175,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.l2cache]
@@ -181,6 +199,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -189,6 +208,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -203,12 +223,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -218,6 +241,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -227,7 +251,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
+eventq_index=0
+executable=/dist/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
 max_stack_size=67108864
@@ -241,11 +266,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -265,6 +292,7 @@
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -276,17 +304,21 @@
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
index 9470739..8b0aca8 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:11:33
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 17:29:33
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -20,4 +18,4 @@
 LDTW:		Passed
 STTW:		Passed
 Done
-Exiting @ tick 27282000 because target called exit()
+Exiting @ tick 27705000 because target called exit()

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
index 9f174a0..4c8817e 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    27705000                       # Number of ticks simulated
 final_tick                                   27705000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  72386                       # Simulator instruction rate (inst/s)
-host_op_rate                                    72381                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              132251643                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 260736                       # Number of bytes of host memory used
-host_seconds                                     0.21                       # Real time elapsed on the host
+host_inst_rate                                  23200                       # Simulator instruction rate (inst/s)
+host_op_rate                                    23199                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               42390050                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236824                       # Number of bytes of host memory used
+host_seconds                                     0.65                       # Real time elapsed on the host
 sim_insts                                       15162                       # Number of instructions simulated
 sim_ops                                         15162                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             19072                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                27904                       # Number of bytes read from this memory
@@ -215,6 +217,7 @@
 system.membus.reqLayer0.utilization               1.9                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            4048750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             14.6                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    5146                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              3529                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect              2366                       # Number of conditional branches incorrect
@@ -294,6 +297,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   169.234439                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.082634                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.082634                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          299                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          221                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.145996                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses              7069                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             7069                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         3004                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            3004                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          3004                       # number of demand (read+write) hits
@@ -399,6 +408,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005144                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000969                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.006113                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          260                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010681                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             3947                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            3947                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -522,6 +537,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data    98.671839                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.024090                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.024090                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.033691                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              7484                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             7484                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         2167                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            2167                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data         1020                       # number of WriteReq hits

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
index e50ecc6..4856301 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -64,6 +68,8 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
+fetchBufferSize=64
 fetchToDecodeDelay=1
 fetchTrapLatency=1
 fetchWidth=8
@@ -128,6 +134,7 @@
 RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
+eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
 instShiftAmt=2
@@ -143,6 +150,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -151,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -165,26 +174,32 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.fuPool]
 type=FUPool
 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+eventq_index=0
 
 [system.cpu.fuPool.FUList0]
 type=FUDesc
 children=opList
 count=6
+eventq_index=0
 opList=system.cpu.fuPool.FUList0.opList
 
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=IntAlu
 opLat=1
@@ -193,16 +208,19 @@
 type=FUDesc
 children=opList0 opList1
 count=2
+eventq_index=0
 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=IntMult
 opLat=3
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=19
 opClass=IntDiv
 opLat=20
@@ -211,22 +229,26 @@
 type=FUDesc
 children=opList0 opList1 opList2
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
 
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatAdd
 opLat=2
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatCmp
 opLat=2
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatCvt
 opLat=2
@@ -235,22 +257,26 @@
 type=FUDesc
 children=opList0 opList1 opList2
 count=2
+eventq_index=0
 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
 
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=FloatMult
 opLat=4
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=12
 opClass=FloatDiv
 opLat=12
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
+eventq_index=0
 issueLat=24
 opClass=FloatSqrt
 opLat=24
@@ -259,10 +285,12 @@
 type=FUDesc
 children=opList
 count=0
+eventq_index=0
 opList=system.cpu.fuPool.FUList4.opList
 
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemRead
 opLat=1
@@ -271,124 +299,145 @@
 type=FUDesc
 children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
 
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAdd
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAddAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdAlu
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdCmp
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdCvt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMisc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMult
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdMultAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdShift
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdShiftAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdSqrt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatAdd
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatAlu
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatCmp
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatCvt
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatDiv
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMisc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMult
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
@@ -397,10 +446,12 @@
 type=FUDesc
 children=opList
 count=0
+eventq_index=0
 opList=system.cpu.fuPool.FUList6.opList
 
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemWrite
 opLat=1
@@ -409,16 +460,19 @@
 type=FUDesc
 children=opList0 opList1
 count=4
+eventq_index=0
 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemRead
 opLat=1
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
+eventq_index=0
 issueLat=1
 opClass=MemWrite
 opLat=1
@@ -427,10 +481,12 @@
 type=FUDesc
 children=opList
 count=1
+eventq_index=0
 opList=system.cpu.fuPool.FUList8.opList
 
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
+eventq_index=0
 issueLat=3
 opClass=IprAccess
 opLat=3
@@ -441,6 +497,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -449,6 +506,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -463,17 +521,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.l2cache]
@@ -482,6 +545,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -490,6 +554,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -504,12 +569,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -519,6 +587,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -528,7 +597,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
+eventq_index=0
+executable=/dist/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
 max_stack_size=67108864
@@ -542,11 +612,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -566,6 +638,7 @@
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -577,17 +650,21 @@
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[0]
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
index 3384dd1..9f4e08c 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout

@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:31:26
-gem5 started Oct 16 2013 01:35:23
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 17:29:34
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -18,4 +18,4 @@
 LDTW:		Passed
 STTW:		Passed
 Done
-Exiting @ tick 26524500 because target called exit()
+Exiting @ tick 26616500 because target called exit()

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
index dcf709c..7bcabaa 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    26616500                       # Number of ticks simulated
 final_tick                                   26616500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  75478                       # Simulator instruction rate (inst/s)
-host_op_rate                                    75473                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              139143595                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 260732                       # Number of bytes of host memory used
-host_seconds                                     0.19                       # Real time elapsed on the host
+host_inst_rate                                  19079                       # Simulator instruction rate (inst/s)
+host_op_rate                                    19079                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               35176168                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 237844                       # Number of bytes of host memory used
+host_seconds                                     0.76                       # Real time elapsed on the host
 sim_insts                                       14436                       # Number of instructions simulated
 sim_ops                                         14436                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             21440                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              9408                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                30848                       # Number of bytes read from this memory
@@ -215,6 +217,7 @@
 system.membus.reqLayer0.utilization               2.3                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            4495750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             16.9                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    6713                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              4454                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect              1076                       # Number of conditional branches incorrect
@@ -506,6 +509,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   187.514405                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.091560                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.091560                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          337                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          245                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.164551                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses             11095                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            11095                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst         4872                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            4872                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          4872                       # number of demand (read+write) hits
@@ -592,6 +601,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005704                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.001052                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.006755                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          399                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          288                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012177                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             4354                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            4354                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -715,6 +730,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data    99.106073                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.024196                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.024196                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          147                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.035889                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              9219                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             9219                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         2962                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            2962                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data         1033                       # number of WriteReq hits

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index 72cf29e..4f177ec 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -74,20 +79,25 @@
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -97,7 +107,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
+eventq_index=0
+executable=/dist/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
 max_stack_size=67108864
@@ -111,11 +122,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -128,6 +141,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -137,5 +151,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
index 7edd901..1a4f967 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr

@@ -1,3 +1 @@
-warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
index 24f0721..13e87da 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:11:45
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 17:29:44
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
index 082962e..9bfbb56 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                     7612000                       # Number of ticks simulated
 final_tick                                    7612000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 451796                       # Simulator instruction rate (inst/s)
-host_op_rate                                   451441                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              226479305                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222832                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                  25833                       # Simulator instruction rate (inst/s)
+host_op_rate                                    25832                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               12968653                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 227056                       # Number of bytes of host memory used
+host_seconds                                     0.59                       # Real time elapsed on the host
 sim_insts                                       15162                       # Number of instructions simulated
 sim_ops                                         15162                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             60828                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data             11342                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                72170                       # Number of bytes read from this memory
@@ -38,6 +40,7 @@
 system.membus.throughput                  10676563321                       # Throughput (bytes/s)
 system.membus.data_through_bus                  81270                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
 system.cpu.numCycles                            15225                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
index 77bbda9..f1f91f6 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
+eventq_index=0
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
@@ -71,6 +76,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=262144
 system=system
 tags=system.cpu.dcache.tags
@@ -93,11 +100,14 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=262144
 
 [system.cpu.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.icache]
@@ -106,6 +116,7 @@
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,6 +125,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=131072
 system=system
 tags=system.cpu.icache.tags
@@ -128,17 +140,22 @@
 assoc=2
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=131072
 
 [system.cpu.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu.l2cache]
@@ -147,6 +164,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -155,6 +173,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=2097152
 system=system
 tags=system.cpu.l2cache.tags
@@ -169,12 +188,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=2097152
 
 [system.cpu.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -184,6 +206,7 @@
 
 [system.cpu.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu.workload]
 type=LiveProcess
@@ -193,7 +216,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
+eventq_index=0
+executable=/dist/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,11 +231,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -224,6 +250,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -233,5 +260,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
index de66adf..543b5de 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:07:35
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 17:29:44
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
index 45bd7d9..6f76b11 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    41368000                       # Number of ticks simulated
 final_tick                                   41368000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 554996                       # Simulator instruction rate (inst/s)
-host_op_rate                                   554737                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1512828488                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230824                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                  30355                       # Simulator instruction rate (inst/s)
+host_op_rate                                    30353                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               82811452                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236788                       # Number of bytes of host memory used
+host_seconds                                     0.50                       # Real time elapsed on the host
 sim_insts                                       15162                       # Number of instructions simulated
 sim_ops                                         15162                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             17792                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                26624                       # Number of bytes read from this memory
@@ -42,6 +44,7 @@
 system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            3744000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              9.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
 system.cpu.numCycles                            82736                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -74,6 +77,12 @@
 system.cpu.icache.tags.occ_blocks::cpu.inst   153.782734                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.075089                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.075089                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          280                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          234                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.136719                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses             30696                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            30696                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst        14928                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total           14928                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst         14928                       # number of demand (read+write) hits
@@ -154,6 +163,12 @@
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004673                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000962                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.005635                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          331                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          275                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010101                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             3760                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            3760                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -277,6 +292,12 @@
 system.cpu.dcache.tags.occ_blocks::cpu.data    97.994344                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.023924                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.023924                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          127                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.033691                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses              7484                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             7484                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         2172                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            2172                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data         1357                       # number of WriteReq hits

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index de3e779..1b54fd8 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini

@@ -159,6 +159,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.dcache.tags
@@ -175,6 +176,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.dtb]
@@ -504,6 +506,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.icache.tags
@@ -520,6 +523,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.interrupts]
@@ -548,7 +552,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 max_stack_size=67108864
@@ -679,6 +683,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.dcache.tags
@@ -695,6 +700,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.dtb]
@@ -1024,6 +1030,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.icache.tags
@@ -1040,6 +1047,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.interrupts]
@@ -1179,6 +1187,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu2.dcache.tags
@@ -1195,6 +1204,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu2.dtb]
@@ -1524,6 +1534,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu2.icache.tags
@@ -1540,6 +1551,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu2.interrupts]
@@ -1679,6 +1691,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu3.dcache.tags
@@ -1695,6 +1708,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu3.dtb]
@@ -2024,6 +2038,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu3.icache.tags
@@ -2040,6 +2055,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu3.interrupts]
@@ -2080,6 +2096,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.l2c.tags
@@ -2096,6 +2113,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.membus]

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 0b0b9c7..26a87e0 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout

@@ -1,26 +1,26 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:31:26
-gem5 started Oct 16 2013 01:35:27
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 17:29:46
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
 [Iteration 1, Thread 2] Got lock
 [Iteration 1, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 1, Thread 1] Got lock
-[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1
 [Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 1, Thread 1] Got lock
+[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1
 Iteration 1 completed
-[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
 [Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 2, Thread 2] Got lock
+[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 2, Thread 3] Got lock
+[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 2 completed
 [Iteration 3, Thread 3] Got lock
 [Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
@@ -29,47 +29,47 @@
 [Iteration 3, Thread 2] Got lock
 [Iteration 3, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 3 completed
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 4, Thread 2] Got lock
 [Iteration 4, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 4 completed
-[Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 5, Thread 1] Got lock
 [Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 5, Thread 3] Got lock
+[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 5 completed
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
 [Iteration 6, Thread 2] Got lock
 [Iteration 6, Thread 2] Critical section done, previously next=1, now next=2
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 6 completed
-[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 7, Thread 1] Got lock
 [Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 7, Thread 3] Got lock
+[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 7 completed
-[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 8, Thread 1] Got lock
 [Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 8, Thread 2] Got lock
+[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 8 completed
-[Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
 [Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 9, Thread 2] Got lock
+[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 9, Thread 3] Got lock
+[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 9 completed
 [Iteration 10, Thread 3] Got lock
 [Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
@@ -79,4 +79,4 @@
 [Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 10 completed
 PASSED :-)
-Exiting @ tick 110804500 because target called exit()
+Exiting @ tick 111025500 because target called exit()

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 34d4262..db4434e 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                   111025500                       # Number of ticks simulated
 final_tick                                  111025500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  77886                       # Simulator instruction rate (inst/s)
-host_op_rate                                    77886                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                8289137                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 295244                       # Number of bytes of host memory used
-host_seconds                                    13.39                       # Real time elapsed on the host
+host_inst_rate                                  93081                       # Simulator instruction rate (inst/s)
+host_op_rate                                    93081                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                9906240                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253180                       # Number of bytes of host memory used
+host_seconds                                    11.21                       # Real time elapsed on the host
 sim_insts                                     1043212                       # Number of instructions simulated
 sim_ops                                       1043212                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.inst            22784                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data            10752                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.inst              640                       # Number of bytes read from this memory
@@ -246,6 +248,7 @@
 system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            6290425                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              5.7                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                        0                       # number of replacements
 system.l2c.tags.tagsinuse                  417.163639                       # Cycle average of tags in use
 system.l2c.tags.total_refs                       1442                       # Total number of references to valid blocks.
@@ -271,6 +274,13 @@
 system.l2c.tags.occ_percent::cpu3.inst       0.000047                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu3.data       0.000011                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.006365                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          526                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          293                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          182                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.008026                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                    18228                       # Number of tag accesses
+system.l2c.tags.data_accesses                   18228                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.inst                229                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.inst                412                       # number of ReadReq hits
@@ -970,6 +980,13 @@
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   241.312438                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.471313                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.471313                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          290                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          145                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2           85                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.566406                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses             6456                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses            6456                       # Number of data accesses
 system.cpu0.icache.ReadReq_hits::cpu0.inst         5113                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total           5113                       # number of ReadReq hits
 system.cpu0.icache.demand_hits::cpu0.inst         5113                       # number of demand (read+write) hits
@@ -1054,6 +1071,13 @@
 system.cpu0.dcache.tags.occ_blocks::cpu0.data   142.026071                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.277395                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.277395                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          168                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1           51                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          100                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.328125                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses           627950                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses          627950                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data        79085                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total          79085                       # number of ReadReq hits
 system.cpu0.dcache.WriteReq_hits::cpu0.data        76817                       # number of WriteReq hits
@@ -1447,6 +1471,12 @@
 system.cpu1.icache.tags.occ_blocks::cpu1.inst    76.730517                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.149864                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.149864                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024          110                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024     0.214844                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses            23807                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses           23807                       # Number of data accesses
 system.cpu1.icache.ReadReq_hits::cpu1.inst        22903                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total          22903                       # number of ReadReq hits
 system.cpu1.icache.demand_hits::cpu1.inst        22903                       # number of demand (read+write) hits
@@ -1531,6 +1561,12 @@
 system.cpu1.dcache.tags.occ_blocks::cpu1.data    23.664777                       # Average occupied blocks per requestor
 system.cpu1.dcache.tags.occ_percent::cpu1.data     0.046220                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_percent::total     0.046220                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses           290684                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses          290684                       # Number of data accesses
 system.cpu1.dcache.ReadReq_hits::cpu1.data        41736                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total          41736                       # number of ReadReq hits
 system.cpu1.dcache.WriteReq_hits::cpu1.data        30310                       # number of WriteReq hits
@@ -1921,6 +1957,12 @@
 system.cpu2.icache.tags.occ_blocks::cpu2.inst    82.236554                       # Average occupied blocks per requestor
 system.cpu2.icache.tags.occ_percent::cpu2.inst     0.160618                       # Average percentage of cache occupancy
 system.cpu2.icache.tags.occ_percent::total     0.160618                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_task_id_blocks::1024          108                       # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::1           97                       # Occupied blocks per task id
+system.cpu2.icache.tags.occ_task_id_percent::1024     0.210938                       # Percentage of cache occupancy per task id
+system.cpu2.icache.tags.tag_accesses            20176                       # Number of tag accesses
+system.cpu2.icache.tags.data_accesses           20176                       # Number of data accesses
 system.cpu2.icache.ReadReq_hits::cpu2.inst        19258                       # number of ReadReq hits
 system.cpu2.icache.ReadReq_hits::total          19258                       # number of ReadReq hits
 system.cpu2.icache.demand_hits::cpu2.inst        19258                       # number of demand (read+write) hits
@@ -2005,6 +2047,11 @@
 system.cpu2.dcache.tags.occ_blocks::cpu2.data    26.142591                       # Average occupied blocks per requestor
 system.cpu2.dcache.tags.occ_percent::cpu2.data     0.051060                       # Average percentage of cache occupancy
 system.cpu2.dcache.tags.occ_percent::total     0.051060                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
+system.cpu2.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
+system.cpu2.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
+system.cpu2.dcache.tags.tag_accesses           328789                       # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses          328789                       # Number of data accesses
 system.cpu2.dcache.ReadReq_hits::cpu2.data        45613                       # number of ReadReq hits
 system.cpu2.dcache.ReadReq_hits::total          45613                       # number of ReadReq hits
 system.cpu2.dcache.WriteReq_hits::cpu2.data        35966                       # number of WriteReq hits
@@ -2396,6 +2443,12 @@
 system.cpu3.icache.tags.occ_blocks::cpu3.inst    79.942822                       # Average occupied blocks per requestor
 system.cpu3.icache.tags.occ_percent::cpu3.inst     0.156138                       # Average percentage of cache occupancy
 system.cpu3.icache.tags.occ_percent::total     0.156138                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_task_id_blocks::1024          110                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::0           10                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
+system.cpu3.icache.tags.occ_task_id_percent::1024     0.214844                       # Percentage of cache occupancy per task id
+system.cpu3.icache.tags.tag_accesses            20994                       # Number of tag accesses
+system.cpu3.icache.tags.data_accesses           20994                       # Number of data accesses
 system.cpu3.icache.ReadReq_hits::cpu3.inst        20090                       # number of ReadReq hits
 system.cpu3.icache.ReadReq_hits::total          20090                       # number of ReadReq hits
 system.cpu3.icache.demand_hits::cpu3.inst        20090                       # number of demand (read+write) hits
@@ -2480,6 +2533,11 @@
 system.cpu3.dcache.tags.occ_blocks::cpu3.data    24.692248                       # Average occupied blocks per requestor
 system.cpu3.dcache.tags.occ_percent::cpu3.data     0.048227                       # Average percentage of cache occupancy
 system.cpu3.dcache.tags.occ_percent::total     0.048227                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
+system.cpu3.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
+system.cpu3.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
+system.cpu3.dcache.tags.tag_accesses           335202                       # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses          335202                       # Number of data accesses
 system.cpu3.dcache.ReadReq_hits::cpu3.data        46656                       # number of ReadReq hits
 system.cpu3.dcache.ReadReq_hits::total          46656                       # number of ReadReq hits
 system.cpu3.dcache.WriteReq_hits::cpu3.data        36553                       # number of WriteReq hits

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index aa7fc34..aa003ca 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu0]
@@ -45,6 +49,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu0.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -78,6 +83,7 @@
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -86,6 +92,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.dcache.tags
@@ -100,11 +107,14 @@
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu0.icache]
@@ -113,6 +123,7 @@
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -121,6 +132,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.icache.tags
@@ -135,21 +147,27 @@
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu0.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu0.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu0.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu0.workload]
 type=LiveProcess
@@ -159,7 +177,8 @@
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
+eventq_index=0
+executable=/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 max_stack_size=67108864
@@ -180,6 +199,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu1.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -213,6 +233,7 @@
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -221,6 +242,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.dcache.tags
@@ -235,11 +257,14 @@
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu1.icache]
@@ -248,6 +273,7 @@
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -256,6 +282,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.icache.tags
@@ -270,21 +297,27 @@
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu1.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu1.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu1.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu2]
 type=AtomicSimpleCPU
@@ -296,6 +329,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu2.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -329,6 +363,7 @@
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -337,6 +372,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu2.dcache.tags
@@ -351,11 +387,14 @@
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu2.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu2.icache]
@@ -364,6 +403,7 @@
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -372,6 +412,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu2.icache.tags
@@ -386,21 +427,27 @@
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu2.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu2.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu2.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu2.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu3]
 type=AtomicSimpleCPU
@@ -412,6 +459,7 @@
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu3.dtb
+eventq_index=0
 fastmem=false
 function_trace=false
 function_trace_start=0
@@ -445,6 +493,7 @@
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -453,6 +502,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu3.dcache.tags
@@ -467,11 +517,14 @@
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu3.dtb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu3.icache]
@@ -480,6 +533,7 @@
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -488,6 +542,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu3.icache.tags
@@ -502,25 +557,32 @@
 assoc=1
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu3.interrupts]
 type=SparcInterrupts
+eventq_index=0
 
 [system.cpu3.isa]
 type=SparcISA
+eventq_index=0
 
 [system.cpu3.itb]
 type=SparcTLB
+eventq_index=0
 size=64
 
 [system.cpu3.tracer]
 type=ExeTracer
+eventq_index=0
 
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.l2c]
@@ -529,6 +591,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -537,6 +600,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.l2c.tags
@@ -551,12 +615,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -569,6 +636,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -579,6 +647,7 @@
 [system.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -588,5 +657,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
index a3bbfbb..79edf97 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:09:34
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 17:29:52
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 8179c99..6a51ab3 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                    87707000                       # Number of ticks simulated
 final_tick                                   87707000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 170274                       # Simulator instruction rate (inst/s)
-host_op_rate                                   170274                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               22048637                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 246052                       # Number of bytes of host memory used
-host_seconds                                     3.98                       # Real time elapsed on the host
+host_inst_rate                                  84570                       # Simulator instruction rate (inst/s)
+host_op_rate                                    84570                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               10950892                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 249088                       # Number of bytes of host memory used
+host_seconds                                     8.01                       # Real time elapsed on the host
 sim_insts                                      677327                       # Number of instructions simulated
 sim_ops                                        677327                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.inst            18048                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data            10560                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.inst             3968                       # Number of bytes read from this memory
@@ -60,6 +62,7 @@
 system.membus.throughput                    407903588                       # Throughput (bytes/s)
 system.membus.data_through_bus                  35776                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                        0                       # number of replacements
 system.l2c.tags.tagsinuse                  366.582542                       # Cycle average of tags in use
 system.l2c.tags.total_refs                       1220                       # Total number of references to valid blocks.
@@ -85,6 +88,12 @@
 system.l2c.tags.occ_percent::cpu3.inst       0.000015                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu3.data       0.000014                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.005594                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          421                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          373                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.006424                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                    15488                       # Number of tag accesses
+system.l2c.tags.data_accesses                   15488                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.inst                185                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.inst                296                       # number of ReadReq hits
@@ -273,6 +282,12 @@
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   222.772698                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.435103                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.435103                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          252                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          199                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.492188                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses           175855                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses          175855                       # Number of data accesses
 system.cpu0.icache.ReadReq_hits::cpu0.inst       174921                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total         174921                       # number of ReadReq hits
 system.cpu0.icache.demand_hits::cpu0.inst       174921                       # number of demand (read+write) hits
@@ -315,6 +330,12 @@
 system.cpu0.dcache.tags.occ_blocks::cpu0.data   150.745494                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.294425                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.294425                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          165                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.322266                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses           329803                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses          329803                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data        54430                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total          54430                       # number of ReadReq hits
 system.cpu0.dcache.WriteReq_hits::cpu0.data        27578                       # number of WriteReq hits
@@ -397,6 +418,12 @@
 system.cpu1.icache.tags.occ_blocks::cpu1.inst    76.751702                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.149906                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.149906                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024           80                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024     0.156250                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses           167788                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses          167788                       # Number of data accesses
 system.cpu1.icache.ReadReq_hits::cpu1.inst       167072                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total         167072                       # number of ReadReq hits
 system.cpu1.icache.demand_hits::cpu1.inst       167072                       # number of demand (read+write) hits
@@ -439,6 +466,11 @@
 system.cpu1.dcache.tags.occ_blocks::cpu1.data    30.316999                       # Average occupied blocks per requestor
 system.cpu1.dcache.tags.occ_percent::cpu1.data     0.059213                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_percent::total     0.059213                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024           26                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.050781                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses           213800                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses          213800                       # Number of data accesses
 system.cpu1.dcache.ReadReq_hits::cpu1.data        40470                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total          40470                       # number of ReadReq hits
 system.cpu1.dcache.WriteReq_hits::cpu1.data        12563                       # number of WriteReq hits
@@ -519,6 +551,12 @@
 system.cpu2.icache.tags.occ_blocks::cpu2.inst    74.781015                       # Average occupied blocks per requestor
 system.cpu2.icache.tags.occ_percent::cpu2.inst     0.146057                       # Average percentage of cache occupancy
 system.cpu2.icache.tags.occ_percent::total     0.146057                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_task_id_blocks::1024           80                       # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
+system.cpu2.icache.tags.occ_task_id_percent::1024     0.156250                       # Percentage of cache occupancy per task id
+system.cpu2.icache.tags.tag_accesses           167724                       # Number of tag accesses
+system.cpu2.icache.tags.data_accesses          167724                       # Number of data accesses
 system.cpu2.icache.ReadReq_hits::cpu2.inst       167008                       # number of ReadReq hits
 system.cpu2.icache.ReadReq_hits::total         167008                       # number of ReadReq hits
 system.cpu2.icache.demand_hits::cpu2.inst       167008                       # number of demand (read+write) hits
@@ -561,6 +599,11 @@
 system.cpu2.dcache.tags.occ_blocks::cpu2.data    29.605505                       # Average occupied blocks per requestor
 system.cpu2.dcache.tags.occ_percent::cpu2.data     0.057823                       # Average percentage of cache occupancy
 system.cpu2.dcache.tags.occ_percent::total     0.057823                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_task_id_blocks::1024           26                       # Occupied blocks per task id
+system.cpu2.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
+system.cpu2.dcache.tags.occ_task_id_percent::1024     0.050781                       # Percentage of cache occupancy per task id
+system.cpu2.dcache.tags.tag_accesses           234360                       # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses          234360                       # Number of data accesses
 system.cpu2.dcache.ReadReq_hits::cpu2.data        42194                       # number of ReadReq hits
 system.cpu2.dcache.ReadReq_hits::total          42194                       # number of ReadReq hits
 system.cpu2.dcache.WriteReq_hits::cpu2.data        15998                       # number of WriteReq hits
@@ -641,6 +684,12 @@
 system.cpu3.icache.tags.occ_blocks::cpu3.inst    72.874497                       # Average occupied blocks per requestor
 system.cpu3.icache.tags.occ_percent::cpu3.inst     0.142333                       # Average percentage of cache occupancy
 system.cpu3.icache.tags.occ_percent::total     0.142333                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_task_id_blocks::1024           80                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
+system.cpu3.icache.tags.occ_task_id_percent::1024     0.156250                       # Percentage of cache occupancy per task id
+system.cpu3.icache.tags.tag_accesses           167660                       # Number of tag accesses
+system.cpu3.icache.tags.data_accesses          167660                       # Number of data accesses
 system.cpu3.icache.ReadReq_hits::cpu3.inst       166942                       # number of ReadReq hits
 system.cpu3.icache.ReadReq_hits::total         166942                       # number of ReadReq hits
 system.cpu3.icache.demand_hits::cpu3.inst       166942                       # number of demand (read+write) hits
@@ -683,6 +732,12 @@
 system.cpu3.dcache.tags.occ_blocks::cpu3.data    28.795404                       # Average occupied blocks per requestor
 system.cpu3.dcache.tags.occ_percent::cpu3.data     0.056241                       # Average percentage of cache occupancy
 system.cpu3.dcache.tags.occ_percent::total     0.056241                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_task_id_blocks::1024           27                       # Occupied blocks per task id
+system.cpu3.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
+system.cpu3.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
+system.cpu3.dcache.tags.occ_task_id_percent::1024     0.052734                       # Percentage of cache occupancy per task id
+system.cpu3.dcache.tags.tag_accesses           223805                       # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses          223805                       # Number of data accesses
 system.cpu3.dcache.ReadReq_hits::cpu3.data        41301                       # number of ReadReq hits
 system.cpu3.dcache.ReadReq_hits::total          41301                       # number of ReadReq hits
 system.cpu3.dcache.WriteReq_hits::cpu3.data        14260                       # number of WriteReq hits

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index fc54ba8..f42d1a5 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini

@@ -85,6 +85,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.dcache.tags
@@ -101,6 +102,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.dtb]
@@ -123,6 +125,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.icache.tags
@@ -139,6 +142,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu0.interrupts]
@@ -167,7 +171,7 @@
 errout=cerr
 euid=100
 eventq_index=0
-executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 max_stack_size=67108864
@@ -224,6 +228,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.dcache.tags
@@ -240,6 +245,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.dtb]
@@ -262,6 +268,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.icache.tags
@@ -278,6 +285,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1.interrupts]
@@ -343,6 +351,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu2.dcache.tags
@@ -359,6 +368,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu2.dtb]
@@ -381,6 +391,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu2.icache.tags
@@ -397,6 +408,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu2.interrupts]
@@ -462,6 +474,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu3.dcache.tags
@@ -478,6 +491,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu3.dtb]
@@ -500,6 +514,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu3.icache.tags
@@ -516,6 +531,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu3.interrupts]
@@ -556,6 +572,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.l2c.tags
@@ -572,6 +589,7 @@
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.membus]

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr
index e45cd05..1a4f967 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr

@@ -1,2 +1 @@
 warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
index 7a29b18..f700798 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:10:12
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 17:29:55
+gem5 executing on u200540-lin
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index 8d5cb34..bea653a 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt

@@ -4,13 +4,15 @@
 sim_ticks                                   262794500                       # Number of ticks simulated
 final_tick                                  262794500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 200508                       # Simulator instruction rate (inst/s)
-host_op_rate                                   200507                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               79406810                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 291148                       # Number of bytes of host memory used
-host_seconds                                     3.31                       # Real time elapsed on the host
+host_inst_rate                                  87015                       # Simulator instruction rate (inst/s)
+host_op_rate                                    87015                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               34460789                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 249056                       # Number of bytes of host memory used
+host_seconds                                     7.63                       # Real time elapsed on the host
 sim_insts                                      663567                       # Number of instructions simulated
 sim_ops                                        663567                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.inst            18240                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data            10560                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.inst             3776                       # Number of bytes read from this memory
@@ -74,6 +76,7 @@
 system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
 system.membus.respLayer1.occupancy            5420500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              2.1                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                        0                       # number of replacements
 system.l2c.tags.tagsinuse                  349.046072                       # Cycle average of tags in use
 system.l2c.tags.total_refs                       1220                       # Total number of references to valid blocks.
@@ -99,6 +102,12 @@
 system.l2c.tags.occ_percent::cpu3.inst       0.000016                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu3.data       0.000013                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.005326                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          429                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          374                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.006546                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                    15709                       # Number of tag accesses
+system.l2c.tags.data_accesses                   15709                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.inst                182                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.inst                300                       # number of ReadReq hits
@@ -560,6 +569,12 @@
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   212.401822                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.414847                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_percent::total     0.414847                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          252                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          199                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024     0.492188                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses           159104                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses          159104                       # Number of data accesses
 system.cpu0.icache.ReadReq_hits::cpu0.inst       158170                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total         158170                       # number of ReadReq hits
 system.cpu0.icache.demand_hits::cpu0.inst       158170                       # number of demand (read+write) hits
@@ -638,6 +653,12 @@
 system.cpu0.dcache.tags.occ_blocks::cpu0.data   145.571924                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.284320                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.284320                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          165                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          149                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.322266                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses           296317                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses          296317                       # Number of data accesses
 system.cpu0.dcache.ReadReq_hits::cpu0.data        48827                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total          48827                       # number of ReadReq hits
 system.cpu0.dcache.WriteReq_hits::cpu0.data        24780                       # number of WriteReq hits
@@ -780,6 +801,13 @@
 system.cpu1.icache.tags.occ_blocks::cpu1.inst    70.017504                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.136753                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_percent::total     0.136753                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
+system.cpu1.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
+system.cpu1.icache.tags.tag_accesses           163870                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses          163870                       # Number of data accesses
 system.cpu1.icache.ReadReq_hits::cpu1.inst       163138                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total         163138                       # number of ReadReq hits
 system.cpu1.icache.demand_hits::cpu1.inst       163138                       # number of demand (read+write) hits
@@ -858,6 +886,12 @@
 system.cpu1.dcache.tags.occ_blocks::cpu1.data    27.720196                       # Average occupied blocks per requestor
 system.cpu1.dcache.tags.occ_percent::cpu1.data     0.054141                       # Average percentage of cache occupancy
 system.cpu1.dcache.tags.occ_percent::total     0.054141                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024           30                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.058594                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses           232288                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses          232288                       # Number of data accesses
 system.cpu1.dcache.ReadReq_hits::cpu1.data        41378                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total          41378                       # number of ReadReq hits
 system.cpu1.dcache.WriteReq_hits::cpu1.data        16307                       # number of WriteReq hits
@@ -998,6 +1032,13 @@
 system.cpu2.icache.tags.occ_blocks::cpu2.inst    67.624960                       # Average occupied blocks per requestor
 system.cpu2.icache.tags.occ_percent::cpu2.inst     0.132080                       # Average percentage of cache occupancy
 system.cpu2.icache.tags.occ_percent::total     0.132080                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
+system.cpu2.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
+system.cpu2.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
+system.cpu2.icache.tags.tag_accesses           165265                       # Number of tag accesses
+system.cpu2.icache.tags.data_accesses          165265                       # Number of data accesses
 system.cpu2.icache.ReadReq_hits::cpu2.inst       164533                       # number of ReadReq hits
 system.cpu2.icache.ReadReq_hits::total         164533                       # number of ReadReq hits
 system.cpu2.icache.demand_hits::cpu2.inst       164533                       # number of demand (read+write) hits
@@ -1076,6 +1117,12 @@
 system.cpu2.dcache.tags.occ_blocks::cpu2.data    26.763890                       # Average occupied blocks per requestor
 system.cpu2.dcache.tags.occ_percent::cpu2.data     0.052273                       # Average percentage of cache occupancy
 system.cpu2.dcache.tags.occ_percent::total     0.052273                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
+system.cpu2.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
+system.cpu2.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu2.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
+system.cpu2.dcache.tags.tag_accesses           237038                       # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses          237038                       # Number of data accesses
 system.cpu2.dcache.ReadReq_hits::cpu2.data        42011                       # number of ReadReq hits
 system.cpu2.dcache.ReadReq_hits::total          42011                       # number of ReadReq hits
 system.cpu2.dcache.WriteReq_hits::cpu2.data        16865                       # number of WriteReq hits
@@ -1216,6 +1263,13 @@
 system.cpu3.icache.tags.occ_blocks::cpu3.inst    65.598437                       # Average occupied blocks per requestor
 system.cpu3.icache.tags.occ_percent::cpu3.inst     0.128122                       # Average percentage of cache occupancy
 system.cpu3.icache.tags.occ_percent::total     0.128122                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_task_id_blocks::1024           86                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::0            9                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::1            8                       # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
+system.cpu3.icache.tags.occ_task_id_percent::1024     0.167969                       # Percentage of cache occupancy per task id
+system.cpu3.icache.tags.tag_accesses           177056                       # Number of tag accesses
+system.cpu3.icache.tags.data_accesses          177056                       # Number of data accesses
 system.cpu3.icache.ReadReq_hits::cpu3.inst       176322                       # number of ReadReq hits
 system.cpu3.icache.ReadReq_hits::total         176322                       # number of ReadReq hits
 system.cpu3.icache.demand_hits::cpu3.inst       176322                       # number of demand (read+write) hits
@@ -1294,6 +1348,12 @@
 system.cpu3.dcache.tags.occ_blocks::cpu3.data    25.915086                       # Average occupied blocks per requestor
 system.cpu3.dcache.tags.occ_percent::cpu3.data     0.050615                       # Average percentage of cache occupancy
 system.cpu3.dcache.tags.occ_percent::total     0.050615                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
+system.cpu3.dcache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
+system.cpu3.dcache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu3.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
+system.cpu3.dcache.tags.tag_accesses           184905                       # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses          184905                       # Number of data accesses
 system.cpu3.dcache.ReadReq_hits::cpu3.data        39563                       # number of ReadReq hits
 system.cpu3.dcache.ReadReq_hits::total          39563                       # number of ReadReq hits
 system.cpu3.dcache.WriteReq_hits::cpu3.data         6216                       # number of WriteReq hits

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
index d0c477d..6c3b665 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr

@@ -79,4 +79,3 @@
 system.cpu5: completed 90000 read, 48384 write accesses @6637212
 system.cpu3: completed 90000 read, 48869 write accesses @6654178
 system.cpu6: completed 100000 read, 53414 write accesses @7257449
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout
index 53312cb..d030573 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout

@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:27:02
-gem5 started Sep 22 2013 05:27:23
-gem5 executing on zizzer
-command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
+gem5 compiled Jan 22 2014 16:37:52
+gem5 started Jan 22 2014 17:26:10
+gem5 executing on u200540-lin
+command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level -re tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_Two_Level
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 7257449 because maximum number of loads reached

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
index 1737064..6ebaf56 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt

@@ -4,9 +4,12 @@
 sim_ticks                                     7257449                       # Number of ticks simulated
 final_tick                                    7257449                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  68193                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 302480                       # Number of bytes of host memory used
-host_seconds                                   106.43                       # Real time elapsed on the host
+host_tick_rate                                 104409                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 258924                       # Number of bytes of host memory used
+host_seconds                                    69.51                       # Real time elapsed on the host
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                128                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                1279                       # delay histogram for all message
 system.ruby.delayHist::samples                4856797                       # delay histogram for all message
@@ -322,6 +325,7 @@
 system.ruby.network.routers08.msg_bytes.Writeback_Data::0      8120304                      
 system.ruby.network.routers08.msg_bytes.Writeback_Data::1     28664064                      
 system.ruby.network.routers08.msg_bytes.Writeback_Control::0      1656240                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.dir_cntrl0.memBuffer.memReq        817953                       # Total number of memory requests
 system.ruby.dir_cntrl0.memBuffer.memRead       604997                       # Number of memory reads
 system.ruby.dir_cntrl0.memBuffer.memWrite       212953                       # Number of memory writes
@@ -377,6 +381,7 @@
 system.ruby.network.msg_byte.Writeback_Control      4968736                      
 system.funcbus.throughput                           0                       # Throughput (bytes/s)
 system.funcbus.data_through_bus                     0                       # Total data (bytes)
+system.cpu_clk_domain.clock                         1                       # Clock period in ticks
 system.cpu0.num_reads                           99060                       # number of read accesses completed
 system.cpu0.num_writes                          53442                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
index ba91b18..53be052 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,12 +14,13 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
 mem_mode=timing
 mem_ranges=0:268435455
-memories=system.funcmem system.physmem
+memories=system.physmem system.funcmem
 num_work_ids=16
 readfile=
 symbolfile=
@@ -33,12 +36,14 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu0]
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -58,6 +63,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -77,6 +83,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -96,6 +103,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -115,6 +123,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -134,6 +143,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -153,6 +163,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -172,6 +183,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -190,11 +202,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.funcbus]
 type=NoncoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 use_default_range=false
 width=8
@@ -206,6 +220,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=false
 latency=30
 latency_var=0
@@ -218,6 +233,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -226,18 +242,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=8
 random_seed=1234
 randomization=false
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -245,9 +265,10 @@
 children=directory memBuffer
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=9
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=6
+eventq_index=0
 memBuffer=system.ruby.dir_cntrl0.memBuffer
 number_of_TBEs=256
 peer=Null
@@ -258,6 +279,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -274,6 +296,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -293,7 +316,8 @@
 L1Icache=system.ruby.l1_cntrl0.L1Icache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
 l2_select_num_bits=0
 number_of_TBEs=256
 peer=Null
@@ -311,6 +335,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -325,6 +350,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -340,6 +366,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -358,7 +385,8 @@
 L1Icache=system.ruby.l1_cntrl1.L1Icache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
+eventq_index=0
 l2_select_num_bits=0
 number_of_TBEs=256
 peer=Null
@@ -376,6 +404,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -390,6 +419,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -405,6 +435,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl1.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl1.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -423,7 +454,8 @@
 L1Icache=system.ruby.l1_cntrl2.L1Icache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=2
+cluster_id=0
+eventq_index=0
 l2_select_num_bits=0
 number_of_TBEs=256
 peer=Null
@@ -441,6 +473,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -455,6 +488,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -470,6 +504,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl2.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl2.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -488,7 +523,8 @@
 L1Icache=system.ruby.l1_cntrl3.L1Icache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=3
+cluster_id=0
+eventq_index=0
 l2_select_num_bits=0
 number_of_TBEs=256
 peer=Null
@@ -506,6 +542,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -520,6 +557,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -535,6 +573,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl3.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl3.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -553,7 +592,8 @@
 L1Icache=system.ruby.l1_cntrl4.L1Icache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=4
+cluster_id=0
+eventq_index=0
 l2_select_num_bits=0
 number_of_TBEs=256
 peer=Null
@@ -571,6 +611,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -585,6 +626,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -600,6 +642,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl4.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl4.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -618,7 +661,8 @@
 L1Icache=system.ruby.l1_cntrl5.L1Icache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=5
+cluster_id=0
+eventq_index=0
 l2_select_num_bits=0
 number_of_TBEs=256
 peer=Null
@@ -636,6 +680,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -650,6 +695,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -665,6 +711,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl5.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl5.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -683,7 +730,8 @@
 L1Icache=system.ruby.l1_cntrl6.L1Icache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=6
+cluster_id=0
+eventq_index=0
 l2_select_num_bits=0
 number_of_TBEs=256
 peer=Null
@@ -701,6 +749,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -715,6 +764,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -730,6 +780,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl6.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl6.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -748,7 +799,8 @@
 L1Icache=system.ruby.l1_cntrl7.L1Icache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=7
+cluster_id=0
+eventq_index=0
 l2_select_num_bits=0
 number_of_TBEs=256
 peer=Null
@@ -766,6 +818,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -780,6 +833,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -795,6 +849,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl7.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl7.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -812,7 +867,8 @@
 L2cache=system.ruby.l2_cntrl0.L2cache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=8
+cluster_id=0
+eventq_index=0
 number_of_TBEs=256
 peer=Null
 recycle_latency=10
@@ -827,6 +883,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
@@ -840,6 +897,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -849,6 +907,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6 system.ruby.network.ext_links7 system.ruby.network.ext_links8 system.ruby.network.ext_links9
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 system.ruby.network.int_links6 system.ruby.network.int_links7 system.ruby.network.int_links8 system.ruby.network.int_links9
 number_of_virtual_networks=10
@@ -859,6 +918,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers00
 latency=1
@@ -868,6 +928,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl1
 int_node=system.ruby.network.routers01
 latency=1
@@ -877,6 +938,7 @@
 [system.ruby.network.ext_links2]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl2
 int_node=system.ruby.network.routers02
 latency=1
@@ -886,6 +948,7 @@
 [system.ruby.network.ext_links3]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl3
 int_node=system.ruby.network.routers03
 latency=1
@@ -895,6 +958,7 @@
 [system.ruby.network.ext_links4]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl4
 int_node=system.ruby.network.routers04
 latency=1
@@ -904,6 +968,7 @@
 [system.ruby.network.ext_links5]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl5
 int_node=system.ruby.network.routers05
 latency=1
@@ -913,6 +978,7 @@
 [system.ruby.network.ext_links6]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl6
 int_node=system.ruby.network.routers06
 latency=1
@@ -922,6 +988,7 @@
 [system.ruby.network.ext_links7]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl7
 int_node=system.ruby.network.routers07
 latency=1
@@ -931,6 +998,7 @@
 [system.ruby.network.ext_links8]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l2_cntrl0
 int_node=system.ruby.network.routers08
 latency=1
@@ -940,6 +1008,7 @@
 [system.ruby.network.ext_links9]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers09
 latency=1
@@ -949,6 +1018,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=10
 node_a=system.ruby.network.routers00
@@ -958,6 +1028,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=11
 node_a=system.ruby.network.routers01
@@ -967,6 +1038,7 @@
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=12
 node_a=system.ruby.network.routers02
@@ -976,6 +1048,7 @@
 [system.ruby.network.int_links3]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=13
 node_a=system.ruby.network.routers03
@@ -985,6 +1058,7 @@
 [system.ruby.network.int_links4]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=14
 node_a=system.ruby.network.routers04
@@ -994,6 +1068,7 @@
 [system.ruby.network.int_links5]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=15
 node_a=system.ruby.network.routers05
@@ -1003,6 +1078,7 @@
 [system.ruby.network.int_links6]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=16
 node_a=system.ruby.network.routers06
@@ -1012,6 +1088,7 @@
 [system.ruby.network.int_links7]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=17
 node_a=system.ruby.network.routers07
@@ -1021,6 +1098,7 @@
 [system.ruby.network.int_links8]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=18
 node_a=system.ruby.network.routers08
@@ -1030,6 +1108,7 @@
 [system.ruby.network.int_links9]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=19
 node_a=system.ruby.network.routers09
@@ -1039,80 +1118,85 @@
 [system.ruby.network.routers00]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers01]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers02]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
 [system.ruby.network.routers03]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=3
 virt_nets=10
 
 [system.ruby.network.routers04]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=4
 virt_nets=10
 
 [system.ruby.network.routers05]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=5
 virt_nets=10
 
 [system.ruby.network.routers06]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=6
 virt_nets=10
 
 [system.ruby.network.routers07]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=7
 virt_nets=10
 
 [system.ruby.network.routers08]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=8
 virt_nets=10
 
 [system.ruby.network.routers09]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=9
 virt_nets=10
 
 [system.ruby.network.routers10]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=10
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=8
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -1124,5 +1208,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
index d888f2c..96061ea 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr

@@ -79,4 +79,3 @@
 system.cpu7: completed 90000 read, 48766 write accesses @6785808
 system.cpu2: completed 90000 read, 49113 write accesses @6821790
 system.cpu6: completed 100000 read, 54332 write accesses @7481441
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
index 802dd1a..45c67b8 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:36:12
-gem5 started Sep 22 2013 05:36:22
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:42:56
+gem5 started Jan 22 2014 17:26:44
+gem5 executing on u200540-lin
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
index a1c3537..9ceb39b 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt

@@ -4,9 +4,12 @@
 sim_ticks                                     7481441                       # Number of ticks simulated
 final_tick                                    7481441                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  40706                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 305724                       # Number of bytes of host memory used
-host_seconds                                   183.79                       # Real time elapsed on the host
+host_tick_rate                                  57492                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 261156                       # Number of bytes of host memory used
+host_seconds                                   130.13                       # Real time elapsed on the host
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
 system.ruby.outstanding_req_hist::samples       619788                      
@@ -280,6 +283,7 @@
 system.ruby.network.routers08.msg_bytes.Forwarded_Control::0        67368                      
 system.ruby.network.routers08.msg_bytes.Invalidate_Control::0          152                      
 system.ruby.network.routers08.msg_bytes.Unblock_Control::2      9858144                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.dir_cntrl0.memBuffer.memReq        820394                       # Total number of memory requests
 system.ruby.dir_cntrl0.memBuffer.memRead       605143                       # Number of memory reads
 system.ruby.dir_cntrl0.memBuffer.memWrite       215243                       # Number of memory writes
@@ -359,6 +363,7 @@
 system.ruby.network.msg_byte.Unblock_Control     29574432                      
 system.funcbus.throughput                           0                       # Throughput (bytes/s)
 system.funcbus.data_through_bus                     0                       # Total data (bytes)
+system.cpu_clk_domain.clock                         1                       # Clock period in ticks
 system.cpu0.num_reads                           99553                       # number of read accesses completed
 system.cpu0.num_writes                          54274                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
index a202baa..4e078b1 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,12 +36,14 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu0]
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -58,6 +63,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -77,6 +83,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -96,6 +103,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -115,6 +123,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -134,6 +143,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -153,6 +163,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -172,6 +183,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -190,11 +202,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.funcbus]
 type=NoncoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 use_default_range=false
 width=8
@@ -206,6 +220,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=false
 latency=30
 latency_var=0
@@ -218,6 +233,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -226,18 +242,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=8
 random_seed=1234
 randomization=false
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -245,10 +265,11 @@
 children=directory memBuffer
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=9
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=5
 distributed_persistent=true
+eventq_index=0
 fixed_timeout_latency=100
 l2_select_num_bits=0
 memBuffer=system.ruby.dir_cntrl0.memBuffer
@@ -262,6 +283,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -278,6 +300,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -298,8 +321,9 @@
 N_tokens=9
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
 dynamic_timeout_enabled=true
+eventq_index=0
 fixed_timeout_latency=300
 l1_request_latency=2
 l1_response_latency=2
@@ -322,6 +346,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -336,6 +361,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -351,6 +377,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -370,8 +397,9 @@
 N_tokens=9
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
 dynamic_timeout_enabled=true
+eventq_index=0
 fixed_timeout_latency=300
 l1_request_latency=2
 l1_response_latency=2
@@ -394,6 +422,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -408,6 +437,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -423,6 +453,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl1.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl1.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -442,8 +473,9 @@
 N_tokens=9
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=2
+cluster_id=0
 dynamic_timeout_enabled=true
+eventq_index=0
 fixed_timeout_latency=300
 l1_request_latency=2
 l1_response_latency=2
@@ -466,6 +498,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -480,6 +513,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -495,6 +529,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl2.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl2.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -514,8 +549,9 @@
 N_tokens=9
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=3
+cluster_id=0
 dynamic_timeout_enabled=true
+eventq_index=0
 fixed_timeout_latency=300
 l1_request_latency=2
 l1_response_latency=2
@@ -538,6 +574,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -552,6 +589,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -567,6 +605,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl3.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl3.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -586,8 +625,9 @@
 N_tokens=9
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=4
+cluster_id=0
 dynamic_timeout_enabled=true
+eventq_index=0
 fixed_timeout_latency=300
 l1_request_latency=2
 l1_response_latency=2
@@ -610,6 +650,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -624,6 +665,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -639,6 +681,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl4.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl4.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -658,8 +701,9 @@
 N_tokens=9
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=5
+cluster_id=0
 dynamic_timeout_enabled=true
+eventq_index=0
 fixed_timeout_latency=300
 l1_request_latency=2
 l1_response_latency=2
@@ -682,6 +726,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -696,6 +741,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -711,6 +757,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl5.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl5.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -730,8 +777,9 @@
 N_tokens=9
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=6
+cluster_id=0
 dynamic_timeout_enabled=true
+eventq_index=0
 fixed_timeout_latency=300
 l1_request_latency=2
 l1_response_latency=2
@@ -754,6 +802,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -768,6 +817,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -783,6 +833,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl6.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl6.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -802,8 +853,9 @@
 N_tokens=9
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=7
+cluster_id=0
 dynamic_timeout_enabled=true
+eventq_index=0
 fixed_timeout_latency=300
 l1_request_latency=2
 l1_response_latency=2
@@ -826,6 +878,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -840,6 +893,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -855,6 +909,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl7.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl7.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -873,7 +928,8 @@
 N_tokens=9
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=8
+cluster_id=0
+eventq_index=0
 filtering_enabled=true
 l2_request_latency=5
 l2_response_latency=5
@@ -889,6 +945,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
@@ -902,6 +959,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -911,6 +969,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6 system.ruby.network.ext_links7 system.ruby.network.ext_links8 system.ruby.network.ext_links9
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 system.ruby.network.int_links6 system.ruby.network.int_links7 system.ruby.network.int_links8 system.ruby.network.int_links9
 number_of_virtual_networks=10
@@ -921,6 +980,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers00
 latency=1
@@ -930,6 +990,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl1
 int_node=system.ruby.network.routers01
 latency=1
@@ -939,6 +1000,7 @@
 [system.ruby.network.ext_links2]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl2
 int_node=system.ruby.network.routers02
 latency=1
@@ -948,6 +1010,7 @@
 [system.ruby.network.ext_links3]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl3
 int_node=system.ruby.network.routers03
 latency=1
@@ -957,6 +1020,7 @@
 [system.ruby.network.ext_links4]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl4
 int_node=system.ruby.network.routers04
 latency=1
@@ -966,6 +1030,7 @@
 [system.ruby.network.ext_links5]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl5
 int_node=system.ruby.network.routers05
 latency=1
@@ -975,6 +1040,7 @@
 [system.ruby.network.ext_links6]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl6
 int_node=system.ruby.network.routers06
 latency=1
@@ -984,6 +1050,7 @@
 [system.ruby.network.ext_links7]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl7
 int_node=system.ruby.network.routers07
 latency=1
@@ -993,6 +1060,7 @@
 [system.ruby.network.ext_links8]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l2_cntrl0
 int_node=system.ruby.network.routers08
 latency=1
@@ -1002,6 +1070,7 @@
 [system.ruby.network.ext_links9]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers09
 latency=1
@@ -1011,6 +1080,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=10
 node_a=system.ruby.network.routers00
@@ -1020,6 +1090,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=11
 node_a=system.ruby.network.routers01
@@ -1029,6 +1100,7 @@
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=12
 node_a=system.ruby.network.routers02
@@ -1038,6 +1110,7 @@
 [system.ruby.network.int_links3]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=13
 node_a=system.ruby.network.routers03
@@ -1047,6 +1120,7 @@
 [system.ruby.network.int_links4]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=14
 node_a=system.ruby.network.routers04
@@ -1056,6 +1130,7 @@
 [system.ruby.network.int_links5]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=15
 node_a=system.ruby.network.routers05
@@ -1065,6 +1140,7 @@
 [system.ruby.network.int_links6]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=16
 node_a=system.ruby.network.routers06
@@ -1074,6 +1150,7 @@
 [system.ruby.network.int_links7]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=17
 node_a=system.ruby.network.routers07
@@ -1083,6 +1160,7 @@
 [system.ruby.network.int_links8]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=18
 node_a=system.ruby.network.routers08
@@ -1092,6 +1170,7 @@
 [system.ruby.network.int_links9]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=19
 node_a=system.ruby.network.routers09
@@ -1101,80 +1180,85 @@
 [system.ruby.network.routers00]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers01]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers02]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
 [system.ruby.network.routers03]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=3
 virt_nets=10
 
 [system.ruby.network.routers04]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=4
 virt_nets=10
 
 [system.ruby.network.routers05]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=5
 virt_nets=10
 
 [system.ruby.network.routers06]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=6
 virt_nets=10
 
 [system.ruby.network.routers07]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=7
 virt_nets=10
 
 [system.ruby.network.routers08]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=8
 virt_nets=10
 
 [system.ruby.network.routers09]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=9
 virt_nets=10
 
 [system.ruby.network.routers10]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=10
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=8
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -1186,5 +1270,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
index 03befb1..78259ab 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr

@@ -79,4 +79,3 @@
 system.cpu4: completed 90000 read, 48720 write accesses @5589754
 system.cpu6: completed 90000 read, 49134 write accesses @5592253
 system.cpu0: completed 100000 read, 54250 write accesses @6151475
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
index 9d06307..b764ed2 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:44:48
-gem5 started Sep 22 2013 05:44:59
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:47:59
+gem5 started Jan 22 2014 17:27:37
+gem5 executing on u200540-lin
 command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
index 83fd022..7d7ea19 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt

@@ -4,9 +4,12 @@
 sim_ticks                                     6151475                       # Number of ticks simulated
 final_tick                                    6151475                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  45886                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303616                       # Number of bytes of host memory used
-host_seconds                                   134.06                       # Real time elapsed on the host
+host_tick_rate                                  74061                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 259044                       # Number of bytes of host memory used
+host_seconds                                    83.06                       # Real time elapsed on the host
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
 system.ruby.outstanding_req_hist::samples       617095                      
@@ -245,6 +248,7 @@
 system.ruby.network.routers08.msg_bytes.Writeback_Data::4     61234056                      
 system.ruby.network.routers08.msg_bytes.Writeback_Control::4      3020648                      
 system.ruby.network.routers08.msg_bytes.Persistent_Control::3      2077536                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.dir_cntrl0.memBuffer.memReq        844944                       # Total number of memory requests
 system.ruby.dir_cntrl0.memBuffer.memRead       610587                       # Number of memory reads
 system.ruby.dir_cntrl0.memBuffer.memWrite       234338                       # Number of memory writes
@@ -318,6 +322,7 @@
 system.ruby.network.msg_byte.Persistent_Control     41550720                      
 system.funcbus.throughput                           0                       # Throughput (bytes/s)
 system.funcbus.data_through_bus                     0                       # Total data (bytes)
+system.cpu_clk_domain.clock                         1                       # Clock period in ticks
 system.cpu0.num_reads                          100000                       # number of read accesses completed
 system.cpu0.num_writes                          54250                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
index 490bbc6..bb19b17 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,12 +14,13 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
 mem_mode=timing
 mem_ranges=0:268435455
-memories=system.funcmem system.physmem
+memories=system.physmem system.funcmem
 num_work_ids=16
 readfile=
 symbolfile=
@@ -33,12 +36,14 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu0]
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -58,6 +63,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -77,6 +83,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -96,6 +103,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -115,6 +123,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -134,6 +143,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -153,6 +163,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -172,6 +183,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -190,11 +202,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.funcbus]
 type=NoncoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 use_default_range=false
 width=8
@@ -206,6 +220,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=false
 latency=30
 latency_var=0
@@ -218,6 +233,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -226,18 +242,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=8
 random_seed=1234
 randomization=false
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -245,8 +265,9 @@
 children=directory memBuffer probeFilter
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=8
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
+eventq_index=0
 full_bit_dir_enabled=false
 memBuffer=system.ruby.dir_cntrl0.memBuffer
 memory_controller_latency=2
@@ -261,6 +282,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -277,6 +299,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -294,6 +317,7 @@
 assoc=4
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=1
 replacement_policy=PSEUDO_LRU
@@ -312,7 +336,8 @@
 buffer_size=0
 cache_response_latency=10
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
 issue_latency=2
 l2_cache_hit_latency=10
 no_mig_atomic=true
@@ -330,6 +355,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -344,6 +370,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -358,6 +385,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
@@ -373,6 +401,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -393,7 +422,8 @@
 buffer_size=0
 cache_response_latency=10
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
+eventq_index=0
 issue_latency=2
 l2_cache_hit_latency=10
 no_mig_atomic=true
@@ -411,6 +441,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -425,6 +456,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -439,6 +471,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
@@ -454,6 +487,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl1.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl1.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -474,7 +508,8 @@
 buffer_size=0
 cache_response_latency=10
 clk_domain=system.ruby.clk_domain
-cntrl_id=2
+cluster_id=0
+eventq_index=0
 issue_latency=2
 l2_cache_hit_latency=10
 no_mig_atomic=true
@@ -492,6 +527,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -506,6 +542,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -520,6 +557,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
@@ -535,6 +573,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl2.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl2.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -555,7 +594,8 @@
 buffer_size=0
 cache_response_latency=10
 clk_domain=system.ruby.clk_domain
-cntrl_id=3
+cluster_id=0
+eventq_index=0
 issue_latency=2
 l2_cache_hit_latency=10
 no_mig_atomic=true
@@ -573,6 +613,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -587,6 +628,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -601,6 +643,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
@@ -616,6 +659,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl3.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl3.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -636,7 +680,8 @@
 buffer_size=0
 cache_response_latency=10
 clk_domain=system.ruby.clk_domain
-cntrl_id=4
+cluster_id=0
+eventq_index=0
 issue_latency=2
 l2_cache_hit_latency=10
 no_mig_atomic=true
@@ -654,6 +699,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -668,6 +714,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -682,6 +729,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
@@ -697,6 +745,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl4.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl4.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -717,7 +766,8 @@
 buffer_size=0
 cache_response_latency=10
 clk_domain=system.ruby.clk_domain
-cntrl_id=5
+cluster_id=0
+eventq_index=0
 issue_latency=2
 l2_cache_hit_latency=10
 no_mig_atomic=true
@@ -735,6 +785,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -749,6 +800,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -763,6 +815,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
@@ -778,6 +831,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl5.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl5.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -798,7 +852,8 @@
 buffer_size=0
 cache_response_latency=10
 clk_domain=system.ruby.clk_domain
-cntrl_id=6
+cluster_id=0
+eventq_index=0
 issue_latency=2
 l2_cache_hit_latency=10
 no_mig_atomic=true
@@ -816,6 +871,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -830,6 +886,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -844,6 +901,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
@@ -859,6 +917,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl6.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl6.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -879,7 +938,8 @@
 buffer_size=0
 cache_response_latency=10
 clk_domain=system.ruby.clk_domain
-cntrl_id=7
+cluster_id=0
+eventq_index=0
 issue_latency=2
 l2_cache_hit_latency=10
 no_mig_atomic=true
@@ -897,6 +957,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -911,6 +972,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -925,6 +987,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
@@ -940,6 +1003,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl7.L1Dcache
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl7.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -955,6 +1019,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -964,6 +1029,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6 system.ruby.network.ext_links7 system.ruby.network.ext_links8
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 system.ruby.network.int_links6 system.ruby.network.int_links7 system.ruby.network.int_links8
 number_of_virtual_networks=10
@@ -974,6 +1040,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -983,6 +1050,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl1
 int_node=system.ruby.network.routers1
 latency=1
@@ -992,6 +1060,7 @@
 [system.ruby.network.ext_links2]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl2
 int_node=system.ruby.network.routers2
 latency=1
@@ -1001,6 +1070,7 @@
 [system.ruby.network.ext_links3]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl3
 int_node=system.ruby.network.routers3
 latency=1
@@ -1010,6 +1080,7 @@
 [system.ruby.network.ext_links4]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl4
 int_node=system.ruby.network.routers4
 latency=1
@@ -1019,6 +1090,7 @@
 [system.ruby.network.ext_links5]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl5
 int_node=system.ruby.network.routers5
 latency=1
@@ -1028,6 +1100,7 @@
 [system.ruby.network.ext_links6]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl6
 int_node=system.ruby.network.routers6
 latency=1
@@ -1037,6 +1110,7 @@
 [system.ruby.network.ext_links7]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl7
 int_node=system.ruby.network.routers7
 latency=1
@@ -1046,6 +1120,7 @@
 [system.ruby.network.ext_links8]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers8
 latency=1
@@ -1055,6 +1130,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=9
 node_a=system.ruby.network.routers0
@@ -1064,6 +1140,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=10
 node_a=system.ruby.network.routers1
@@ -1073,6 +1150,7 @@
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=11
 node_a=system.ruby.network.routers2
@@ -1082,6 +1160,7 @@
 [system.ruby.network.int_links3]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=12
 node_a=system.ruby.network.routers3
@@ -1091,6 +1170,7 @@
 [system.ruby.network.int_links4]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=13
 node_a=system.ruby.network.routers4
@@ -1100,6 +1180,7 @@
 [system.ruby.network.int_links5]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=14
 node_a=system.ruby.network.routers5
@@ -1109,6 +1190,7 @@
 [system.ruby.network.int_links6]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=15
 node_a=system.ruby.network.routers6
@@ -1118,6 +1200,7 @@
 [system.ruby.network.int_links7]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=16
 node_a=system.ruby.network.routers7
@@ -1127,6 +1210,7 @@
 [system.ruby.network.int_links8]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=17
 node_a=system.ruby.network.routers8
@@ -1136,74 +1220,78 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
 [system.ruby.network.routers3]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=3
 virt_nets=10
 
 [system.ruby.network.routers4]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=4
 virt_nets=10
 
 [system.ruby.network.routers5]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=5
 virt_nets=10
 
 [system.ruby.network.routers6]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=6
 virt_nets=10
 
 [system.ruby.network.routers7]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=7
 virt_nets=10
 
 [system.ruby.network.routers8]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=8
 virt_nets=10
 
 [system.ruby.network.routers9]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=9
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=8
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -1215,5 +1303,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
index a5b70c1..f2f8ae7 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr

@@ -79,4 +79,3 @@
 system.cpu4: completed 90000 read, 48456 write accesses @5248509
 system.cpu7: completed 90000 read, 48936 write accesses @5260982
 system.cpu2: completed 100000 read, 54294 write accesses @5795833
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
index 5f64106..4c8b54d 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:17:28
-gem5 started Sep 22 2013 05:17:37
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:32:54
+gem5 started Jan 22 2014 17:25:37
+gem5 executing on u200540-lin
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
index dccaff6..c7c9aeb 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt

@@ -4,9 +4,12 @@
 sim_ticks                                     5795833                       # Number of ticks simulated
 final_tick                                    5795833                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  40133                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303548                       # Number of bytes of host memory used
-host_seconds                                   144.41                       # Real time elapsed on the host
+host_tick_rate                                  66984                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 260008                       # Number of bytes of host memory used
+host_seconds                                    86.53                       # Real time elapsed on the host
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
 system.ruby.outstanding_req_hist::samples       618244                      
@@ -280,6 +283,7 @@
 system.ruby.network.routers7.msg_bytes.Writeback_Control::5       365344                      
 system.ruby.network.routers7.msg_bytes.Broadcast_Control::3      4321008                      
 system.ruby.network.routers7.msg_bytes.Unblock_Control::5       615240                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.dir_cntrl0.memBuffer.memReq        811546                       # Total number of memory requests
 system.ruby.dir_cntrl0.memBuffer.memRead       597507                       # Number of memory reads
 system.ruby.dir_cntrl0.memBuffer.memWrite       214013                       # Number of memory writes
@@ -356,6 +360,7 @@
 system.ruby.network.msg_byte.Unblock_Control     14822312                      
 system.funcbus.throughput                           0                       # Throughput (bytes/s)
 system.funcbus.data_through_bus                     0                       # Total data (bytes)
+system.cpu_clk_domain.clock                         1                       # Clock period in ticks
 system.cpu0.num_reads                           99395                       # number of read accesses completed
 system.cpu0.num_writes                          53721                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
index cd6eb6e..717e12a 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,12 +14,13 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
 mem_mode=timing
 mem_ranges=0:268435455
-memories=system.funcmem system.physmem
+memories=system.physmem system.funcmem
 num_work_ids=16
 readfile=
 symbolfile=
@@ -33,12 +36,14 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu0]
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -58,6 +63,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -77,6 +83,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -96,6 +103,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -115,6 +123,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -134,6 +143,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -153,6 +163,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -172,6 +183,7 @@
 type=MemTest
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -190,11 +202,13 @@
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.funcbus]
 type=NoncoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 use_default_range=false
 width=8
@@ -206,6 +220,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=false
 latency=30
 latency_var=0
@@ -218,6 +233,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -226,18 +242,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=8
 random_seed=1234
 randomization=false
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -245,9 +265,10 @@
 children=directory memBuffer
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=8
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
+eventq_index=0
 memBuffer=system.ruby.dir_cntrl0.memBuffer
 number_of_TBEs=256
 peer=Null
@@ -258,6 +279,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -274,6 +296,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -293,7 +316,8 @@
 cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
 issue_latency=2
 number_of_TBEs=256
 peer=Null
@@ -309,6 +333,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -324,6 +349,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.cacheMemory
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -342,7 +368,8 @@
 cacheMemory=system.ruby.l1_cntrl1.cacheMemory
 cache_response_latency=12
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
+eventq_index=0
 issue_latency=2
 number_of_TBEs=256
 peer=Null
@@ -358,6 +385,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -373,6 +401,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl1.cacheMemory
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl1.cacheMemory
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -391,7 +420,8 @@
 cacheMemory=system.ruby.l1_cntrl2.cacheMemory
 cache_response_latency=12
 clk_domain=system.ruby.clk_domain
-cntrl_id=2
+cluster_id=0
+eventq_index=0
 issue_latency=2
 number_of_TBEs=256
 peer=Null
@@ -407,6 +437,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -422,6 +453,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl2.cacheMemory
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl2.cacheMemory
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -440,7 +472,8 @@
 cacheMemory=system.ruby.l1_cntrl3.cacheMemory
 cache_response_latency=12
 clk_domain=system.ruby.clk_domain
-cntrl_id=3
+cluster_id=0
+eventq_index=0
 issue_latency=2
 number_of_TBEs=256
 peer=Null
@@ -456,6 +489,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -471,6 +505,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl3.cacheMemory
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl3.cacheMemory
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -489,7 +524,8 @@
 cacheMemory=system.ruby.l1_cntrl4.cacheMemory
 cache_response_latency=12
 clk_domain=system.ruby.clk_domain
-cntrl_id=4
+cluster_id=0
+eventq_index=0
 issue_latency=2
 number_of_TBEs=256
 peer=Null
@@ -505,6 +541,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -520,6 +557,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl4.cacheMemory
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl4.cacheMemory
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -538,7 +576,8 @@
 cacheMemory=system.ruby.l1_cntrl5.cacheMemory
 cache_response_latency=12
 clk_domain=system.ruby.clk_domain
-cntrl_id=5
+cluster_id=0
+eventq_index=0
 issue_latency=2
 number_of_TBEs=256
 peer=Null
@@ -554,6 +593,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -569,6 +609,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl5.cacheMemory
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl5.cacheMemory
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -587,7 +628,8 @@
 cacheMemory=system.ruby.l1_cntrl6.cacheMemory
 cache_response_latency=12
 clk_domain=system.ruby.clk_domain
-cntrl_id=6
+cluster_id=0
+eventq_index=0
 issue_latency=2
 number_of_TBEs=256
 peer=Null
@@ -603,6 +645,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -618,6 +661,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl6.cacheMemory
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl6.cacheMemory
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -636,7 +680,8 @@
 cacheMemory=system.ruby.l1_cntrl7.cacheMemory
 cache_response_latency=12
 clk_domain=system.ruby.clk_domain
-cntrl_id=7
+cluster_id=0
+eventq_index=0
 issue_latency=2
 number_of_TBEs=256
 peer=Null
@@ -652,6 +697,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -667,6 +713,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl7.cacheMemory
 deadlock_threshold=1000000
+eventq_index=0
 icache=system.ruby.l1_cntrl7.cacheMemory
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -682,6 +729,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -691,6 +739,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6 system.ruby.network.ext_links7 system.ruby.network.ext_links8
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 system.ruby.network.int_links6 system.ruby.network.int_links7 system.ruby.network.int_links8
 number_of_virtual_networks=10
@@ -701,6 +750,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -710,6 +760,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl1
 int_node=system.ruby.network.routers1
 latency=1
@@ -719,6 +770,7 @@
 [system.ruby.network.ext_links2]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl2
 int_node=system.ruby.network.routers2
 latency=1
@@ -728,6 +780,7 @@
 [system.ruby.network.ext_links3]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl3
 int_node=system.ruby.network.routers3
 latency=1
@@ -737,6 +790,7 @@
 [system.ruby.network.ext_links4]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl4
 int_node=system.ruby.network.routers4
 latency=1
@@ -746,6 +800,7 @@
 [system.ruby.network.ext_links5]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl5
 int_node=system.ruby.network.routers5
 latency=1
@@ -755,6 +810,7 @@
 [system.ruby.network.ext_links6]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl6
 int_node=system.ruby.network.routers6
 latency=1
@@ -764,6 +820,7 @@
 [system.ruby.network.ext_links7]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl7
 int_node=system.ruby.network.routers7
 latency=1
@@ -773,6 +830,7 @@
 [system.ruby.network.ext_links8]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers8
 latency=1
@@ -782,6 +840,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=9
 node_a=system.ruby.network.routers0
@@ -791,6 +850,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=10
 node_a=system.ruby.network.routers1
@@ -800,6 +860,7 @@
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=11
 node_a=system.ruby.network.routers2
@@ -809,6 +870,7 @@
 [system.ruby.network.int_links3]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=12
 node_a=system.ruby.network.routers3
@@ -818,6 +880,7 @@
 [system.ruby.network.int_links4]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=13
 node_a=system.ruby.network.routers4
@@ -827,6 +890,7 @@
 [system.ruby.network.int_links5]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=14
 node_a=system.ruby.network.routers5
@@ -836,6 +900,7 @@
 [system.ruby.network.int_links6]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=15
 node_a=system.ruby.network.routers6
@@ -845,6 +910,7 @@
 [system.ruby.network.int_links7]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=16
 node_a=system.ruby.network.routers7
@@ -854,6 +920,7 @@
 [system.ruby.network.int_links8]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=17
 node_a=system.ruby.network.routers8
@@ -863,74 +930,78 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
 [system.ruby.network.routers3]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=3
 virt_nets=10
 
 [system.ruby.network.routers4]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=4
 virt_nets=10
 
 [system.ruby.network.routers5]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=5
 virt_nets=10
 
 [system.ruby.network.routers6]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=6
 virt_nets=10
 
 [system.ruby.network.routers7]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=7
 virt_nets=10
 
 [system.ruby.network.routers8]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=8
 virt_nets=10
 
 [system.ruby.network.routers9]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=9
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=8
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -942,5 +1013,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
index 082530a..5a7e36b 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr

@@ -79,4 +79,3 @@
 system.cpu5: completed 90000 read, 49075 write accesses @7851926
 system.cpu4: completed 90000 read, 49432 write accesses @7874435
 system.cpu7: completed 100000 read, 53796 write accesses @8664886
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
index 1c746b0..1137a77 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:49
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:32
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
index d75cefc..ab5af96 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt

@@ -4,9 +4,12 @@
 sim_ticks                                     8664886                       # Number of ticks simulated
 final_tick                                    8664886                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 151755                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 301056                       # Number of bytes of host memory used
-host_seconds                                    57.10                       # Real time elapsed on the host
+host_tick_rate                                 261960                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257512                       # Number of bytes of host memory used
+host_seconds                                    33.08                       # Real time elapsed on the host
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                  4                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                  39                       # delay histogram for all message
 system.ruby.delayHist::samples                1237687                       # delay histogram for all message
@@ -136,6 +139,7 @@
 system.ruby.network.routers7.msg_bytes.Data::2      5512896                      
 system.ruby.network.routers7.msg_bytes.Response_Data::4      5637312                      
 system.ruby.network.routers7.msg_bytes.Writeback_Control::3       620680                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.dir_cntrl0.memBuffer.memReq       1218678                       # Total number of memory requests
 system.ruby.dir_cntrl0.memBuffer.memRead       609346                       # Number of memory reads
 system.ruby.dir_cntrl0.memBuffer.memWrite       609308                       # Number of memory writes
@@ -181,6 +185,7 @@
 system.ruby.network.msg_byte.Writeback_Control     14883240                      
 system.funcbus.throughput                           0                       # Throughput (bytes/s)
 system.funcbus.data_through_bus                     0                       # Total data (bytes)
+system.cpu_clk_domain.clock                         1                       # Clock period in ticks
 system.cpu0.num_reads                           99885                       # number of read accesses completed
 system.cpu0.num_writes                          54375                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed

diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
index 0b50bed..dd37e6b 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,12 +14,13 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
 mem_mode=timing
 mem_ranges=
-memories=system.physmem system.funcmem
+memories=system.funcmem system.physmem
 num_work_ids=16
 readfile=
 symbolfile=
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1000
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.cpu0]
@@ -40,6 +44,7 @@
 children=l1c
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -61,6 +66,7 @@
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -69,6 +75,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu0.l1c.tags
@@ -83,7 +90,9 @@
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu1]
@@ -91,6 +100,7 @@
 children=l1c
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -112,6 +122,7 @@
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -120,6 +131,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu1.l1c.tags
@@ -134,7 +146,9 @@
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu2]
@@ -142,6 +156,7 @@
 children=l1c
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -163,6 +178,7 @@
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -171,6 +187,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu2.l1c.tags
@@ -185,7 +202,9 @@
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu3]
@@ -193,6 +212,7 @@
 children=l1c
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -214,6 +234,7 @@
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -222,6 +243,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu3.l1c.tags
@@ -236,7 +258,9 @@
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu4]
@@ -244,6 +268,7 @@
 children=l1c
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -265,6 +290,7 @@
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -273,6 +299,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu4.l1c.tags
@@ -287,7 +314,9 @@
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu5]
@@ -295,6 +324,7 @@
 children=l1c
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -316,6 +346,7 @@
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -324,6 +355,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu5.l1c.tags
@@ -338,7 +370,9 @@
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu6]
@@ -346,6 +380,7 @@
 children=l1c
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -367,6 +402,7 @@
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -375,6 +411,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu6.l1c.tags
@@ -389,7 +426,9 @@
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu7]
@@ -397,6 +436,7 @@
 children=l1c
 atomic=false
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -418,6 +458,7 @@
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -426,6 +467,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu7.l1c.tags
@@ -440,17 +482,21 @@
 assoc=4
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu_clk_domain]
 type=SrcClockDomain
 clock=500
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.funcbus]
 type=NoncoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 use_default_range=false
 width=8
@@ -462,6 +508,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=false
 latency=30000
 latency_var=0
@@ -475,6 +522,7 @@
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -483,6 +531,7 @@
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=65536
 system=system
 tags=system.l2c.tags
@@ -497,12 +546,15 @@
 assoc=8
 block_size=64
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 hit_latency=20
+sequential_access=false
 size=65536
 
 [system.membus]
 type=CoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -515,6 +567,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -525,6 +578,7 @@
 [system.toL2Bus]
 type=CoherentBus
 clk_domain=system.cpu_clk_domain
+eventq_index=0
 header_cycles=1
 system=system
 use_default_range=false
@@ -534,5 +588,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
index ad8539d..084f6f6 100755
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr

@@ -71,4 +71,3 @@
 system.cpu7: completed 90000 read, 48496 write accesses @592485000
 system.cpu0: completed 90000 read, 48680 write accesses @594831500
 system.cpu3: completed 100000 read, 53536 write accesses @652606500
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simout b/tests/quick/se/50.memtest/ref/null/none/memtest/simout
index de32ac2..831211e 100755
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/simout
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simout
-Redirecting stderr to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:53:51
-gem5 started Sep 22 2013 05:53:54
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:54:17
+gem5 started Jan 22 2014 17:28:45
+gem5 executing on u200540-lin
 command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest -re tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
index 6f84c5b..d30a7aa 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt

@@ -4,9 +4,11 @@
 sim_ticks                                   652606500                       # Number of ticks simulated
 final_tick                                  652606500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                              158104978                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 355504                       # Number of bytes of host memory used
-host_seconds                                     4.13                       # Real time elapsed on the host
+host_tick_rate                              148113487                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 336812                       # Number of bytes of host memory used
+host_seconds                                     4.41                       # Real time elapsed on the host
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0                 80014                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1                 82049                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu2                 81047                       # Number of bytes read from this memory
@@ -94,6 +96,7 @@
 system.membus.reqLayer0.utilization              43.9                       # Layer utilization (%)
 system.membus.respLayer0.occupancy          311361500                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization             47.7                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                    13254                       # number of replacements
 system.l2c.tags.tagsinuse                  783.820018                       # Cycle average of tags in use
 system.l2c.tags.total_refs                     149317                       # Total number of references to valid blocks.
@@ -119,6 +122,12 @@
 system.l2c.tags.occ_percent::cpu6            0.006582                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu7            0.006846                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.765449                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024          811                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          611                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          200                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.791992                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                  1942968                       # Number of tag accesses
+system.l2c.tags.data_accesses                 1942968                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0                   10635                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1                   10552                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu2                   10744                       # number of ReadReq hits
@@ -740,6 +749,12 @@
 system.cpu0.l1c.tags.occ_blocks::cpu0      393.709596                       # Average occupied blocks per requestor
 system.cpu0.l1c.tags.occ_percent::cpu0       0.768964                       # Average percentage of cache occupancy
 system.cpu0.l1c.tags.occ_percent::total      0.768964                       # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024          400                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0          380                       # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024     0.781250                       # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses              330568                       # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses             330568                       # Number of data accesses
 system.cpu0.l1c.ReadReq_hits::cpu0               8685                       # number of ReadReq hits
 system.cpu0.l1c.ReadReq_hits::total              8685                       # number of ReadReq hits
 system.cpu0.l1c.WriteReq_hits::cpu0              1118                       # number of WriteReq hits
@@ -855,6 +870,12 @@
 system.cpu1.l1c.tags.occ_blocks::cpu1      395.298418                       # Average occupied blocks per requestor
 system.cpu1.l1c.tags.occ_percent::cpu1       0.772067                       # Average percentage of cache occupancy
 system.cpu1.l1c.tags.occ_percent::total      0.772067                       # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_task_id_blocks::1024          407                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::0          374                       # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024     0.794922                       # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses              332439                       # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses             332439                       # Number of data accesses
 system.cpu1.l1c.ReadReq_hits::cpu1               8757                       # number of ReadReq hits
 system.cpu1.l1c.ReadReq_hits::total              8757                       # number of ReadReq hits
 system.cpu1.l1c.WriteReq_hits::cpu1              1135                       # number of WriteReq hits
@@ -970,6 +991,12 @@
 system.cpu2.l1c.tags.occ_blocks::cpu2      394.859577                       # Average occupied blocks per requestor
 system.cpu2.l1c.tags.occ_percent::cpu2       0.771210                       # Average percentage of cache occupancy
 system.cpu2.l1c.tags.occ_percent::total      0.771210                       # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_task_id_blocks::1024          400                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::0          381                       # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu2.l1c.tags.occ_task_id_percent::1024     0.781250                       # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses              331261                       # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses             331261                       # Number of data accesses
 system.cpu2.l1c.ReadReq_hits::cpu2               8708                       # number of ReadReq hits
 system.cpu2.l1c.ReadReq_hits::total              8708                       # number of ReadReq hits
 system.cpu2.l1c.WriteReq_hits::cpu2              1070                       # number of WriteReq hits
@@ -1085,6 +1112,12 @@
 system.cpu3.l1c.tags.occ_blocks::cpu3      397.838914                       # Average occupied blocks per requestor
 system.cpu3.l1c.tags.occ_percent::cpu3       0.777029                       # Average percentage of cache occupancy
 system.cpu3.l1c.tags.occ_percent::total      0.777029                       # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_task_id_blocks::1024          398                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::0          380                       # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
+system.cpu3.l1c.tags.occ_task_id_percent::1024     0.777344                       # Percentage of cache occupancy per task id
+system.cpu3.l1c.tags.tag_accesses              331508                       # Number of tag accesses
+system.cpu3.l1c.tags.data_accesses             331508                       # Number of data accesses
 system.cpu3.l1c.ReadReq_hits::cpu3               8781                       # number of ReadReq hits
 system.cpu3.l1c.ReadReq_hits::total              8781                       # number of ReadReq hits
 system.cpu3.l1c.WriteReq_hits::cpu3              1109                       # number of WriteReq hits
@@ -1200,6 +1233,12 @@
 system.cpu4.l1c.tags.occ_blocks::cpu4      393.544066                       # Average occupied blocks per requestor
 system.cpu4.l1c.tags.occ_percent::cpu4       0.768641                       # Average percentage of cache occupancy
 system.cpu4.l1c.tags.occ_percent::total      0.768641                       # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_task_id_blocks::1024          404                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::0          378                       # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
+system.cpu4.l1c.tags.occ_task_id_percent::1024     0.789062                       # Percentage of cache occupancy per task id
+system.cpu4.l1c.tags.tag_accesses              331555                       # Number of tag accesses
+system.cpu4.l1c.tags.data_accesses             331555                       # Number of data accesses
 system.cpu4.l1c.ReadReq_hits::cpu4               8712                       # number of ReadReq hits
 system.cpu4.l1c.ReadReq_hits::total              8712                       # number of ReadReq hits
 system.cpu4.l1c.WriteReq_hits::cpu4              1102                       # number of WriteReq hits
@@ -1315,6 +1354,12 @@
 system.cpu5.l1c.tags.occ_blocks::cpu5      395.592742                       # Average occupied blocks per requestor
 system.cpu5.l1c.tags.occ_percent::cpu5       0.772642                       # Average percentage of cache occupancy
 system.cpu5.l1c.tags.occ_percent::total      0.772642                       # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_task_id_blocks::1024          399                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::0          375                       # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024     0.779297                       # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses              332072                       # Number of tag accesses
+system.cpu5.l1c.tags.data_accesses             332072                       # Number of data accesses
 system.cpu5.l1c.ReadReq_hits::cpu5               8824                       # number of ReadReq hits
 system.cpu5.l1c.ReadReq_hits::total              8824                       # number of ReadReq hits
 system.cpu5.l1c.WriteReq_hits::cpu5              1160                       # number of WriteReq hits
@@ -1430,6 +1475,12 @@
 system.cpu6.l1c.tags.occ_blocks::cpu6      395.582005                       # Average occupied blocks per requestor
 system.cpu6.l1c.tags.occ_percent::cpu6       0.772621                       # Average percentage of cache occupancy
 system.cpu6.l1c.tags.occ_percent::total      0.772621                       # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_task_id_blocks::1024          408                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::0          376                       # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
+system.cpu6.l1c.tags.occ_task_id_percent::1024     0.796875                       # Percentage of cache occupancy per task id
+system.cpu6.l1c.tags.tag_accesses              332017                       # Number of tag accesses
+system.cpu6.l1c.tags.data_accesses             332017                       # Number of data accesses
 system.cpu6.l1c.ReadReq_hits::cpu6               8715                       # number of ReadReq hits
 system.cpu6.l1c.ReadReq_hits::total              8715                       # number of ReadReq hits
 system.cpu6.l1c.WriteReq_hits::cpu6              1094                       # number of WriteReq hits
@@ -1545,6 +1596,12 @@
 system.cpu7.l1c.tags.occ_blocks::cpu7      394.587693                       # Average occupied blocks per requestor
 system.cpu7.l1c.tags.occ_percent::cpu7       0.770679                       # Average percentage of cache occupancy
 system.cpu7.l1c.tags.occ_percent::total      0.770679                       # Average percentage of cache occupancy
+system.cpu7.l1c.tags.occ_task_id_blocks::1024          401                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::0          370                       # Occupied blocks per task id
+system.cpu7.l1c.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
+system.cpu7.l1c.tags.occ_task_id_percent::1024     0.783203                       # Percentage of cache occupancy per task id
+system.cpu7.l1c.tags.tag_accesses              331300                       # Number of tag accesses
+system.cpu7.l1c.tags.data_accesses             331300                       # Number of data accesses
 system.cpu7.l1c.ReadReq_hits::cpu7               8635                       # number of ReadReq hits
 system.cpu7.l1c.ReadReq_hits::total              8635                       # number of ReadReq hits
 system.cpu7.l1c.WriteReq_hits::cpu7              1078                       # number of WriteReq hits

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
index f5d2abb..2b5c3b1 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr

@@ -2,4 +2,3 @@
     0.072760 rounded to 0
 warn: rounding error > tolerance
     0.072760 rounded to 0
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
index 95d13e9..941dddf 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout

@@ -1,12 +1,10 @@
-Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:27:02
-gem5 started Sep 22 2013 05:27:12
-gem5 executing on zizzer
-command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
+gem5 compiled Jan 22 2014 16:37:52
+gem5 started Jan 22 2014 17:26:11
+gem5 executing on u200540-lin
+command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level -re tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 318321 because Ruby Tester completed

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
index 07c1031..c90fc8b 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt

@@ -4,9 +4,12 @@
 sim_ticks                                      318321                       # Number of ticks simulated
 final_tick                                     318321                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                1524477                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 167184                       # Number of bytes of host memory used
-host_seconds                                     0.21                       # Real time elapsed on the host
+host_tick_rate                                2101304                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 123592                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                256                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                2559                       # delay histogram for all message
 system.ruby.delayHist::samples                   7069                       # delay histogram for all message
@@ -102,6 +105,7 @@
 system.ruby.network.routers1.msg_bytes.Writeback_Data::0        51984                      
 system.ruby.network.routers1.msg_bytes.Writeback_Data::1        36936                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::0          272                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.dir_cntrl0.memBuffer.memReq          1660                       # Total number of memory requests
 system.ruby.dir_cntrl0.memBuffer.memRead          874                       # Number of memory reads
 system.ruby.dir_cntrl0.memBuffer.memWrite          786                       # Number of memory writes

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
index 7b4a4a0..6839497 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.physmem]
@@ -40,6 +44,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -48,18 +53,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=1
 random_seed=1234
 randomization=true
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -67,9 +76,10 @@
 children=directory memBuffer
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=2
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=6
+eventq_index=0
 memBuffer=system.ruby.dir_cntrl0.memBuffer
 number_of_TBEs=256
 peer=Null
@@ -80,6 +90,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -96,6 +107,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -115,7 +127,8 @@
 L1Icache=system.ruby.l1_cntrl0.L1Icache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
 l2_select_num_bits=0
 number_of_TBEs=256
 peer=Null
@@ -133,6 +146,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -147,6 +161,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -162,6 +177,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -179,7 +195,8 @@
 L2cache=system.ruby.l2_cntrl0.L2cache
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
+eventq_index=0
 number_of_TBEs=256
 peer=Null
 recycle_latency=10
@@ -194,6 +211,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=15
 replacement_policy=PSEUDO_LRU
@@ -207,6 +225,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -216,6 +235,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
 number_of_virtual_networks=10
@@ -226,6 +246,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -235,6 +256,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l2_cntrl0
 int_node=system.ruby.network.routers1
 latency=1
@@ -244,6 +266,7 @@
 [system.ruby.network.ext_links2]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers2
 latency=1
@@ -253,6 +276,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=3
 node_a=system.ruby.network.routers0
@@ -262,6 +286,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=4
 node_a=system.ruby.network.routers1
@@ -271,6 +296,7 @@
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=5
 node_a=system.ruby.network.routers2
@@ -280,38 +306,36 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
 [system.ruby.network.routers3]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=3
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -327,6 +351,7 @@
 checks_to_complete=100
 clk_domain=system.clk_domain
 deadlock_threshold=50000
+eventq_index=0
 num_cpus=1
 system=system
 wakeup_frequency=10
@@ -335,5 +360,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
index f5d2abb..2b5c3b1 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr

@@ -2,4 +2,3 @@
     0.072760 rounded to 0
 warn: rounding error > tolerance
     0.072760 rounded to 0
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
index 2167c12..b4257bd 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:36:12
-gem5 started Sep 22 2013 05:36:22
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:42:56
+gem5 started Jan 22 2014 17:27:15
+gem5 executing on u200540-lin
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
index 6245a45..aefa03a 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt

@@ -4,9 +4,12 @@
 sim_ticks                                      327361                       # Number of ticks simulated
 final_tick                                     327361                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 557303                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 169404                       # Number of bytes of host memory used
-host_seconds                                     0.59                       # Real time elapsed on the host
+host_tick_rate                                 771883                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 124808                       # Number of bytes of host memory used
+host_seconds                                     0.42                       # Real time elapsed on the host
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
 system.ruby.outstanding_req_hist::samples         1000                      
@@ -84,6 +87,7 @@
 system.ruby.network.routers1.msg_bytes.Writeback_Control::1        13536                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::2          640                      
 system.ruby.network.routers1.msg_bytes.Unblock_Control::2        14064                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.dir_cntrl0.memBuffer.memReq          1619                       # Total number of memory requests
 system.ruby.dir_cntrl0.memBuffer.memRead          854                       # Number of memory reads
 system.ruby.dir_cntrl0.memBuffer.memWrite          765                       # Number of memory writes

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
index 7d3b90c..323ed5f 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.physmem]
@@ -40,6 +44,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -48,18 +53,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=1
 random_seed=1234
 randomization=true
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -67,10 +76,11 @@
 children=directory memBuffer
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=2
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=5
 distributed_persistent=true
+eventq_index=0
 fixed_timeout_latency=100
 l2_select_num_bits=0
 memBuffer=system.ruby.dir_cntrl0.memBuffer
@@ -84,6 +94,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -100,6 +111,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -120,8 +132,9 @@
 N_tokens=2
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
 dynamic_timeout_enabled=true
+eventq_index=0
 fixed_timeout_latency=300
 l1_request_latency=2
 l1_response_latency=2
@@ -144,6 +157,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -158,6 +172,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -173,6 +188,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -191,7 +207,8 @@
 N_tokens=2
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
+eventq_index=0
 filtering_enabled=true
 l2_request_latency=5
 l2_response_latency=5
@@ -207,6 +224,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
@@ -220,6 +238,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -229,6 +248,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
 number_of_virtual_networks=10
@@ -239,6 +259,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -248,6 +269,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l2_cntrl0
 int_node=system.ruby.network.routers1
 latency=1
@@ -257,6 +279,7 @@
 [system.ruby.network.ext_links2]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers2
 latency=1
@@ -266,6 +289,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=3
 node_a=system.ruby.network.routers0
@@ -275,6 +299,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=4
 node_a=system.ruby.network.routers1
@@ -284,6 +309,7 @@
 [system.ruby.network.int_links2]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=5
 node_a=system.ruby.network.routers2
@@ -293,38 +319,36 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
 [system.ruby.network.routers3]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=3
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -340,6 +364,7 @@
 checks_to_complete=100
 clk_domain=system.clk_domain
 deadlock_threshold=50000
+eventq_index=0
 num_cpus=1
 system=system
 wakeup_frequency=10
@@ -348,5 +373,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
index f5d2abb..2b5c3b1 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr

@@ -2,4 +2,3 @@
     0.072760 rounded to 0
 warn: rounding error > tolerance
     0.072760 rounded to 0
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
index 733c0ee..a6637bc 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
-Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:44:48
-gem5 started Sep 22 2013 05:44:59
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:47:59
+gem5 started Jan 22 2014 17:27:41
+gem5 executing on u200540-lin
 command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
index 5c157ab..389c456 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt

@@ -4,9 +4,12 @@
 sim_ticks                                      225141                       # Number of ticks simulated
 final_tick                                     225141                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                1264878                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 168320                       # Number of bytes of host memory used
-host_seconds                                     0.18                       # Real time elapsed on the host
+host_tick_rate                                1830870                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 123716                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
 system.ruby.outstanding_req_hist::samples         1007                      
@@ -83,6 +86,7 @@
 system.ruby.network.routers1.msg_bytes.Writeback_Data::4       120168                      
 system.ruby.network.routers1.msg_bytes.Writeback_Control::4          576                      
 system.ruby.network.routers1.msg_bytes.Persistent_Control::3         2984                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.dir_cntrl0.memBuffer.memReq          1655                       # Total number of memory requests
 system.ruby.dir_cntrl0.memBuffer.memRead          868                       # Number of memory reads
 system.ruby.dir_cntrl0.memBuffer.memWrite          787                       # Number of memory writes

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
index 3ff5205..e4c8141 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.physmem]
@@ -40,6 +44,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -48,18 +53,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=1
 random_seed=1234
 randomization=true
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -67,8 +76,9 @@
 children=directory memBuffer probeFilter
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
+eventq_index=0
 full_bit_dir_enabled=false
 memBuffer=system.ruby.dir_cntrl0.memBuffer
 memory_controller_latency=2
@@ -83,6 +93,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -99,6 +110,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -116,6 +128,7 @@
 assoc=4
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=1
 replacement_policy=PSEUDO_LRU
@@ -134,7 +147,8 @@
 buffer_size=0
 cache_response_latency=10
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
 issue_latency=2
 l2_cache_hit_latency=10
 no_mig_atomic=true
@@ -152,6 +166,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -166,6 +181,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=true
 latency=2
 replacement_policy=PSEUDO_LRU
@@ -180,6 +196,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=10
 replacement_policy=PSEUDO_LRU
@@ -195,6 +212,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.L1Dcache
 deadlock_threshold=500000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.L1Icache
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -210,6 +228,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -219,6 +238,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
 number_of_virtual_networks=10
@@ -229,6 +249,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -238,6 +259,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers1
 latency=1
@@ -247,6 +269,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=2
 node_a=system.ruby.network.routers0
@@ -256,6 +279,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=3
 node_a=system.ruby.network.routers1
@@ -265,32 +289,29 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -306,6 +327,7 @@
 checks_to_complete=100
 clk_domain=system.clk_domain
 deadlock_threshold=50000
+eventq_index=0
 num_cpus=1
 system=system
 wakeup_frequency=10
@@ -314,5 +336,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
index f5d2abb..2b5c3b1 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr

@@ -2,4 +2,3 @@
     0.072760 rounded to 0
 warn: rounding error > tolerance
     0.072760 rounded to 0
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
index 980451a..8f18036 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simout
-Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:17:28
-gem5 started Sep 22 2013 05:17:38
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:32:54
+gem5 started Jan 22 2014 17:25:38
+gem5 executing on u200540-lin
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
index ca2b008..618345d 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt

@@ -4,9 +4,12 @@
 sim_ticks                                      172201                       # Number of ticks simulated
 final_tick                                     172201                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                1338362                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 168248                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
+host_tick_rate                                1805084                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 124680                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.outstanding_req_hist::bucket_size            2                      
 system.ruby.outstanding_req_hist::max_bucket           19                      
 system.ruby.outstanding_req_hist::samples          986                      
@@ -40,6 +43,7 @@
 system.ruby.miss_latency_hist            |          60      7.09%      7.09% |          28      3.31%     10.40% |           1      0.12%     10.52% |           3      0.35%     10.87% |          14      1.65%     12.53% |         145     17.14%     29.67% |         352     41.61%     71.28% |         192     22.70%     93.97% |          40      4.73%     98.70% |          11      1.30%    100.00%
 system.ruby.miss_latency_hist::total              846                      
 system.ruby.Directory.incomplete_times            846                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.l1_cntrl0.L1Dcache.demand_hits           70                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          848                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Dcache.demand_accesses          918                       # Number of cache demand accesses

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
index 5aaa974..25bd77a 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -33,6 +36,7 @@
 [system.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.physmem]
@@ -40,6 +44,7 @@
 bandwidth=0.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30
 latency_var=0
@@ -48,18 +53,22 @@
 
 [system.ruby]
 type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+all_instructions=false
 block_size_bytes=64
 clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
 mem_size=268435456
 no_mem_vec=false
+num_of_sequencers=1
 random_seed=1234
 randomization=true
-stats_filename=ruby.stats
 
 [system.ruby.clk_domain]
 type=SrcClockDomain
 clock=1
+eventq_index=0
 voltage_domain=system.voltage_domain
 
 [system.ruby.dir_cntrl0]
@@ -67,9 +76,10 @@
 children=directory memBuffer
 buffer_size=0
 clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
 directory=system.ruby.dir_cntrl0.directory
 directory_latency=12
+eventq_index=0
 memBuffer=system.ruby.dir_cntrl0.memBuffer
 number_of_TBEs=256
 peer=Null
@@ -80,6 +90,7 @@
 
 [system.ruby.dir_cntrl0.directory]
 type=RubyDirectoryMemory
+eventq_index=0
 map_levels=4
 numa_high_bit=5
 size=268435456
@@ -96,6 +107,7 @@
 clk_domain=system.ruby.memctrl_clk_domain
 dimm_bit_0=12
 dimms_per_channel=2
+eventq_index=0
 mem_ctl_latency=12
 mem_fixed_delay=0
 mem_random_arbitrate=0
@@ -115,7 +127,8 @@
 cacheMemory=system.ruby.l1_cntrl0.cacheMemory
 cache_response_latency=12
 clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
 issue_latency=2
 number_of_TBEs=256
 peer=Null
@@ -131,6 +144,7 @@
 assoc=2
 dataAccessLatency=1
 dataArrayBanks=1
+eventq_index=0
 is_icache=false
 latency=3
 replacement_policy=PSEUDO_LRU
@@ -146,6 +160,7 @@
 clk_domain=system.ruby.clk_domain
 dcache=system.ruby.l1_cntrl0.cacheMemory
 deadlock_threshold=500000
+eventq_index=0
 icache=system.ruby.l1_cntrl0.cacheMemory
 max_outstanding_requests=16
 ruby_system=system.ruby
@@ -161,6 +176,7 @@
 type=DerivedClockDomain
 clk_divider=3
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 
 [system.ruby.network]
 type=SimpleNetwork
@@ -170,6 +186,7 @@
 clk_domain=system.ruby.clk_domain
 control_msg_size=8
 endpoint_bandwidth=1000
+eventq_index=0
 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
 int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
 number_of_virtual_networks=10
@@ -180,6 +197,7 @@
 [system.ruby.network.ext_links0]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.l1_cntrl0
 int_node=system.ruby.network.routers0
 latency=1
@@ -189,6 +207,7 @@
 [system.ruby.network.ext_links1]
 type=SimpleExtLink
 bandwidth_factor=16
+eventq_index=0
 ext_node=system.ruby.dir_cntrl0
 int_node=system.ruby.network.routers1
 latency=1
@@ -198,6 +217,7 @@
 [system.ruby.network.int_links0]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=2
 node_a=system.ruby.network.routers0
@@ -207,6 +227,7 @@
 [system.ruby.network.int_links1]
 type=SimpleIntLink
 bandwidth_factor=16
+eventq_index=0
 latency=1
 link_id=3
 node_a=system.ruby.network.routers1
@@ -216,32 +237,29 @@
 [system.ruby.network.routers0]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=0
 virt_nets=10
 
 [system.ruby.network.routers1]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=1
 virt_nets=10
 
 [system.ruby.network.routers2]
 type=Switch
 clk_domain=system.ruby.clk_domain
+eventq_index=0
 router_id=2
 virt_nets=10
 
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
 [system.sys_port_proxy]
 type=RubyPortProxy
 access_phys_mem=true
 clk_domain=system.clk_domain
+eventq_index=0
 ruby_system=system.ruby
 support_data_reqs=true
 support_inst_reqs=true
@@ -257,6 +275,7 @@
 checks_to_complete=100
 clk_domain=system.clk_domain
 deadlock_threshold=50000
+eventq_index=0
 num_cpus=1
 system=system
 wakeup_frequency=10
@@ -265,5 +284,6 @@
 
 [system.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
index f5d2abb..2b5c3b1 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr

@@ -2,4 +2,3 @@
     0.072760 rounded to 0
 warn: rounding error > tolerance
     0.072760 rounded to 0
-hack: be nice to actually delete the event here

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
index 6606669..f268d31 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 24 2013 03:08:53
-gem5 started Sep 28 2013 03:05:49
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:27:55
+gem5 started Jan 22 2014 17:24:37
+gem5 executing on u200540-lin
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
index 9c41d3d..67ca7d4 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt

@@ -4,9 +4,12 @@
 sim_ticks                                      221941                       # Number of ticks simulated
 final_tick                                     221941                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                2165156                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 165760                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_tick_rate                                3307860                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 122180                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                             1                       # Clock period in ticks
+system.ruby.clk_domain.clock                        1                       # Clock period in ticks
 system.ruby.delayHist::bucket_size                  2                       # delay histogram for all message
 system.ruby.delayHist::max_bucket                  19                       # delay histogram for all message
 system.ruby.delayHist::samples                   1828                       # delay histogram for all message
@@ -47,6 +50,7 @@
 system.ruby.miss_latency_hist            |           6      0.66%      0.66% |           4      0.44%      1.09% |          82      8.95%     10.04% |         594     64.85%     74.89% |         229     25.00%     99.89% |           1      0.11%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00% |           0      0.00%    100.00%
 system.ruby.miss_latency_hist::total              916                      
 system.ruby.Directory.incomplete_times            916                      
+system.ruby.memctrl_clk_domain.clock                3                       # Clock period in ticks
 system.ruby.l1_cntrl0.cacheMemory.demand_hits           38                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses          917                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses          955                       # Number of cache demand accesses

diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini
index 61b6eb3..b3c13e1 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -34,10 +37,12 @@
 type=SrcClockDomain
 children=voltage_domain
 clock=1000
+eventq_index=0
 voltage_domain=system.clk_domain.voltage_domain
 
 [system.clk_domain.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
 [system.cpu]
@@ -45,12 +50,14 @@
 clk_domain=system.clk_domain
 config_file=tests/quick/se/70.tgen/tgen-simple-dram.cfg
 elastic_req=false
+eventq_index=0
 system=system
 port=system.monitor.slave
 
 [system.membus]
 type=NoncoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 use_default_range=false
 width=16
@@ -69,6 +76,7 @@
 disable_latency_hists=false
 disable_outstanding_hists=false
 disable_transaction_hists=false
+eventq_index=0
 itt_bins=20
 itt_max_bin=100000
 latency_bins=20
@@ -93,6 +101,7 @@
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -104,13 +113,16 @@
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[0]
 

diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout
index 2426a6c..cffe931 100755
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram/simout
-Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:53:51
-gem5 started Sep 22 2013 05:53:54
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:54:17
+gem5 started Jan 22 2014 17:29:00
+gem5 executing on u200540-lin
 command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt
index 9c1ab67..9a5e1ca 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt

@@ -4,9 +4,11 @@
 sim_ticks                                100000000000                       # Number of ticks simulated
 final_tick                               100000000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                            20181472495                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 192916                       # Number of bytes of host memory used
-host_seconds                                     4.96                       # Real time elapsed on the host
+host_tick_rate                            33856013702                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 195468                       # Number of bytes of host memory used
+host_seconds                                     2.95                       # Real time elapsed on the host
+system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu              213331136                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            213331136                       # Number of bytes read from this memory
 system.physmem.num_reads::cpu                 3333299                       # Number of read requests responded to by this memory

diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
index 27a6fb9..1932695 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini

@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -34,10 +37,12 @@
 type=SrcClockDomain
 children=voltage_domain
 clock=1000
+eventq_index=0
 voltage_domain=system.clk_domain.voltage_domain
 
 [system.clk_domain.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
 [system.cpu]
@@ -45,12 +50,14 @@
 clk_domain=system.clk_domain
 config_file=tests/quick/se/70.tgen/tgen-simple-mem.cfg
 elastic_req=false
+eventq_index=0
 system=system
 port=system.monitor.slave
 
 [system.membus]
 type=NoncoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 use_default_range=false
 width=16
@@ -69,6 +76,7 @@
 disable_latency_hists=false
 disable_outstanding_hists=false
 disable_transaction_hists=false
+eventq_index=0
 itt_bins=20
 itt_max_bin=100000
 latency_bins=20
@@ -86,6 +94,7 @@
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0

diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout
index efa3fa5..ccbd215 100755
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout

@@ -1,11 +1,9 @@
-Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simout
-Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:53:51
-gem5 started Sep 22 2013 05:53:54
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:54:17
+gem5 started Jan 22 2014 17:29:05
+gem5 executing on u200540-lin
 command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...

diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
index 14b3c1d..ead0039 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt

@@ -4,9 +4,11 @@
 sim_ticks                                100000000000                       # Number of ticks simulated
 final_tick                               100000000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                             8032030639                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228596                       # Number of bytes of host memory used
-host_seconds                                    12.45                       # Real time elapsed on the host
+host_tick_rate                            14364594493                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 195500                       # Number of bytes of host memory used
+host_seconds                                     6.96                       # Real time elapsed on the host
+system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu                     64                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                   64                       # Number of bytes read from this memory
 system.physmem.bytes_written::cpu           213329152                       # Number of bytes written to this memory
commit	f3585c841e964c98911784a187fc4f081a02a0a6	[log] [tgz]
author	Ali Saidi <Ali.Saidi@ARM.com>	Fri Jan 24 15:29:33 2014 -0600
committer	Ali Saidi <Ali.Saidi@ARM.com>	Fri Jan 24 15:29:33 2014 -0600
tree	2a5a3edeaeb0ffe37ca3a04b884f8f66c7538bbf
parent	cfc4a999828a5b51f4c514e3a7c47b4eebc450b9 [diff]