Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1 | |
| 2 | ---------- Begin Simulation Statistics ---------- |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 3 | sim_seconds 2.804327 # Number of seconds simulated |
| 4 | sim_ticks 2804326619500 # Number of ticks simulated |
| 5 | final_tick 2804326619500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 6 | sim_freq 1000000000000 # Frequency of simulated ticks |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 7 | host_inst_rate 119116 # Simulator instruction rate (inst/s) |
| 8 | host_op_rate 144575 # Simulator op (including micro ops) rate (op/s) |
| 9 | host_tick_rate 2855979889 # Simulator tick rate (ticks/s) |
| 10 | host_mem_usage 563896 # Number of bytes of host memory used |
| 11 | host_seconds 981.91 # Real time elapsed on the host |
| 12 | sim_insts 116961561 # Number of instructions simulated |
| 13 | sim_ops 141959724 # Number of ops (including micro ops) simulated |
Ali Saidi | f3585c8 | 2014-01-24 15:29:33 -0600 | [diff] [blame] | 14 | system.voltage_domain.voltage 1 # Voltage in Volts |
| 15 | system.clk_domain.clock 1000 # Clock period in ticks |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 16 | system.realview.nvmem.bytes_read::cpu0.inst 640 # Number of bytes read from this memory |
| 17 | system.realview.nvmem.bytes_read::total 640 # Number of bytes read from this memory |
| 18 | system.realview.nvmem.bytes_inst_read::cpu0.inst 640 # Number of instructions bytes read from this memory |
| 19 | system.realview.nvmem.bytes_inst_read::total 640 # Number of instructions bytes read from this memory |
| 20 | system.realview.nvmem.num_reads::cpu0.inst 10 # Number of read requests responded to by this memory |
| 21 | system.realview.nvmem.num_reads::total 10 # Number of read requests responded to by this memory |
| 22 | system.realview.nvmem.bw_read::cpu0.inst 228 # Total read bandwidth from this memory (bytes/s) |
| 23 | system.realview.nvmem.bw_read::total 228 # Total read bandwidth from this memory (bytes/s) |
| 24 | system.realview.nvmem.bw_inst_read::cpu0.inst 228 # Instruction read bandwidth from this memory (bytes/s) |
| 25 | system.realview.nvmem.bw_inst_read::total 228 # Instruction read bandwidth from this memory (bytes/s) |
| 26 | system.realview.nvmem.bw_total::cpu0.inst 228 # Total bandwidth to/from this memory (bytes/s) |
| 27 | system.realview.nvmem.bw_total::total 228 # Total bandwidth to/from this memory (bytes/s) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 28 | system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 29 | system.physmem.bytes_read::cpu0.dtb.walker 4352 # Number of bytes read from this memory |
Steve Reinhardt | 5b08e21 | 2014-06-22 14:33:09 -0700 | [diff] [blame] | 30 | system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 31 | system.physmem.bytes_read::cpu0.inst 740544 # Number of bytes read from this memory |
| 32 | system.physmem.bytes_read::cpu0.data 5179680 # Number of bytes read from this memory |
| 33 | system.physmem.bytes_read::cpu1.dtb.walker 4416 # Number of bytes read from this memory |
| 34 | system.physmem.bytes_read::cpu1.inst 636864 # Number of bytes read from this memory |
| 35 | system.physmem.bytes_read::cpu1.data 4641732 # Number of bytes read from this memory |
| 36 | system.physmem.bytes_read::total 11208612 # Number of bytes read from this memory |
| 37 | system.physmem.bytes_inst_read::cpu0.inst 740544 # Number of instructions bytes read from this memory |
| 38 | system.physmem.bytes_inst_read::cpu1.inst 636864 # Number of instructions bytes read from this memory |
| 39 | system.physmem.bytes_inst_read::total 1377408 # Number of instructions bytes read from this memory |
| 40 | system.physmem.bytes_written::writebacks 6113984 # Number of bytes written to this memory |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 41 | system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory |
| 42 | system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory |
| 43 | system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 44 | system.physmem.bytes_written::total 8449844 # Number of bytes written to this memory |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 45 | system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 46 | system.physmem.num_reads::cpu0.dtb.walker 68 # Number of read requests responded to by this memory |
Steve Reinhardt | 5b08e21 | 2014-06-22 14:33:09 -0700 | [diff] [blame] | 47 | system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 48 | system.physmem.num_reads::cpu0.inst 11571 # Number of read requests responded to by this memory |
| 49 | system.physmem.num_reads::cpu0.data 81451 # Number of read requests responded to by this memory |
| 50 | system.physmem.num_reads::cpu1.dtb.walker 69 # Number of read requests responded to by this memory |
| 51 | system.physmem.num_reads::cpu1.inst 9951 # Number of read requests responded to by this memory |
| 52 | system.physmem.num_reads::cpu1.data 72528 # Number of read requests responded to by this memory |
| 53 | system.physmem.num_reads::total 175654 # Number of read requests responded to by this memory |
| 54 | system.physmem.num_writes::writebacks 95531 # Number of write requests responded to by this memory |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 55 | system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory |
| 56 | system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory |
| 57 | system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 58 | system.physmem.num_writes::total 136136 # Number of write requests responded to by this memory |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 59 | system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 60 | system.physmem.bw_read::cpu0.dtb.walker 1552 # Total read bandwidth from this memory (bytes/s) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 61 | system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 62 | system.physmem.bw_read::cpu0.inst 264072 # Total read bandwidth from this memory (bytes/s) |
| 63 | system.physmem.bw_read::cpu0.data 1847032 # Total read bandwidth from this memory (bytes/s) |
| 64 | system.physmem.bw_read::cpu1.dtb.walker 1575 # Total read bandwidth from this memory (bytes/s) |
| 65 | system.physmem.bw_read::cpu1.inst 227101 # Total read bandwidth from this memory (bytes/s) |
| 66 | system.physmem.bw_read::cpu1.data 1655204 # Total read bandwidth from this memory (bytes/s) |
| 67 | system.physmem.bw_read::total 3996900 # Total read bandwidth from this memory (bytes/s) |
| 68 | system.physmem.bw_inst_read::cpu0.inst 264072 # Instruction read bandwidth from this memory (bytes/s) |
| 69 | system.physmem.bw_inst_read::cpu1.inst 227101 # Instruction read bandwidth from this memory (bytes/s) |
| 70 | system.physmem.bw_inst_read::total 491172 # Instruction read bandwidth from this memory (bytes/s) |
| 71 | system.physmem.bw_write::writebacks 2180197 # Write bandwidth from this memory (bytes/s) |
| 72 | system.physmem.bw_write::realview.ide 826700 # Write bandwidth from this memory (bytes/s) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 73 | system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s) |
| 74 | system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 75 | system.physmem.bw_write::total 3013145 # Write bandwidth from this memory (bytes/s) |
| 76 | system.physmem.bw_total::writebacks 2180197 # Total bandwidth to/from this memory (bytes/s) |
| 77 | system.physmem.bw_total::realview.ide 827042 # Total bandwidth to/from this memory (bytes/s) |
| 78 | system.physmem.bw_total::cpu0.dtb.walker 1552 # Total bandwidth to/from this memory (bytes/s) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 79 | system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 80 | system.physmem.bw_total::cpu0.inst 264072 # Total bandwidth to/from this memory (bytes/s) |
| 81 | system.physmem.bw_total::cpu0.data 1853278 # Total bandwidth to/from this memory (bytes/s) |
| 82 | system.physmem.bw_total::cpu1.dtb.walker 1575 # Total bandwidth to/from this memory (bytes/s) |
| 83 | system.physmem.bw_total::cpu1.inst 227101 # Total bandwidth to/from this memory (bytes/s) |
| 84 | system.physmem.bw_total::cpu1.data 1655207 # Total bandwidth to/from this memory (bytes/s) |
| 85 | system.physmem.bw_total::total 7010045 # Total bandwidth to/from this memory (bytes/s) |
| 86 | system.physmem.readReqs 175655 # Number of read requests accepted |
| 87 | system.physmem.writeReqs 136136 # Number of write requests accepted |
| 88 | system.physmem.readBursts 175655 # Number of DRAM read bursts, including those serviced by the write queue |
| 89 | system.physmem.writeBursts 136136 # Number of DRAM write bursts, including those merged in the write queue |
| 90 | system.physmem.bytesReadDRAM 11233984 # Total number of bytes read from DRAM |
| 91 | system.physmem.bytesReadWrQ 7936 # Total number of bytes read from write queue |
| 92 | system.physmem.bytesWritten 8463616 # Total number of bytes written to DRAM |
| 93 | system.physmem.bytesReadSys 11208676 # Total read bytes from the system interface side |
| 94 | system.physmem.bytesWrittenSys 8449844 # Total written bytes from the system interface side |
| 95 | system.physmem.servicedByWrQ 124 # Number of DRAM read bursts serviced by the write queue |
| 96 | system.physmem.mergedWrBursts 3872 # Number of DRAM write bursts merged with an existing one |
| 97 | system.physmem.neitherReadNorWriteReqs 4658 # Number of requests that are neither read nor write |
| 98 | system.physmem.perBankRdBursts::0 11108 # Per bank write bursts |
| 99 | system.physmem.perBankRdBursts::1 11142 # Per bank write bursts |
| 100 | system.physmem.perBankRdBursts::2 11724 # Per bank write bursts |
| 101 | system.physmem.perBankRdBursts::3 11223 # Per bank write bursts |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 102 | system.physmem.perBankRdBursts::4 11369 # Per bank write bursts |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 103 | system.physmem.perBankRdBursts::5 11393 # Per bank write bursts |
| 104 | system.physmem.perBankRdBursts::6 11953 # Per bank write bursts |
| 105 | system.physmem.perBankRdBursts::7 11818 # Per bank write bursts |
| 106 | system.physmem.perBankRdBursts::8 10217 # Per bank write bursts |
| 107 | system.physmem.perBankRdBursts::9 10450 # Per bank write bursts |
| 108 | system.physmem.perBankRdBursts::10 10599 # Per bank write bursts |
| 109 | system.physmem.perBankRdBursts::11 9773 # Per bank write bursts |
| 110 | system.physmem.perBankRdBursts::12 10412 # Per bank write bursts |
| 111 | system.physmem.perBankRdBursts::13 11414 # Per bank write bursts |
| 112 | system.physmem.perBankRdBursts::14 10639 # Per bank write bursts |
| 113 | system.physmem.perBankRdBursts::15 10297 # Per bank write bursts |
| 114 | system.physmem.perBankWrBursts::0 8312 # Per bank write bursts |
| 115 | system.physmem.perBankWrBursts::1 8440 # Per bank write bursts |
| 116 | system.physmem.perBankWrBursts::2 9043 # Per bank write bursts |
| 117 | system.physmem.perBankWrBursts::3 8548 # Per bank write bursts |
| 118 | system.physmem.perBankWrBursts::4 8346 # Per bank write bursts |
| 119 | system.physmem.perBankWrBursts::5 8542 # Per bank write bursts |
| 120 | system.physmem.perBankWrBursts::6 8974 # Per bank write bursts |
| 121 | system.physmem.perBankWrBursts::7 8818 # Per bank write bursts |
| 122 | system.physmem.perBankWrBursts::8 7763 # Per bank write bursts |
| 123 | system.physmem.perBankWrBursts::9 7812 # Per bank write bursts |
| 124 | system.physmem.perBankWrBursts::10 7942 # Per bank write bursts |
| 125 | system.physmem.perBankWrBursts::11 7398 # Per bank write bursts |
| 126 | system.physmem.perBankWrBursts::12 7887 # Per bank write bursts |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 127 | system.physmem.perBankWrBursts::13 8744 # Per bank write bursts |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 128 | system.physmem.perBankWrBursts::14 8046 # Per bank write bursts |
| 129 | system.physmem.perBankWrBursts::15 7629 # Per bank write bursts |
Nilay Vaish | 2823982 | 2013-11-26 17:05:25 -0600 | [diff] [blame] | 130 | system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 131 | system.physmem.numWrRetry 14 # Number of times write queue was full causing retry |
| 132 | system.physmem.totGap 2804326433500 # Total gap between requests |
Nilay Vaish | 2823982 | 2013-11-26 17:05:25 -0600 | [diff] [blame] | 133 | system.physmem.readPktSize::0 0 # Read request sizes (log2) |
| 134 | system.physmem.readPktSize::1 0 # Read request sizes (log2) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 135 | system.physmem.readPktSize::2 541 # Read request sizes (log2) |
| 136 | system.physmem.readPktSize::3 14 # Read request sizes (log2) |
Nilay Vaish | 2823982 | 2013-11-26 17:05:25 -0600 | [diff] [blame] | 137 | system.physmem.readPktSize::4 0 # Read request sizes (log2) |
| 138 | system.physmem.readPktSize::5 0 # Read request sizes (log2) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 139 | system.physmem.readPktSize::6 175100 # Read request sizes (log2) |
Nilay Vaish | 2823982 | 2013-11-26 17:05:25 -0600 | [diff] [blame] | 140 | system.physmem.writePktSize::0 0 # Write request sizes (log2) |
| 141 | system.physmem.writePktSize::1 0 # Write request sizes (log2) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 142 | system.physmem.writePktSize::2 4381 # Write request sizes (log2) |
Nilay Vaish | 2823982 | 2013-11-26 17:05:25 -0600 | [diff] [blame] | 143 | system.physmem.writePktSize::3 0 # Write request sizes (log2) |
| 144 | system.physmem.writePktSize::4 0 # Write request sizes (log2) |
| 145 | system.physmem.writePktSize::5 0 # Write request sizes (log2) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 146 | system.physmem.writePktSize::6 131755 # Write request sizes (log2) |
| 147 | system.physmem.rdQLenPdf::0 104424 # What read queue length does an incoming req see |
| 148 | system.physmem.rdQLenPdf::1 61078 # What read queue length does an incoming req see |
| 149 | system.physmem.rdQLenPdf::2 8506 # What read queue length does an incoming req see |
| 150 | system.physmem.rdQLenPdf::3 1503 # What read queue length does an incoming req see |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 151 | system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see |
| 152 | system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see |
| 153 | system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see |
| 154 | system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see |
| 155 | system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see |
| 156 | system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see |
| 157 | system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see |
| 158 | system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see |
| 159 | system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see |
| 160 | system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see |
| 161 | system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see |
| 162 | system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see |
| 163 | system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see |
| 164 | system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see |
| 165 | system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see |
| 166 | system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see |
Andreas Hansson | 8b4b1dc | 2014-03-23 11:12:19 -0400 | [diff] [blame] | 167 | system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see |
Nilay Vaish | 2823982 | 2013-11-26 17:05:25 -0600 | [diff] [blame] | 168 | system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see |
| 169 | system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see |
| 170 | system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see |
| 171 | system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see |
| 172 | system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see |
| 173 | system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see |
| 174 | system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see |
| 175 | system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see |
| 176 | system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see |
| 177 | system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see |
| 178 | system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 179 | system.physmem.wrQLenPdf::0 106 # What write queue length does an incoming req see |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 180 | system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see |
| 181 | system.physmem.wrQLenPdf::2 93 # What write queue length does an incoming req see |
| 182 | system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 183 | system.physmem.wrQLenPdf::4 90 # What write queue length does an incoming req see |
| 184 | system.physmem.wrQLenPdf::5 89 # What write queue length does an incoming req see |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 185 | system.physmem.wrQLenPdf::6 93 # What write queue length does an incoming req see |
| 186 | system.physmem.wrQLenPdf::7 93 # What write queue length does an incoming req see |
| 187 | system.physmem.wrQLenPdf::8 93 # What write queue length does an incoming req see |
| 188 | system.physmem.wrQLenPdf::9 90 # What write queue length does an incoming req see |
| 189 | system.physmem.wrQLenPdf::10 92 # What write queue length does an incoming req see |
| 190 | system.physmem.wrQLenPdf::11 92 # What write queue length does an incoming req see |
| 191 | system.physmem.wrQLenPdf::12 92 # What write queue length does an incoming req see |
| 192 | system.physmem.wrQLenPdf::13 86 # What write queue length does an incoming req see |
| 193 | system.physmem.wrQLenPdf::14 88 # What write queue length does an incoming req see |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 194 | system.physmem.wrQLenPdf::15 2034 # What write queue length does an incoming req see |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 195 | system.physmem.wrQLenPdf::16 2586 # What write queue length does an incoming req see |
| 196 | system.physmem.wrQLenPdf::17 4529 # What write queue length does an incoming req see |
| 197 | system.physmem.wrQLenPdf::18 6433 # What write queue length does an incoming req see |
| 198 | system.physmem.wrQLenPdf::19 6799 # What write queue length does an incoming req see |
| 199 | system.physmem.wrQLenPdf::20 7535 # What write queue length does an incoming req see |
| 200 | system.physmem.wrQLenPdf::21 7769 # What write queue length does an incoming req see |
| 201 | system.physmem.wrQLenPdf::22 8333 # What write queue length does an incoming req see |
| 202 | system.physmem.wrQLenPdf::23 8830 # What write queue length does an incoming req see |
| 203 | system.physmem.wrQLenPdf::24 9585 # What write queue length does an incoming req see |
| 204 | system.physmem.wrQLenPdf::25 9109 # What write queue length does an incoming req see |
| 205 | system.physmem.wrQLenPdf::26 8670 # What write queue length does an incoming req see |
| 206 | system.physmem.wrQLenPdf::27 8281 # What write queue length does an incoming req see |
| 207 | system.physmem.wrQLenPdf::28 8757 # What write queue length does an incoming req see |
| 208 | system.physmem.wrQLenPdf::29 7217 # What write queue length does an incoming req see |
| 209 | system.physmem.wrQLenPdf::30 7138 # What write queue length does an incoming req see |
| 210 | system.physmem.wrQLenPdf::31 7317 # What write queue length does an incoming req see |
| 211 | system.physmem.wrQLenPdf::32 6805 # What write queue length does an incoming req see |
| 212 | system.physmem.wrQLenPdf::33 229 # What write queue length does an incoming req see |
| 213 | system.physmem.wrQLenPdf::34 205 # What write queue length does an incoming req see |
| 214 | system.physmem.wrQLenPdf::35 196 # What write queue length does an incoming req see |
| 215 | system.physmem.wrQLenPdf::36 176 # What write queue length does an incoming req see |
| 216 | system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see |
| 217 | system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see |
| 218 | system.physmem.wrQLenPdf::39 195 # What write queue length does an incoming req see |
| 219 | system.physmem.wrQLenPdf::40 174 # What write queue length does an incoming req see |
| 220 | system.physmem.wrQLenPdf::41 161 # What write queue length does an incoming req see |
| 221 | system.physmem.wrQLenPdf::42 150 # What write queue length does an incoming req see |
| 222 | system.physmem.wrQLenPdf::43 143 # What write queue length does an incoming req see |
| 223 | system.physmem.wrQLenPdf::44 151 # What write queue length does an incoming req see |
| 224 | system.physmem.wrQLenPdf::45 144 # What write queue length does an incoming req see |
| 225 | system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see |
| 226 | system.physmem.wrQLenPdf::47 115 # What write queue length does an incoming req see |
| 227 | system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see |
| 228 | system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 229 | system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 230 | system.physmem.wrQLenPdf::51 54 # What write queue length does an incoming req see |
| 231 | system.physmem.wrQLenPdf::52 39 # What write queue length does an incoming req see |
| 232 | system.physmem.wrQLenPdf::53 38 # What write queue length does an incoming req see |
| 233 | system.physmem.wrQLenPdf::54 29 # What write queue length does an incoming req see |
| 234 | system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see |
| 235 | system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see |
| 236 | system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see |
| 237 | system.physmem.wrQLenPdf::58 32 # What write queue length does an incoming req see |
| 238 | system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see |
| 239 | system.physmem.wrQLenPdf::60 22 # What write queue length does an incoming req see |
| 240 | system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see |
| 241 | system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see |
| 242 | system.physmem.wrQLenPdf::63 31 # What write queue length does an incoming req see |
| 243 | system.physmem.bytesPerActivate::samples 64866 # Bytes accessed per row activation |
| 244 | system.physmem.bytesPerActivate::mean 303.665033 # Bytes accessed per row activation |
| 245 | system.physmem.bytesPerActivate::gmean 178.572173 # Bytes accessed per row activation |
| 246 | system.physmem.bytesPerActivate::stdev 327.227913 # Bytes accessed per row activation |
| 247 | system.physmem.bytesPerActivate::0-127 24436 37.67% 37.67% # Bytes accessed per row activation |
| 248 | system.physmem.bytesPerActivate::128-255 15780 24.33% 62.00% # Bytes accessed per row activation |
| 249 | system.physmem.bytesPerActivate::256-383 6593 10.16% 72.16% # Bytes accessed per row activation |
| 250 | system.physmem.bytesPerActivate::384-511 3751 5.78% 77.95% # Bytes accessed per row activation |
| 251 | system.physmem.bytesPerActivate::512-639 2794 4.31% 82.25% # Bytes accessed per row activation |
| 252 | system.physmem.bytesPerActivate::640-767 1520 2.34% 84.60% # Bytes accessed per row activation |
| 253 | system.physmem.bytesPerActivate::768-895 1090 1.68% 86.28% # Bytes accessed per row activation |
| 254 | system.physmem.bytesPerActivate::896-1023 1132 1.75% 88.02% # Bytes accessed per row activation |
| 255 | system.physmem.bytesPerActivate::1024-1151 7770 11.98% 100.00% # Bytes accessed per row activation |
| 256 | system.physmem.bytesPerActivate::total 64866 # Bytes accessed per row activation |
| 257 | system.physmem.rdPerTurnAround::samples 6698 # Reads before turning the bus around for writes |
| 258 | system.physmem.rdPerTurnAround::mean 26.205584 # Reads before turning the bus around for writes |
| 259 | system.physmem.rdPerTurnAround::stdev 477.627003 # Reads before turning the bus around for writes |
| 260 | system.physmem.rdPerTurnAround::0-2047 6695 99.96% 99.96% # Reads before turning the bus around for writes |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 261 | system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.97% # Reads before turning the bus around for writes |
| 262 | system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes |
| 263 | system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 264 | system.physmem.rdPerTurnAround::total 6698 # Reads before turning the bus around for writes |
| 265 | system.physmem.wrPerTurnAround::samples 6698 # Writes before turning the bus around for reads |
| 266 | system.physmem.wrPerTurnAround::mean 19.743804 # Writes before turning the bus around for reads |
| 267 | system.physmem.wrPerTurnAround::gmean 18.225845 # Writes before turning the bus around for reads |
| 268 | system.physmem.wrPerTurnAround::stdev 11.527754 # Writes before turning the bus around for reads |
| 269 | system.physmem.wrPerTurnAround::0-3 13 0.19% 0.19% # Writes before turning the bus around for reads |
| 270 | system.physmem.wrPerTurnAround::4-7 9 0.13% 0.33% # Writes before turning the bus around for reads |
| 271 | system.physmem.wrPerTurnAround::8-11 4 0.06% 0.39% # Writes before turning the bus around for reads |
| 272 | system.physmem.wrPerTurnAround::12-15 9 0.13% 0.52% # Writes before turning the bus around for reads |
| 273 | system.physmem.wrPerTurnAround::16-19 5778 86.26% 86.79% # Writes before turning the bus around for reads |
| 274 | system.physmem.wrPerTurnAround::20-23 106 1.58% 88.37% # Writes before turning the bus around for reads |
| 275 | system.physmem.wrPerTurnAround::24-27 43 0.64% 89.01% # Writes before turning the bus around for reads |
| 276 | system.physmem.wrPerTurnAround::28-31 223 3.33% 92.34% # Writes before turning the bus around for reads |
| 277 | system.physmem.wrPerTurnAround::32-35 204 3.05% 95.39% # Writes before turning the bus around for reads |
| 278 | system.physmem.wrPerTurnAround::36-39 17 0.25% 95.64% # Writes before turning the bus around for reads |
| 279 | system.physmem.wrPerTurnAround::40-43 22 0.33% 95.97% # Writes before turning the bus around for reads |
| 280 | system.physmem.wrPerTurnAround::44-47 15 0.22% 96.19% # Writes before turning the bus around for reads |
| 281 | system.physmem.wrPerTurnAround::48-51 32 0.48% 96.67% # Writes before turning the bus around for reads |
| 282 | system.physmem.wrPerTurnAround::52-55 10 0.15% 96.82% # Writes before turning the bus around for reads |
| 283 | system.physmem.wrPerTurnAround::56-59 8 0.12% 96.94% # Writes before turning the bus around for reads |
| 284 | system.physmem.wrPerTurnAround::60-63 5 0.07% 97.01% # Writes before turning the bus around for reads |
| 285 | system.physmem.wrPerTurnAround::64-67 143 2.13% 99.15% # Writes before turning the bus around for reads |
| 286 | system.physmem.wrPerTurnAround::68-71 6 0.09% 99.24% # Writes before turning the bus around for reads |
| 287 | system.physmem.wrPerTurnAround::72-75 3 0.04% 99.28% # Writes before turning the bus around for reads |
| 288 | system.physmem.wrPerTurnAround::76-79 6 0.09% 99.37% # Writes before turning the bus around for reads |
| 289 | system.physmem.wrPerTurnAround::80-83 10 0.15% 99.52% # Writes before turning the bus around for reads |
| 290 | system.physmem.wrPerTurnAround::92-95 1 0.01% 99.54% # Writes before turning the bus around for reads |
| 291 | system.physmem.wrPerTurnAround::96-99 5 0.07% 99.61% # Writes before turning the bus around for reads |
| 292 | system.physmem.wrPerTurnAround::104-107 4 0.06% 99.67% # Writes before turning the bus around for reads |
| 293 | system.physmem.wrPerTurnAround::108-111 1 0.01% 99.69% # Writes before turning the bus around for reads |
| 294 | system.physmem.wrPerTurnAround::112-115 3 0.04% 99.73% # Writes before turning the bus around for reads |
| 295 | system.physmem.wrPerTurnAround::116-119 3 0.04% 99.78% # Writes before turning the bus around for reads |
| 296 | system.physmem.wrPerTurnAround::120-123 3 0.04% 99.82% # Writes before turning the bus around for reads |
| 297 | system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads |
| 298 | system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads |
| 299 | system.physmem.wrPerTurnAround::132-135 2 0.03% 99.99% # Writes before turning the bus around for reads |
| 300 | system.physmem.wrPerTurnAround::140-143 1 0.01% 100.00% # Writes before turning the bus around for reads |
| 301 | system.physmem.wrPerTurnAround::total 6698 # Writes before turning the bus around for reads |
| 302 | system.physmem.totQLat 2733630250 # Total ticks spent queuing |
| 303 | system.physmem.totMemAccLat 6024836500 # Total ticks spent from burst creation until serviced by the DRAM |
| 304 | system.physmem.totBusLat 877655000 # Total ticks spent in databus transfers |
| 305 | system.physmem.avgQLat 15573.49 # Average queueing delay per DRAM burst |
Nilay Vaish | 2823982 | 2013-11-26 17:05:25 -0600 | [diff] [blame] | 306 | system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 307 | system.physmem.avgMemAccLat 34323.49 # Average memory access latency per DRAM burst |
| 308 | system.physmem.avgRdBW 4.01 # Average DRAM read bandwidth in MiByte/s |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 309 | system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s |
| 310 | system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s |
| 311 | system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s |
Nilay Vaish | 2823982 | 2013-11-26 17:05:25 -0600 | [diff] [blame] | 312 | system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 313 | system.physmem.busUtil 0.05 # Data bus utilization in percentage |
| 314 | system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads |
Nilay Vaish | 2823982 | 2013-11-26 17:05:25 -0600 | [diff] [blame] | 315 | system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 316 | system.physmem.avgRdQLen 1.63 # Average read queue length when enqueuing |
| 317 | system.physmem.avgWrQLen 10.73 # Average write queue length when enqueuing |
| 318 | system.physmem.readRowHits 145110 # Number of row buffer hits during reads |
| 319 | system.physmem.writeRowHits 97798 # Number of row buffer hits during writes |
| 320 | system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads |
| 321 | system.physmem.writeRowHitRate 73.94 # Row buffer hit rate for writes |
| 322 | system.physmem.avgGap 8994250.74 # Average gap between requests |
| 323 | system.physmem.pageHitRate 78.92 # Row buffer hit rate, read and write combined |
| 324 | system.physmem.memoryStateTime::IDLE 2678438745750 # Time in different power states |
| 325 | system.physmem.memoryStateTime::REF 93642380000 # Time in different power states |
Andreas Hansson | 57e5401 | 2014-05-09 18:58:50 -0400 | [diff] [blame] | 326 | system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 327 | system.physmem.memoryStateTime::ACT 32245482750 # Time in different power states |
Andreas Hansson | 57e5401 | 2014-05-09 18:58:50 -0400 | [diff] [blame] | 328 | system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 329 | system.physmem.actEnergy::0 259141680 # Energy for activate commands per rank (pJ) |
| 330 | system.physmem.actEnergy::1 231245280 # Energy for activate commands per rank (pJ) |
| 331 | system.physmem.preEnergy::0 141396750 # Energy for precharge commands per rank (pJ) |
| 332 | system.physmem.preEnergy::1 126175500 # Energy for precharge commands per rank (pJ) |
| 333 | system.physmem.readEnergy::0 715486200 # Energy for read commands per rank (pJ) |
| 334 | system.physmem.readEnergy::1 653647800 # Energy for read commands per rank (pJ) |
| 335 | system.physmem.writeEnergy::0 447269040 # Energy for write commands per rank (pJ) |
| 336 | system.physmem.writeEnergy::1 409672080 # Energy for write commands per rank (pJ) |
| 337 | system.physmem.refreshEnergy::0 183164495280 # Energy for refresh commands per rank (pJ) |
| 338 | system.physmem.refreshEnergy::1 183164495280 # Energy for refresh commands per rank (pJ) |
| 339 | system.physmem.actBackEnergy::0 77839312860 # Energy for active background per rank (pJ) |
| 340 | system.physmem.actBackEnergy::1 76923425745 # Energy for active background per rank (pJ) |
| 341 | system.physmem.preBackEnergy::0 1614311544000 # Energy for precharge background per rank (pJ) |
| 342 | system.physmem.preBackEnergy::1 1615114953750 # Energy for precharge background per rank (pJ) |
| 343 | system.physmem.totalEnergy::0 1876878645810 # Total energy per rank (pJ) |
| 344 | system.physmem.totalEnergy::1 1876623615435 # Total energy per rank (pJ) |
| 345 | system.physmem.averagePower::0 669.281339 # Core power per rank (mW) |
| 346 | system.physmem.averagePower::1 669.190397 # Core power per rank (mW) |
| 347 | system.membus.trans_dist::ReadReq 68041 # Transaction distribution |
| 348 | system.membus.trans_dist::ReadResp 68040 # Transaction distribution |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 349 | system.membus.trans_dist::WriteReq 27608 # Transaction distribution |
| 350 | system.membus.trans_dist::WriteResp 27608 # Transaction distribution |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 351 | system.membus.trans_dist::Writeback 95531 # Transaction distribution |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 352 | system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution |
| 353 | system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 354 | system.membus.trans_dist::UpgradeReq 4632 # Transaction distribution |
| 355 | system.membus.trans_dist::SCUpgradeReq 26 # Transaction distribution |
| 356 | system.membus.trans_dist::UpgradeResp 4658 # Transaction distribution |
| 357 | system.membus.trans_dist::ReadExReq 138441 # Transaction distribution |
| 358 | system.membus.trans_dist::ReadExResp 138441 # Transaction distribution |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 359 | system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 360 | system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 20 # Packet count per connected master and slave (bytes) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 361 | system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 362 | system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464888 # Packet count per connected master and slave (bytes) |
| 363 | system.membus.pkt_count_system.l2c.mem_side::total 572528 # Packet count per connected master and slave (bytes) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 364 | system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72712 # Packet count per connected master and slave (bytes) |
| 365 | system.membus.pkt_count_system.iocache.mem_side::total 72712 # Packet count per connected master and slave (bytes) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 366 | system.membus.pkt_count::total 645240 # Packet count per connected master and slave (bytes) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 367 | system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 368 | system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 640 # Cumulative packet size per connected master and slave (bytes) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 369 | system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 370 | system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17339160 # Cumulative packet size per connected master and slave (bytes) |
| 371 | system.membus.pkt_size_system.l2c.mem_side::total 17503137 # Cumulative packet size per connected master and slave (bytes) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 372 | system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) |
| 373 | system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 374 | system.membus.pkt_size::total 19822433 # Cumulative packet size per connected master and slave (bytes) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 375 | system.membus.snoops 234 # Total snoops (count) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 376 | system.membus.snoop_fanout::samples 311110 # Request fanout histogram |
Andreas Hansson | c4e9128 | 2014-09-20 17:18:53 -0400 | [diff] [blame] | 377 | system.membus.snoop_fanout::mean 1 # Request fanout histogram |
| 378 | system.membus.snoop_fanout::stdev 0 # Request fanout histogram |
| 379 | system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 380 | system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 381 | system.membus.snoop_fanout::1 311110 100.00% 100.00% # Request fanout histogram |
Andreas Hansson | c4e9128 | 2014-09-20 17:18:53 -0400 | [diff] [blame] | 382 | system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram |
| 383 | system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 384 | system.membus.snoop_fanout::min_value 1 # Request fanout histogram |
| 385 | system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 386 | system.membus.snoop_fanout::total 311110 # Request fanout histogram |
| 387 | system.membus.reqLayer0.occupancy 81518499 # Layer occupancy (ticks) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 388 | system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 389 | system.membus.reqLayer1.occupancy 15812 # Layer occupancy (ticks) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 390 | system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 391 | system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks) |
Andreas Hansson | b636315 | 2013-08-19 03:52:36 -0400 | [diff] [blame] | 392 | system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 393 | system.membus.reqLayer5.occupancy 1434327498 # Layer occupancy (ticks) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 394 | system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 395 | system.membus.respLayer2.occupancy 1730433594 # Layer occupancy (ticks) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 396 | system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 397 | system.membus.respLayer3.occupancy 38513958 # Layer occupancy (ticks) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 398 | system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
Ali Saidi | f3585c8 | 2014-01-24 15:29:33 -0600 | [diff] [blame] | 399 | system.cpu_clk_domain.clock 500 # Clock period in ticks |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 400 | system.l2c.tags.replacements 104268 # number of replacements |
| 401 | system.l2c.tags.tagsinuse 65131.307742 # Cycle average of tags in use |
| 402 | system.l2c.tags.total_refs 3106944 # Total number of references to valid blocks. |
| 403 | system.l2c.tags.sampled_refs 169509 # Sample count of references to valid blocks. |
| 404 | system.l2c.tags.avg_refs 18.329080 # Average number of references to valid blocks. |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 405 | system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 406 | system.l2c.tags.occ_blocks::writebacks 48616.163532 # Average occupied blocks per requestor |
| 407 | system.l2c.tags.occ_blocks::cpu0.dtb.walker 48.311212 # Average occupied blocks per requestor |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 408 | system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000235 # Average occupied blocks per requestor |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 409 | system.l2c.tags.occ_blocks::cpu0.inst 5571.967356 # Average occupied blocks per requestor |
| 410 | system.l2c.tags.occ_blocks::cpu0.data 2874.440506 # Average occupied blocks per requestor |
| 411 | system.l2c.tags.occ_blocks::cpu1.dtb.walker 44.347195 # Average occupied blocks per requestor |
| 412 | system.l2c.tags.occ_blocks::cpu1.inst 4984.192297 # Average occupied blocks per requestor |
| 413 | system.l2c.tags.occ_blocks::cpu1.data 2991.885408 # Average occupied blocks per requestor |
| 414 | system.l2c.tags.occ_percent::writebacks 0.741824 # Average percentage of cache occupancy |
| 415 | system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000737 # Average percentage of cache occupancy |
Andreas Hansson | b636315 | 2013-08-19 03:52:36 -0400 | [diff] [blame] | 416 | system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 417 | system.l2c.tags.occ_percent::cpu0.inst 0.085021 # Average percentage of cache occupancy |
| 418 | system.l2c.tags.occ_percent::cpu0.data 0.043860 # Average percentage of cache occupancy |
| 419 | system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000677 # Average percentage of cache occupancy |
| 420 | system.l2c.tags.occ_percent::cpu1.inst 0.076053 # Average percentage of cache occupancy |
| 421 | system.l2c.tags.occ_percent::cpu1.data 0.045653 # Average percentage of cache occupancy |
| 422 | system.l2c.tags.occ_percent::total 0.993825 # Average percentage of cache occupancy |
| 423 | system.l2c.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id |
| 424 | system.l2c.tags.occ_task_id_blocks::1024 65178 # Occupied blocks per task id |
| 425 | system.l2c.tags.age_task_id_blocks_1023::4 63 # Occupied blocks per task id |
| 426 | system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id |
| 427 | system.l2c.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id |
| 428 | system.l2c.tags.age_task_id_blocks_1024::2 3243 # Occupied blocks per task id |
| 429 | system.l2c.tags.age_task_id_blocks_1024::3 8995 # Occupied blocks per task id |
| 430 | system.l2c.tags.age_task_id_blocks_1024::4 52594 # Occupied blocks per task id |
| 431 | system.l2c.tags.occ_task_id_percent::1023 0.000961 # Percentage of cache occupancy per task id |
| 432 | system.l2c.tags.occ_task_id_percent::1024 0.994537 # Percentage of cache occupancy per task id |
| 433 | system.l2c.tags.tag_accesses 29221748 # Number of tag accesses |
| 434 | system.l2c.tags.data_accesses 29221748 # Number of data accesses |
| 435 | system.l2c.ReadReq_hits::cpu0.dtb.walker 36519 # number of ReadReq hits |
| 436 | system.l2c.ReadReq_hits::cpu0.itb.walker 8855 # number of ReadReq hits |
| 437 | system.l2c.ReadReq_hits::cpu0.inst 959908 # number of ReadReq hits |
| 438 | system.l2c.ReadReq_hits::cpu0.data 271615 # number of ReadReq hits |
| 439 | system.l2c.ReadReq_hits::cpu1.dtb.walker 36602 # number of ReadReq hits |
| 440 | system.l2c.ReadReq_hits::cpu1.itb.walker 7424 # number of ReadReq hits |
| 441 | system.l2c.ReadReq_hits::cpu1.inst 964068 # number of ReadReq hits |
| 442 | system.l2c.ReadReq_hits::cpu1.data 269451 # number of ReadReq hits |
| 443 | system.l2c.ReadReq_hits::total 2554442 # number of ReadReq hits |
| 444 | system.l2c.Writeback_hits::writebacks 703423 # number of Writeback hits |
| 445 | system.l2c.Writeback_hits::total 703423 # number of Writeback hits |
| 446 | system.l2c.UpgradeReq_hits::cpu0.data 37 # number of UpgradeReq hits |
| 447 | system.l2c.UpgradeReq_hits::cpu1.data 59 # number of UpgradeReq hits |
| 448 | system.l2c.UpgradeReq_hits::total 96 # number of UpgradeReq hits |
| 449 | system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits |
| 450 | system.l2c.SCUpgradeReq_hits::cpu1.data 32 # number of SCUpgradeReq hits |
| 451 | system.l2c.SCUpgradeReq_hits::total 53 # number of SCUpgradeReq hits |
| 452 | system.l2c.ReadExReq_hits::cpu0.data 77798 # number of ReadExReq hits |
| 453 | system.l2c.ReadExReq_hits::cpu1.data 78748 # number of ReadExReq hits |
| 454 | system.l2c.ReadExReq_hits::total 156546 # number of ReadExReq hits |
| 455 | system.l2c.demand_hits::cpu0.dtb.walker 36519 # number of demand (read+write) hits |
| 456 | system.l2c.demand_hits::cpu0.itb.walker 8855 # number of demand (read+write) hits |
| 457 | system.l2c.demand_hits::cpu0.inst 959908 # number of demand (read+write) hits |
| 458 | system.l2c.demand_hits::cpu0.data 349413 # number of demand (read+write) hits |
| 459 | system.l2c.demand_hits::cpu1.dtb.walker 36602 # number of demand (read+write) hits |
| 460 | system.l2c.demand_hits::cpu1.itb.walker 7424 # number of demand (read+write) hits |
| 461 | system.l2c.demand_hits::cpu1.inst 964068 # number of demand (read+write) hits |
| 462 | system.l2c.demand_hits::cpu1.data 348199 # number of demand (read+write) hits |
| 463 | system.l2c.demand_hits::total 2710988 # number of demand (read+write) hits |
| 464 | system.l2c.overall_hits::cpu0.dtb.walker 36519 # number of overall hits |
| 465 | system.l2c.overall_hits::cpu0.itb.walker 8855 # number of overall hits |
| 466 | system.l2c.overall_hits::cpu0.inst 959908 # number of overall hits |
| 467 | system.l2c.overall_hits::cpu0.data 349413 # number of overall hits |
| 468 | system.l2c.overall_hits::cpu1.dtb.walker 36602 # number of overall hits |
| 469 | system.l2c.overall_hits::cpu1.itb.walker 7424 # number of overall hits |
| 470 | system.l2c.overall_hits::cpu1.inst 964068 # number of overall hits |
| 471 | system.l2c.overall_hits::cpu1.data 348199 # number of overall hits |
| 472 | system.l2c.overall_hits::total 2710988 # number of overall hits |
| 473 | system.l2c.ReadReq_misses::cpu0.dtb.walker 68 # number of ReadReq misses |
Steve Reinhardt | 5b08e21 | 2014-06-22 14:33:09 -0700 | [diff] [blame] | 474 | system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 475 | system.l2c.ReadReq_misses::cpu0.inst 10928 # number of ReadReq misses |
| 476 | system.l2c.ReadReq_misses::cpu0.data 7151 # number of ReadReq misses |
| 477 | system.l2c.ReadReq_misses::cpu1.dtb.walker 69 # number of ReadReq misses |
| 478 | system.l2c.ReadReq_misses::cpu1.inst 9955 # number of ReadReq misses |
| 479 | system.l2c.ReadReq_misses::cpu1.data 7971 # number of ReadReq misses |
| 480 | system.l2c.ReadReq_misses::total 36143 # number of ReadReq misses |
| 481 | system.l2c.UpgradeReq_misses::cpu0.data 1299 # number of UpgradeReq misses |
| 482 | system.l2c.UpgradeReq_misses::cpu1.data 1443 # number of UpgradeReq misses |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 483 | system.l2c.UpgradeReq_misses::total 2742 # number of UpgradeReq misses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 484 | system.l2c.SCUpgradeReq_misses::cpu0.data 8 # number of SCUpgradeReq misses |
| 485 | system.l2c.SCUpgradeReq_misses::cpu1.data 18 # number of SCUpgradeReq misses |
| 486 | system.l2c.SCUpgradeReq_misses::total 26 # number of SCUpgradeReq misses |
| 487 | system.l2c.ReadExReq_misses::cpu0.data 74760 # number of ReadExReq misses |
| 488 | system.l2c.ReadExReq_misses::cpu1.data 65571 # number of ReadExReq misses |
| 489 | system.l2c.ReadExReq_misses::total 140331 # number of ReadExReq misses |
| 490 | system.l2c.demand_misses::cpu0.dtb.walker 68 # number of demand (read+write) misses |
Steve Reinhardt | 5b08e21 | 2014-06-22 14:33:09 -0700 | [diff] [blame] | 491 | system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 492 | system.l2c.demand_misses::cpu0.inst 10928 # number of demand (read+write) misses |
| 493 | system.l2c.demand_misses::cpu0.data 81911 # number of demand (read+write) misses |
| 494 | system.l2c.demand_misses::cpu1.dtb.walker 69 # number of demand (read+write) misses |
| 495 | system.l2c.demand_misses::cpu1.inst 9955 # number of demand (read+write) misses |
| 496 | system.l2c.demand_misses::cpu1.data 73542 # number of demand (read+write) misses |
| 497 | system.l2c.demand_misses::total 176474 # number of demand (read+write) misses |
| 498 | system.l2c.overall_misses::cpu0.dtb.walker 68 # number of overall misses |
Steve Reinhardt | 5b08e21 | 2014-06-22 14:33:09 -0700 | [diff] [blame] | 499 | system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 500 | system.l2c.overall_misses::cpu0.inst 10928 # number of overall misses |
| 501 | system.l2c.overall_misses::cpu0.data 81911 # number of overall misses |
| 502 | system.l2c.overall_misses::cpu1.dtb.walker 69 # number of overall misses |
| 503 | system.l2c.overall_misses::cpu1.inst 9955 # number of overall misses |
| 504 | system.l2c.overall_misses::cpu1.data 73542 # number of overall misses |
| 505 | system.l2c.overall_misses::total 176474 # number of overall misses |
| 506 | system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 5396500 # number of ReadReq miss cycles |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 507 | system.l2c.ReadReq_miss_latency::cpu0.itb.walker 74500 # number of ReadReq miss cycles |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 508 | system.l2c.ReadReq_miss_latency::cpu0.inst 829990750 # number of ReadReq miss cycles |
| 509 | system.l2c.ReadReq_miss_latency::cpu0.data 573729742 # number of ReadReq miss cycles |
| 510 | system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 5378000 # number of ReadReq miss cycles |
| 511 | system.l2c.ReadReq_miss_latency::cpu1.inst 749581500 # number of ReadReq miss cycles |
| 512 | system.l2c.ReadReq_miss_latency::cpu1.data 653390493 # number of ReadReq miss cycles |
| 513 | system.l2c.ReadReq_miss_latency::total 2817541485 # number of ReadReq miss cycles |
| 514 | system.l2c.UpgradeReq_miss_latency::cpu0.data 304487 # number of UpgradeReq miss cycles |
| 515 | system.l2c.UpgradeReq_miss_latency::cpu1.data 465980 # number of UpgradeReq miss cycles |
| 516 | system.l2c.UpgradeReq_miss_latency::total 770467 # number of UpgradeReq miss cycles |
| 517 | system.l2c.SCUpgradeReq_miss_latency::cpu0.data 116995 # number of SCUpgradeReq miss cycles |
| 518 | system.l2c.SCUpgradeReq_miss_latency::cpu1.data 162993 # number of SCUpgradeReq miss cycles |
| 519 | system.l2c.SCUpgradeReq_miss_latency::total 279988 # number of SCUpgradeReq miss cycles |
| 520 | system.l2c.ReadExReq_miss_latency::cpu0.data 5741255809 # number of ReadExReq miss cycles |
| 521 | system.l2c.ReadExReq_miss_latency::cpu1.data 5109104302 # number of ReadExReq miss cycles |
| 522 | system.l2c.ReadExReq_miss_latency::total 10850360111 # number of ReadExReq miss cycles |
| 523 | system.l2c.demand_miss_latency::cpu0.dtb.walker 5396500 # number of demand (read+write) miss cycles |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 524 | system.l2c.demand_miss_latency::cpu0.itb.walker 74500 # number of demand (read+write) miss cycles |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 525 | system.l2c.demand_miss_latency::cpu0.inst 829990750 # number of demand (read+write) miss cycles |
| 526 | system.l2c.demand_miss_latency::cpu0.data 6314985551 # number of demand (read+write) miss cycles |
| 527 | system.l2c.demand_miss_latency::cpu1.dtb.walker 5378000 # number of demand (read+write) miss cycles |
| 528 | system.l2c.demand_miss_latency::cpu1.inst 749581500 # number of demand (read+write) miss cycles |
| 529 | system.l2c.demand_miss_latency::cpu1.data 5762494795 # number of demand (read+write) miss cycles |
| 530 | system.l2c.demand_miss_latency::total 13667901596 # number of demand (read+write) miss cycles |
| 531 | system.l2c.overall_miss_latency::cpu0.dtb.walker 5396500 # number of overall miss cycles |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 532 | system.l2c.overall_miss_latency::cpu0.itb.walker 74500 # number of overall miss cycles |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 533 | system.l2c.overall_miss_latency::cpu0.inst 829990750 # number of overall miss cycles |
| 534 | system.l2c.overall_miss_latency::cpu0.data 6314985551 # number of overall miss cycles |
| 535 | system.l2c.overall_miss_latency::cpu1.dtb.walker 5378000 # number of overall miss cycles |
| 536 | system.l2c.overall_miss_latency::cpu1.inst 749581500 # number of overall miss cycles |
| 537 | system.l2c.overall_miss_latency::cpu1.data 5762494795 # number of overall miss cycles |
| 538 | system.l2c.overall_miss_latency::total 13667901596 # number of overall miss cycles |
| 539 | system.l2c.ReadReq_accesses::cpu0.dtb.walker 36587 # number of ReadReq accesses(hits+misses) |
| 540 | system.l2c.ReadReq_accesses::cpu0.itb.walker 8856 # number of ReadReq accesses(hits+misses) |
| 541 | system.l2c.ReadReq_accesses::cpu0.inst 970836 # number of ReadReq accesses(hits+misses) |
| 542 | system.l2c.ReadReq_accesses::cpu0.data 278766 # number of ReadReq accesses(hits+misses) |
| 543 | system.l2c.ReadReq_accesses::cpu1.dtb.walker 36671 # number of ReadReq accesses(hits+misses) |
| 544 | system.l2c.ReadReq_accesses::cpu1.itb.walker 7424 # number of ReadReq accesses(hits+misses) |
| 545 | system.l2c.ReadReq_accesses::cpu1.inst 974023 # number of ReadReq accesses(hits+misses) |
| 546 | system.l2c.ReadReq_accesses::cpu1.data 277422 # number of ReadReq accesses(hits+misses) |
| 547 | system.l2c.ReadReq_accesses::total 2590585 # number of ReadReq accesses(hits+misses) |
| 548 | system.l2c.Writeback_accesses::writebacks 703423 # number of Writeback accesses(hits+misses) |
| 549 | system.l2c.Writeback_accesses::total 703423 # number of Writeback accesses(hits+misses) |
| 550 | system.l2c.UpgradeReq_accesses::cpu0.data 1336 # number of UpgradeReq accesses(hits+misses) |
| 551 | system.l2c.UpgradeReq_accesses::cpu1.data 1502 # number of UpgradeReq accesses(hits+misses) |
| 552 | system.l2c.UpgradeReq_accesses::total 2838 # number of UpgradeReq accesses(hits+misses) |
| 553 | system.l2c.SCUpgradeReq_accesses::cpu0.data 29 # number of SCUpgradeReq accesses(hits+misses) |
| 554 | system.l2c.SCUpgradeReq_accesses::cpu1.data 50 # number of SCUpgradeReq accesses(hits+misses) |
| 555 | system.l2c.SCUpgradeReq_accesses::total 79 # number of SCUpgradeReq accesses(hits+misses) |
| 556 | system.l2c.ReadExReq_accesses::cpu0.data 152558 # number of ReadExReq accesses(hits+misses) |
| 557 | system.l2c.ReadExReq_accesses::cpu1.data 144319 # number of ReadExReq accesses(hits+misses) |
| 558 | system.l2c.ReadExReq_accesses::total 296877 # number of ReadExReq accesses(hits+misses) |
| 559 | system.l2c.demand_accesses::cpu0.dtb.walker 36587 # number of demand (read+write) accesses |
| 560 | system.l2c.demand_accesses::cpu0.itb.walker 8856 # number of demand (read+write) accesses |
| 561 | system.l2c.demand_accesses::cpu0.inst 970836 # number of demand (read+write) accesses |
| 562 | system.l2c.demand_accesses::cpu0.data 431324 # number of demand (read+write) accesses |
| 563 | system.l2c.demand_accesses::cpu1.dtb.walker 36671 # number of demand (read+write) accesses |
| 564 | system.l2c.demand_accesses::cpu1.itb.walker 7424 # number of demand (read+write) accesses |
| 565 | system.l2c.demand_accesses::cpu1.inst 974023 # number of demand (read+write) accesses |
| 566 | system.l2c.demand_accesses::cpu1.data 421741 # number of demand (read+write) accesses |
| 567 | system.l2c.demand_accesses::total 2887462 # number of demand (read+write) accesses |
| 568 | system.l2c.overall_accesses::cpu0.dtb.walker 36587 # number of overall (read+write) accesses |
| 569 | system.l2c.overall_accesses::cpu0.itb.walker 8856 # number of overall (read+write) accesses |
| 570 | system.l2c.overall_accesses::cpu0.inst 970836 # number of overall (read+write) accesses |
| 571 | system.l2c.overall_accesses::cpu0.data 431324 # number of overall (read+write) accesses |
| 572 | system.l2c.overall_accesses::cpu1.dtb.walker 36671 # number of overall (read+write) accesses |
| 573 | system.l2c.overall_accesses::cpu1.itb.walker 7424 # number of overall (read+write) accesses |
| 574 | system.l2c.overall_accesses::cpu1.inst 974023 # number of overall (read+write) accesses |
| 575 | system.l2c.overall_accesses::cpu1.data 421741 # number of overall (read+write) accesses |
| 576 | system.l2c.overall_accesses::total 2887462 # number of overall (read+write) accesses |
| 577 | system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001859 # miss rate for ReadReq accesses |
| 578 | system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000113 # miss rate for ReadReq accesses |
| 579 | system.l2c.ReadReq_miss_rate::cpu0.inst 0.011256 # miss rate for ReadReq accesses |
| 580 | system.l2c.ReadReq_miss_rate::cpu0.data 0.025652 # miss rate for ReadReq accesses |
| 581 | system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001882 # miss rate for ReadReq accesses |
| 582 | system.l2c.ReadReq_miss_rate::cpu1.inst 0.010220 # miss rate for ReadReq accesses |
| 583 | system.l2c.ReadReq_miss_rate::cpu1.data 0.028732 # miss rate for ReadReq accesses |
| 584 | system.l2c.ReadReq_miss_rate::total 0.013952 # miss rate for ReadReq accesses |
| 585 | system.l2c.UpgradeReq_miss_rate::cpu0.data 0.972305 # miss rate for UpgradeReq accesses |
| 586 | system.l2c.UpgradeReq_miss_rate::cpu1.data 0.960719 # miss rate for UpgradeReq accesses |
| 587 | system.l2c.UpgradeReq_miss_rate::total 0.966173 # miss rate for UpgradeReq accesses |
| 588 | system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.275862 # miss rate for SCUpgradeReq accesses |
| 589 | system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.360000 # miss rate for SCUpgradeReq accesses |
| 590 | system.l2c.SCUpgradeReq_miss_rate::total 0.329114 # miss rate for SCUpgradeReq accesses |
| 591 | system.l2c.ReadExReq_miss_rate::cpu0.data 0.490043 # miss rate for ReadExReq accesses |
| 592 | system.l2c.ReadExReq_miss_rate::cpu1.data 0.454348 # miss rate for ReadExReq accesses |
| 593 | system.l2c.ReadExReq_miss_rate::total 0.472691 # miss rate for ReadExReq accesses |
| 594 | system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001859 # miss rate for demand accesses |
| 595 | system.l2c.demand_miss_rate::cpu0.itb.walker 0.000113 # miss rate for demand accesses |
| 596 | system.l2c.demand_miss_rate::cpu0.inst 0.011256 # miss rate for demand accesses |
| 597 | system.l2c.demand_miss_rate::cpu0.data 0.189906 # miss rate for demand accesses |
| 598 | system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001882 # miss rate for demand accesses |
| 599 | system.l2c.demand_miss_rate::cpu1.inst 0.010220 # miss rate for demand accesses |
| 600 | system.l2c.demand_miss_rate::cpu1.data 0.174377 # miss rate for demand accesses |
| 601 | system.l2c.demand_miss_rate::total 0.061117 # miss rate for demand accesses |
| 602 | system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001859 # miss rate for overall accesses |
| 603 | system.l2c.overall_miss_rate::cpu0.itb.walker 0.000113 # miss rate for overall accesses |
| 604 | system.l2c.overall_miss_rate::cpu0.inst 0.011256 # miss rate for overall accesses |
| 605 | system.l2c.overall_miss_rate::cpu0.data 0.189906 # miss rate for overall accesses |
| 606 | system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001882 # miss rate for overall accesses |
| 607 | system.l2c.overall_miss_rate::cpu1.inst 0.010220 # miss rate for overall accesses |
| 608 | system.l2c.overall_miss_rate::cpu1.data 0.174377 # miss rate for overall accesses |
| 609 | system.l2c.overall_miss_rate::total 0.061117 # miss rate for overall accesses |
| 610 | system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79360.294118 # average ReadReq miss latency |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 611 | system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74500 # average ReadReq miss latency |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 612 | system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75950.837299 # average ReadReq miss latency |
| 613 | system.l2c.ReadReq_avg_miss_latency::cpu0.data 80230.700881 # average ReadReq miss latency |
| 614 | system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 77942.028986 # average ReadReq miss latency |
| 615 | system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75296.986439 # average ReadReq miss latency |
| 616 | system.l2c.ReadReq_avg_miss_latency::cpu1.data 81970.956342 # average ReadReq miss latency |
| 617 | system.l2c.ReadReq_avg_miss_latency::total 77955.385137 # average ReadReq miss latency |
| 618 | system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 234.401078 # average UpgradeReq miss latency |
| 619 | system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 322.924463 # average UpgradeReq miss latency |
| 620 | system.l2c.UpgradeReq_avg_miss_latency::total 280.987236 # average UpgradeReq miss latency |
| 621 | system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14624.375000 # average SCUpgradeReq miss latency |
| 622 | system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9055.166667 # average SCUpgradeReq miss latency |
| 623 | system.l2c.SCUpgradeReq_avg_miss_latency::total 10768.769231 # average SCUpgradeReq miss latency |
| 624 | system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76795.824090 # average ReadExReq miss latency |
| 625 | system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77917.132604 # average ReadExReq miss latency |
| 626 | system.l2c.ReadExReq_avg_miss_latency::total 77319.766203 # average ReadExReq miss latency |
| 627 | system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79360.294118 # average overall miss latency |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 628 | system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74500 # average overall miss latency |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 629 | system.l2c.demand_avg_miss_latency::cpu0.inst 75950.837299 # average overall miss latency |
| 630 | system.l2c.demand_avg_miss_latency::cpu0.data 77095.695950 # average overall miss latency |
| 631 | system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 77942.028986 # average overall miss latency |
| 632 | system.l2c.demand_avg_miss_latency::cpu1.inst 75296.986439 # average overall miss latency |
| 633 | system.l2c.demand_avg_miss_latency::cpu1.data 78356.514577 # average overall miss latency |
| 634 | system.l2c.demand_avg_miss_latency::total 77449.945012 # average overall miss latency |
| 635 | system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79360.294118 # average overall miss latency |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 636 | system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74500 # average overall miss latency |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 637 | system.l2c.overall_avg_miss_latency::cpu0.inst 75950.837299 # average overall miss latency |
| 638 | system.l2c.overall_avg_miss_latency::cpu0.data 77095.695950 # average overall miss latency |
| 639 | system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 77942.028986 # average overall miss latency |
| 640 | system.l2c.overall_avg_miss_latency::cpu1.inst 75296.986439 # average overall miss latency |
| 641 | system.l2c.overall_avg_miss_latency::cpu1.data 78356.514577 # average overall miss latency |
| 642 | system.l2c.overall_avg_miss_latency::total 77449.945012 # average overall miss latency |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 643 | system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 644 | system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 645 | system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked |
| 646 | system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 647 | system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 648 | system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 649 | system.l2c.fast_writes 0 # number of fast writes performed |
| 650 | system.l2c.cache_copies 0 # number of cache copies performed |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 651 | system.l2c.writebacks::writebacks 95531 # number of writebacks |
| 652 | system.l2c.writebacks::total 95531 # number of writebacks |
| 653 | system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits |
| 654 | system.l2c.ReadReq_mshr_hits::cpu0.data 73 # number of ReadReq MSHR hits |
| 655 | system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 656 | system.l2c.ReadReq_mshr_hits::cpu1.data 66 # number of ReadReq MSHR hits |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 657 | system.l2c.ReadReq_mshr_hits::total 150 # number of ReadReq MSHR hits |
| 658 | system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits |
| 659 | system.l2c.demand_mshr_hits::cpu0.data 73 # number of demand (read+write) MSHR hits |
| 660 | system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 661 | system.l2c.demand_mshr_hits::cpu1.data 66 # number of demand (read+write) MSHR hits |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 662 | system.l2c.demand_mshr_hits::total 150 # number of demand (read+write) MSHR hits |
| 663 | system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits |
| 664 | system.l2c.overall_mshr_hits::cpu0.data 73 # number of overall MSHR hits |
| 665 | system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 666 | system.l2c.overall_mshr_hits::cpu1.data 66 # number of overall MSHR hits |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 667 | system.l2c.overall_mshr_hits::total 150 # number of overall MSHR hits |
| 668 | system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 68 # number of ReadReq MSHR misses |
Steve Reinhardt | 5b08e21 | 2014-06-22 14:33:09 -0700 | [diff] [blame] | 669 | system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 670 | system.l2c.ReadReq_mshr_misses::cpu0.inst 10921 # number of ReadReq MSHR misses |
| 671 | system.l2c.ReadReq_mshr_misses::cpu0.data 7078 # number of ReadReq MSHR misses |
| 672 | system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 69 # number of ReadReq MSHR misses |
| 673 | system.l2c.ReadReq_mshr_misses::cpu1.inst 9951 # number of ReadReq MSHR misses |
| 674 | system.l2c.ReadReq_mshr_misses::cpu1.data 7905 # number of ReadReq MSHR misses |
| 675 | system.l2c.ReadReq_mshr_misses::total 35993 # number of ReadReq MSHR misses |
| 676 | system.l2c.UpgradeReq_mshr_misses::cpu0.data 1299 # number of UpgradeReq MSHR misses |
| 677 | system.l2c.UpgradeReq_mshr_misses::cpu1.data 1443 # number of UpgradeReq MSHR misses |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 678 | system.l2c.UpgradeReq_mshr_misses::total 2742 # number of UpgradeReq MSHR misses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 679 | system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 8 # number of SCUpgradeReq MSHR misses |
| 680 | system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 18 # number of SCUpgradeReq MSHR misses |
| 681 | system.l2c.SCUpgradeReq_mshr_misses::total 26 # number of SCUpgradeReq MSHR misses |
| 682 | system.l2c.ReadExReq_mshr_misses::cpu0.data 74760 # number of ReadExReq MSHR misses |
| 683 | system.l2c.ReadExReq_mshr_misses::cpu1.data 65571 # number of ReadExReq MSHR misses |
| 684 | system.l2c.ReadExReq_mshr_misses::total 140331 # number of ReadExReq MSHR misses |
| 685 | system.l2c.demand_mshr_misses::cpu0.dtb.walker 68 # number of demand (read+write) MSHR misses |
Steve Reinhardt | 5b08e21 | 2014-06-22 14:33:09 -0700 | [diff] [blame] | 686 | system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 687 | system.l2c.demand_mshr_misses::cpu0.inst 10921 # number of demand (read+write) MSHR misses |
| 688 | system.l2c.demand_mshr_misses::cpu0.data 81838 # number of demand (read+write) MSHR misses |
| 689 | system.l2c.demand_mshr_misses::cpu1.dtb.walker 69 # number of demand (read+write) MSHR misses |
| 690 | system.l2c.demand_mshr_misses::cpu1.inst 9951 # number of demand (read+write) MSHR misses |
| 691 | system.l2c.demand_mshr_misses::cpu1.data 73476 # number of demand (read+write) MSHR misses |
| 692 | system.l2c.demand_mshr_misses::total 176324 # number of demand (read+write) MSHR misses |
| 693 | system.l2c.overall_mshr_misses::cpu0.dtb.walker 68 # number of overall MSHR misses |
Steve Reinhardt | 5b08e21 | 2014-06-22 14:33:09 -0700 | [diff] [blame] | 694 | system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 695 | system.l2c.overall_mshr_misses::cpu0.inst 10921 # number of overall MSHR misses |
| 696 | system.l2c.overall_mshr_misses::cpu0.data 81838 # number of overall MSHR misses |
| 697 | system.l2c.overall_mshr_misses::cpu1.dtb.walker 69 # number of overall MSHR misses |
| 698 | system.l2c.overall_mshr_misses::cpu1.inst 9951 # number of overall MSHR misses |
| 699 | system.l2c.overall_mshr_misses::cpu1.data 73476 # number of overall MSHR misses |
| 700 | system.l2c.overall_mshr_misses::total 176324 # number of overall MSHR misses |
| 701 | system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4553000 # number of ReadReq MSHR miss cycles |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 702 | system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 703 | system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 692294000 # number of ReadReq MSHR miss cycles |
| 704 | system.l2c.ReadReq_mshr_miss_latency::cpu0.data 481153492 # number of ReadReq MSHR miss cycles |
| 705 | system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4523000 # number of ReadReq MSHR miss cycles |
| 706 | system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 624075250 # number of ReadReq MSHR miss cycles |
| 707 | system.l2c.ReadReq_mshr_miss_latency::cpu1.data 550752493 # number of ReadReq MSHR miss cycles |
| 708 | system.l2c.ReadReq_mshr_miss_latency::total 2357413735 # number of ReadReq MSHR miss cycles |
| 709 | system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 12992798 # number of UpgradeReq MSHR miss cycles |
| 710 | system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14497943 # number of UpgradeReq MSHR miss cycles |
| 711 | system.l2c.UpgradeReq_mshr_miss_latency::total 27490741 # number of UpgradeReq MSHR miss cycles |
| 712 | system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 80008 # number of SCUpgradeReq MSHR miss cycles |
| 713 | system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 180018 # number of SCUpgradeReq MSHR miss cycles |
| 714 | system.l2c.SCUpgradeReq_mshr_miss_latency::total 260026 # number of SCUpgradeReq MSHR miss cycles |
| 715 | system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4808098691 # number of ReadExReq MSHR miss cycles |
| 716 | system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4293415698 # number of ReadExReq MSHR miss cycles |
| 717 | system.l2c.ReadExReq_mshr_miss_latency::total 9101514389 # number of ReadExReq MSHR miss cycles |
| 718 | system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 4553000 # number of demand (read+write) MSHR miss cycles |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 719 | system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 720 | system.l2c.demand_mshr_miss_latency::cpu0.inst 692294000 # number of demand (read+write) MSHR miss cycles |
| 721 | system.l2c.demand_mshr_miss_latency::cpu0.data 5289252183 # number of demand (read+write) MSHR miss cycles |
| 722 | system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 4523000 # number of demand (read+write) MSHR miss cycles |
| 723 | system.l2c.demand_mshr_miss_latency::cpu1.inst 624075250 # number of demand (read+write) MSHR miss cycles |
| 724 | system.l2c.demand_mshr_miss_latency::cpu1.data 4844168191 # number of demand (read+write) MSHR miss cycles |
| 725 | system.l2c.demand_mshr_miss_latency::total 11458928124 # number of demand (read+write) MSHR miss cycles |
| 726 | system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 4553000 # number of overall MSHR miss cycles |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 727 | system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 728 | system.l2c.overall_mshr_miss_latency::cpu0.inst 692294000 # number of overall MSHR miss cycles |
| 729 | system.l2c.overall_mshr_miss_latency::cpu0.data 5289252183 # number of overall MSHR miss cycles |
| 730 | system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 4523000 # number of overall MSHR miss cycles |
| 731 | system.l2c.overall_mshr_miss_latency::cpu1.inst 624075250 # number of overall MSHR miss cycles |
| 732 | system.l2c.overall_mshr_miss_latency::cpu1.data 4844168191 # number of overall MSHR miss cycles |
| 733 | system.l2c.overall_mshr_miss_latency::total 11458928124 # number of overall MSHR miss cycles |
| 734 | system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 35706500 # number of ReadReq MSHR uncacheable cycles |
| 735 | system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2951899000 # number of ReadReq MSHR uncacheable cycles |
| 736 | system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2427344000 # number of ReadReq MSHR uncacheable cycles |
| 737 | system.l2c.ReadReq_mshr_uncacheable_latency::total 5414949500 # number of ReadReq MSHR uncacheable cycles |
| 738 | system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2228650000 # number of WriteReq MSHR uncacheable cycles |
| 739 | system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1873529499 # number of WriteReq MSHR uncacheable cycles |
| 740 | system.l2c.WriteReq_mshr_uncacheable_latency::total 4102179499 # number of WriteReq MSHR uncacheable cycles |
| 741 | system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 35706500 # number of overall MSHR uncacheable cycles |
| 742 | system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5180549000 # number of overall MSHR uncacheable cycles |
| 743 | system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4300873499 # number of overall MSHR uncacheable cycles |
| 744 | system.l2c.overall_mshr_uncacheable_latency::total 9517128999 # number of overall MSHR uncacheable cycles |
| 745 | system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001859 # mshr miss rate for ReadReq accesses |
| 746 | system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000113 # mshr miss rate for ReadReq accesses |
| 747 | system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.011249 # mshr miss rate for ReadReq accesses |
| 748 | system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.025390 # mshr miss rate for ReadReq accesses |
| 749 | system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001882 # mshr miss rate for ReadReq accesses |
| 750 | system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010216 # mshr miss rate for ReadReq accesses |
| 751 | system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.028494 # mshr miss rate for ReadReq accesses |
| 752 | system.l2c.ReadReq_mshr_miss_rate::total 0.013894 # mshr miss rate for ReadReq accesses |
| 753 | system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.972305 # mshr miss rate for UpgradeReq accesses |
| 754 | system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.960719 # mshr miss rate for UpgradeReq accesses |
| 755 | system.l2c.UpgradeReq_mshr_miss_rate::total 0.966173 # mshr miss rate for UpgradeReq accesses |
| 756 | system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.275862 # mshr miss rate for SCUpgradeReq accesses |
| 757 | system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.360000 # mshr miss rate for SCUpgradeReq accesses |
| 758 | system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.329114 # mshr miss rate for SCUpgradeReq accesses |
| 759 | system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.490043 # mshr miss rate for ReadExReq accesses |
| 760 | system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.454348 # mshr miss rate for ReadExReq accesses |
| 761 | system.l2c.ReadExReq_mshr_miss_rate::total 0.472691 # mshr miss rate for ReadExReq accesses |
| 762 | system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001859 # mshr miss rate for demand accesses |
| 763 | system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000113 # mshr miss rate for demand accesses |
| 764 | system.l2c.demand_mshr_miss_rate::cpu0.inst 0.011249 # mshr miss rate for demand accesses |
| 765 | system.l2c.demand_mshr_miss_rate::cpu0.data 0.189737 # mshr miss rate for demand accesses |
| 766 | system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001882 # mshr miss rate for demand accesses |
| 767 | system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010216 # mshr miss rate for demand accesses |
| 768 | system.l2c.demand_mshr_miss_rate::cpu1.data 0.174221 # mshr miss rate for demand accesses |
| 769 | system.l2c.demand_mshr_miss_rate::total 0.061065 # mshr miss rate for demand accesses |
| 770 | system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001859 # mshr miss rate for overall accesses |
| 771 | system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000113 # mshr miss rate for overall accesses |
| 772 | system.l2c.overall_mshr_miss_rate::cpu0.inst 0.011249 # mshr miss rate for overall accesses |
| 773 | system.l2c.overall_mshr_miss_rate::cpu0.data 0.189737 # mshr miss rate for overall accesses |
| 774 | system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001882 # mshr miss rate for overall accesses |
| 775 | system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010216 # mshr miss rate for overall accesses |
| 776 | system.l2c.overall_mshr_miss_rate::cpu1.data 0.174221 # mshr miss rate for overall accesses |
| 777 | system.l2c.overall_mshr_miss_rate::total 0.061065 # mshr miss rate for overall accesses |
| 778 | system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66955.882353 # average ReadReq mshr miss latency |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 779 | system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 780 | system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63391.081403 # average ReadReq mshr miss latency |
| 781 | system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67978.735801 # average ReadReq mshr miss latency |
| 782 | system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average ReadReq mshr miss latency |
| 783 | system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62714.827656 # average ReadReq mshr miss latency |
| 784 | system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 69671.409614 # average ReadReq mshr miss latency |
| 785 | system.l2c.ReadReq_avg_mshr_miss_latency::total 65496.450282 # average ReadReq mshr miss latency |
| 786 | system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.153965 # average UpgradeReq mshr miss latency |
| 787 | system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10047.084546 # average UpgradeReq mshr miss latency |
| 788 | system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.799052 # average UpgradeReq mshr miss latency |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 789 | system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency |
| 790 | system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency |
| 791 | system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 792 | system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64313.786664 # average ReadExReq mshr miss latency |
| 793 | system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65477.355813 # average ReadExReq mshr miss latency |
| 794 | system.l2c.ReadExReq_avg_mshr_miss_latency::total 64857.475462 # average ReadExReq mshr miss latency |
| 795 | system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66955.882353 # average overall mshr miss latency |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 796 | system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 797 | system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63391.081403 # average overall mshr miss latency |
| 798 | system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64630.760564 # average overall mshr miss latency |
| 799 | system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average overall mshr miss latency |
| 800 | system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62714.827656 # average overall mshr miss latency |
| 801 | system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65928.577917 # average overall mshr miss latency |
| 802 | system.l2c.demand_avg_mshr_miss_latency::total 64987.909326 # average overall mshr miss latency |
| 803 | system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66955.882353 # average overall mshr miss latency |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 804 | system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 805 | system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63391.081403 # average overall mshr miss latency |
| 806 | system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64630.760564 # average overall mshr miss latency |
| 807 | system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average overall mshr miss latency |
| 808 | system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62714.827656 # average overall mshr miss latency |
| 809 | system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65928.577917 # average overall mshr miss latency |
| 810 | system.l2c.overall_avg_mshr_miss_latency::total 64987.909326 # average overall mshr miss latency |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 811 | system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency |
| 812 | system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency |
| 813 | system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency |
| 814 | system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
| 815 | system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency |
| 816 | system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency |
| 817 | system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 818 | system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency |
| 819 | system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency |
| 820 | system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency |
| 821 | system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
| 822 | system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 823 | system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA |
| 824 | system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |
| 825 | system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA |
| 826 | system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA |
| 827 | system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU |
| 828 | system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post |
| 829 | system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR |
| 830 | system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU |
| 831 | system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post |
| 832 | system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR |
| 833 | system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU |
| 834 | system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post |
| 835 | system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR |
| 836 | system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU |
| 837 | system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post |
| 838 | system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR |
| 839 | system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU |
| 840 | system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post |
| 841 | system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR |
| 842 | system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU |
| 843 | system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post |
| 844 | system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR |
| 845 | system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU |
| 846 | system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post |
| 847 | system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR |
| 848 | system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU |
| 849 | system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post |
| 850 | system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR |
| 851 | system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post |
| 852 | system.realview.ethernet.postedInterrupts 0 # number of posts to CPU |
| 853 | system.realview.ethernet.droppedPackets 0 # number of packets dropped |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 854 | system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 855 | system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). |
| 856 | system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). |
| 857 | system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. |
| 858 | system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. |
| 859 | system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 860 | system.toL2Bus.trans_dist::ReadReq 2655325 # Transaction distribution |
| 861 | system.toL2Bus.trans_dist::ReadResp 2655239 # Transaction distribution |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 862 | system.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution |
| 863 | system.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 864 | system.toL2Bus.trans_dist::Writeback 703423 # Transaction distribution |
| 865 | system.toL2Bus.trans_dist::WriteInvalidateReq 36238 # Transaction distribution |
| 866 | system.toL2Bus.trans_dist::UpgradeReq 2838 # Transaction distribution |
| 867 | system.toL2Bus.trans_dist::SCUpgradeReq 79 # Transaction distribution |
| 868 | system.toL2Bus.trans_dist::UpgradeResp 2917 # Transaction distribution |
| 869 | system.toL2Bus.trans_dist::ReadExReq 296877 # Transaction distribution |
| 870 | system.toL2Bus.trans_dist::ReadExResp 296877 # Transaction distribution |
| 871 | system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3891298 # Packet count per connected master and slave (bytes) |
| 872 | system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2533043 # Packet count per connected master and slave (bytes) |
| 873 | system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42437 # Packet count per connected master and slave (bytes) |
| 874 | system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169072 # Packet count per connected master and slave (bytes) |
| 875 | system.toL2Bus.pkt_count::total 6635850 # Packet count per connected master and slave (bytes) |
| 876 | system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124513216 # Cumulative packet size per connected master and slave (bytes) |
| 877 | system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99808865 # Cumulative packet size per connected master and slave (bytes) |
| 878 | system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 65120 # Cumulative packet size per connected master and slave (bytes) |
| 879 | system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 293032 # Cumulative packet size per connected master and slave (bytes) |
| 880 | system.toL2Bus.pkt_size::total 224680233 # Cumulative packet size per connected master and slave (bytes) |
| 881 | system.toL2Bus.snoops 69343 # Total snoops (count) |
| 882 | system.toL2Bus.snoop_fanout::samples 3662983 # Request fanout histogram |
| 883 | system.toL2Bus.snoop_fanout::mean 5.009961 # Request fanout histogram |
| 884 | system.toL2Bus.snoop_fanout::stdev 0.099307 # Request fanout histogram |
Andreas Hansson | c4e9128 | 2014-09-20 17:18:53 -0400 | [diff] [blame] | 885 | system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 886 | system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 887 | system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram |
| 888 | system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 889 | system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram |
| 890 | system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 891 | system.toL2Bus.snoop_fanout::5 3626496 99.00% 99.00% # Request fanout histogram |
| 892 | system.toL2Bus.snoop_fanout::6 36487 1.00% 100.00% # Request fanout histogram |
Andreas Hansson | c4e9128 | 2014-09-20 17:18:53 -0400 | [diff] [blame] | 893 | system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 894 | system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 895 | system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 896 | system.toL2Bus.snoop_fanout::total 3662983 # Request fanout histogram |
| 897 | system.toL2Bus.reqLayer0.occupancy 4670881246 # Layer occupancy (ticks) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 898 | system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 899 | system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks) |
| 900 | system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 901 | system.toL2Bus.respLayer0.occupancy 8762800197 # Layer occupancy (ticks) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 902 | system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 903 | system.toL2Bus.respLayer1.occupancy 3909656420 # Layer occupancy (ticks) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 904 | system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 905 | system.toL2Bus.respLayer2.occupancy 26229350 # Layer occupancy (ticks) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 906 | system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 907 | system.toL2Bus.respLayer3.occupancy 96621860 # Layer occupancy (ticks) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 908 | system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 909 | system.iobus.trans_dist::ReadReq 30210 # Transaction distribution |
| 910 | system.iobus.trans_dist::ReadResp 30210 # Transaction distribution |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 911 | system.iobus.trans_dist::WriteReq 59030 # Transaction distribution |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 912 | system.iobus.trans_dist::WriteResp 59038 # Transaction distribution |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 913 | system.iobus.trans_dist::WriteInvalidateReq 8 # Transaction distribution |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 914 | system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) |
| 915 | system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) |
| 916 | system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) |
| 917 | system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 918 | system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 919 | system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) |
| 920 | system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 921 | system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 922 | system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 923 | system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 924 | system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 925 | system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 926 | system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 927 | system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) |
| 928 | system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 929 | system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 930 | system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) |
| 931 | system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) |
| 932 | system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) |
| 933 | system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) |
| 934 | system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 935 | system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) |
| 936 | system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) |
| 937 | system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) |
| 938 | system.iobus.pkt_count::total 178496 # Packet count per connected master and slave (bytes) |
| 939 | system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) |
| 940 | system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) |
| 941 | system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) |
| 942 | system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) |
Andreas Hansson | c4e9128 | 2014-09-20 17:18:53 -0400 | [diff] [blame] | 943 | system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 944 | system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) |
| 945 | system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) |
Andreas Hansson | c4e9128 | 2014-09-20 17:18:53 -0400 | [diff] [blame] | 946 | system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 947 | system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 948 | system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 949 | system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) |
Andreas Hansson | c4e9128 | 2014-09-20 17:18:53 -0400 | [diff] [blame] | 950 | system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
Andreas Hansson | c4e9128 | 2014-09-20 17:18:53 -0400 | [diff] [blame] | 951 | system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 952 | system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) |
| 953 | system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) |
Andreas Hansson | c4e9128 | 2014-09-20 17:18:53 -0400 | [diff] [blame] | 954 | system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 955 | system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) |
| 956 | system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) |
| 957 | system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) |
| 958 | system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) |
| 959 | system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 960 | system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) |
| 961 | system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) |
| 962 | system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) |
| 963 | system.iobus.pkt_size::total 2480421 # Cumulative packet size per connected master and slave (bytes) |
| 964 | system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 965 | system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 966 | system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 967 | system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 968 | system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 969 | system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 970 | system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 971 | system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 972 | system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 973 | system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 974 | system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 975 | system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 976 | system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 977 | system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 978 | system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) |
| 979 | system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 980 | system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 981 | system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) |
| 982 | system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) |
| 983 | system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 984 | system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 985 | system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) |
| 986 | system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) |
| 987 | system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
| 988 | system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) |
| 989 | system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 990 | system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 991 | system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) |
| 992 | system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) |
| 993 | system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) |
| 994 | system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) |
| 995 | system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 996 | system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) |
Andreas Hansson | 74553c7 | 2013-05-30 12:54:18 -0400 | [diff] [blame] | 997 | system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 998 | system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) |
| 999 | system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 1000 | system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) |
| 1001 | system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) |
| 1002 | system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) |
| 1003 | system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1004 | system.iobus.reqLayer27.occupancy 326627644 # Layer occupancy (ticks) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1005 | system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) |
| 1006 | system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) |
| 1007 | system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 1008 | system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) |
| 1009 | system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1010 | system.iobus.respLayer3.occupancy 36841042 # Layer occupancy (ticks) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1011 | system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1012 | system.cpu0.branchPred.lookups 27349422 # Number of BP lookups |
| 1013 | system.cpu0.branchPred.condPredicted 14250256 # Number of conditional branches predicted |
| 1014 | system.cpu0.branchPred.condIncorrect 549515 # Number of conditional branches incorrect |
| 1015 | system.cpu0.branchPred.BTBLookups 17066610 # Number of BTB lookups |
| 1016 | system.cpu0.branchPred.BTBHits 12886962 # Number of BTB hits |
Nilay Vaish | 9bc132e | 2013-01-24 12:29:00 -0600 | [diff] [blame] | 1017 | system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1018 | system.cpu0.branchPred.BTBHitPct 75.509794 # BTB Hit Percentage |
| 1019 | system.cpu0.branchPred.usedRAS 6758521 # Number of times the RAS was used to get a target. |
| 1020 | system.cpu0.branchPred.RASInCorrect 30298 # Number of incorrect RAS predictions. |
Ali Saidi | cfb805c | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 1021 | system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits |
| 1022 | system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses |
| 1023 | system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits |
| 1024 | system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses |
| 1025 | system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits |
| 1026 | system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses |
| 1027 | system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed |
| 1028 | system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 1029 | system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| 1030 | system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1031 | system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB |
| 1032 | system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1033 | system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| 1034 | system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1035 | system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| 1036 | system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses |
| 1037 | system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses |
| 1038 | system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses |
| 1039 | system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits |
| 1040 | system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses |
| 1041 | system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1042 | system.cpu0.dtb.inst_hits 0 # ITB inst hits |
| 1043 | system.cpu0.dtb.inst_misses 0 # ITB inst misses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1044 | system.cpu0.dtb.read_hits 14278108 # DTB read hits |
| 1045 | system.cpu0.dtb.read_misses 49273 # DTB read misses |
| 1046 | system.cpu0.dtb.write_hits 10337716 # DTB write hits |
| 1047 | system.cpu0.dtb.write_misses 7471 # DTB write misses |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1048 | system.cpu0.dtb.flush_tlb 178 # Number of times complete TLB was flushed |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1049 | system.cpu0.dtb.flush_tlb_mva 473 # Number of times TLB was flushed by MVA |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1050 | system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| 1051 | system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1052 | system.cpu0.dtb.flush_entries 3414 # Number of entries that have been flushed from TLB |
| 1053 | system.cpu0.dtb.align_faults 948 # Number of TLB faults due to alignment restrictions |
| 1054 | system.cpu0.dtb.prefetch_faults 1297 # Number of TLB faults due to prefetch |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1055 | system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1056 | system.cpu0.dtb.perms_faults 559 # Number of TLB faults due to permissions restrictions |
| 1057 | system.cpu0.dtb.read_accesses 14327381 # DTB read accesses |
| 1058 | system.cpu0.dtb.write_accesses 10345187 # DTB write accesses |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1059 | system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1060 | system.cpu0.dtb.hits 24615824 # DTB hits |
| 1061 | system.cpu0.dtb.misses 56744 # DTB misses |
| 1062 | system.cpu0.dtb.accesses 24672568 # DTB accesses |
Ali Saidi | cfb805c | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 1063 | system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits |
| 1064 | system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses |
| 1065 | system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits |
| 1066 | system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses |
| 1067 | system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits |
| 1068 | system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses |
| 1069 | system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed |
| 1070 | system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 1071 | system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| 1072 | system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1073 | system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB |
| 1074 | system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1075 | system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| 1076 | system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1077 | system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| 1078 | system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses |
| 1079 | system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses |
| 1080 | system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses |
| 1081 | system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits |
| 1082 | system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses |
| 1083 | system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1084 | system.cpu0.itb.inst_hits 20514368 # ITB inst hits |
| 1085 | system.cpu0.itb.inst_misses 8789 # ITB inst misses |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1086 | system.cpu0.itb.read_hits 0 # DTB read hits |
| 1087 | system.cpu0.itb.read_misses 0 # DTB read misses |
| 1088 | system.cpu0.itb.write_hits 0 # DTB write hits |
| 1089 | system.cpu0.itb.write_misses 0 # DTB write misses |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1090 | system.cpu0.itb.flush_tlb 178 # Number of times complete TLB was flushed |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1091 | system.cpu0.itb.flush_tlb_mva 473 # Number of times TLB was flushed by MVA |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1092 | system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| 1093 | system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1094 | system.cpu0.itb.flush_entries 2304 # Number of entries that have been flushed from TLB |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1095 | system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1096 | system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| 1097 | system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1098 | system.cpu0.itb.perms_faults 1449 # Number of TLB faults due to permissions restrictions |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1099 | system.cpu0.itb.read_accesses 0 # DTB read accesses |
| 1100 | system.cpu0.itb.write_accesses 0 # DTB write accesses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1101 | system.cpu0.itb.inst_accesses 20523157 # ITB inst accesses |
| 1102 | system.cpu0.itb.hits 20514368 # DTB hits |
| 1103 | system.cpu0.itb.misses 8789 # DTB misses |
| 1104 | system.cpu0.itb.accesses 20523157 # DTB accesses |
| 1105 | system.cpu0.numCycles 107867607 # number of cpu cycles simulated |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1106 | system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started |
| 1107 | system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1108 | system.cpu0.fetch.icacheStallCycles 40554205 # Number of cycles fetch is stalled on an Icache miss |
| 1109 | system.cpu0.fetch.Insts 105662539 # Number of instructions fetch has processed |
| 1110 | system.cpu0.fetch.Branches 27349422 # Number of branches that fetch encountered |
| 1111 | system.cpu0.fetch.predictedBranches 19645483 # Number of branches that fetch has predicted taken |
| 1112 | system.cpu0.fetch.Cycles 61985766 # Number of cycles fetch has run and was not squashing or blocked |
| 1113 | system.cpu0.fetch.SquashCycles 3245353 # Number of cycles fetch has spent squashing |
| 1114 | system.cpu0.fetch.TlbCycles 132544 # Number of cycles fetch has spent waiting for tlb |
| 1115 | system.cpu0.fetch.MiscStallCycles 7121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 1116 | system.cpu0.fetch.PendingDrainCycles 440 # Number of cycles fetch has spent waiting on pipes to drain |
| 1117 | system.cpu0.fetch.PendingTrapStallCycles 622961 # Number of stall cycles due to pending traps |
| 1118 | system.cpu0.fetch.PendingQuiesceStallCycles 144030 # Number of stall cycles due to pending quiesce instructions |
| 1119 | system.cpu0.fetch.IcacheWaitRetryStallCycles 269 # Number of stall cycles due to full MSHR |
| 1120 | system.cpu0.fetch.CacheLines 20513111 # Number of cache lines fetched |
| 1121 | system.cpu0.fetch.IcacheSquashes 376873 # Number of outstanding Icache misses that were squashed |
| 1122 | system.cpu0.fetch.ItlbSquashes 3476 # Number of outstanding ITLB misses that were squashed |
| 1123 | system.cpu0.fetch.rateDist::samples 105069976 # Number of instructions fetched each cycle (Total) |
| 1124 | system.cpu0.fetch.rateDist::mean 1.208080 # Number of instructions fetched each cycle (Total) |
| 1125 | system.cpu0.fetch.rateDist::stdev 2.305286 # Number of instructions fetched each cycle (Total) |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1126 | system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1127 | system.cpu0.fetch.rateDist::0 75961238 72.30% 72.30% # Number of instructions fetched each cycle (Total) |
| 1128 | system.cpu0.fetch.rateDist::1 3886755 3.70% 76.00% # Number of instructions fetched each cycle (Total) |
| 1129 | system.cpu0.fetch.rateDist::2 2398368 2.28% 78.28% # Number of instructions fetched each cycle (Total) |
| 1130 | system.cpu0.fetch.rateDist::3 8188948 7.79% 86.07% # Number of instructions fetched each cycle (Total) |
| 1131 | system.cpu0.fetch.rateDist::4 1668369 1.59% 87.66% # Number of instructions fetched each cycle (Total) |
| 1132 | system.cpu0.fetch.rateDist::5 1057044 1.01% 88.67% # Number of instructions fetched each cycle (Total) |
| 1133 | system.cpu0.fetch.rateDist::6 6240721 5.94% 94.60% # Number of instructions fetched each cycle (Total) |
| 1134 | system.cpu0.fetch.rateDist::7 1068642 1.02% 95.62% # Number of instructions fetched each cycle (Total) |
| 1135 | system.cpu0.fetch.rateDist::8 4599891 4.38% 100.00% # Number of instructions fetched each cycle (Total) |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1136 | system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) |
| 1137 | system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) |
| 1138 | system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1139 | system.cpu0.fetch.rateDist::total 105069976 # Number of instructions fetched each cycle (Total) |
| 1140 | system.cpu0.fetch.branchRate 0.253546 # Number of branch fetches per cycle |
| 1141 | system.cpu0.fetch.rate 0.979558 # Number of inst fetches per cycle |
| 1142 | system.cpu0.decode.IdleCycles 28001193 # Number of cycles decode is idle |
| 1143 | system.cpu0.decode.BlockedCycles 58307153 # Number of cycles decode is blocked |
| 1144 | system.cpu0.decode.RunCycles 15793340 # Number of cycles decode is running |
| 1145 | system.cpu0.decode.UnblockCycles 1494905 # Number of cycles decode is unblocking |
| 1146 | system.cpu0.decode.SquashCycles 1473111 # Number of cycles decode is squashing |
| 1147 | system.cpu0.decode.BranchResolved 1905219 # Number of times decode resolved a branch |
| 1148 | system.cpu0.decode.BranchMispred 151604 # Number of times decode detected a branch misprediction |
| 1149 | system.cpu0.decode.DecodedInsts 87425197 # Number of instructions handled by decode |
| 1150 | system.cpu0.decode.SquashedInsts 489487 # Number of squashed instructions handled by decode |
| 1151 | system.cpu0.rename.SquashCycles 1473111 # Number of cycles rename is squashing |
| 1152 | system.cpu0.rename.IdleCycles 28862922 # Number of cycles rename is idle |
| 1153 | system.cpu0.rename.BlockCycles 7852670 # Number of cycles rename is blocking |
| 1154 | system.cpu0.rename.serializeStallCycles 44540857 # count of cycles rename stalled for serializing inst |
| 1155 | system.cpu0.rename.RunCycles 16413726 # Number of cycles rename is running |
| 1156 | system.cpu0.rename.UnblockCycles 5926414 # Number of cycles rename is unblocking |
| 1157 | system.cpu0.rename.RenamedInsts 83594857 # Number of instructions processed by rename |
| 1158 | system.cpu0.rename.ROBFullEvents 2128 # Number of times rename has blocked due to ROB full |
| 1159 | system.cpu0.rename.IQFullEvents 1233256 # Number of times rename has blocked due to IQ full |
| 1160 | system.cpu0.rename.LQFullEvents 243031 # Number of times rename has blocked due to LQ full |
| 1161 | system.cpu0.rename.SQFullEvents 3726809 # Number of times rename has blocked due to SQ full |
| 1162 | system.cpu0.rename.RenamedOperands 86235184 # Number of destination operands rename has renamed |
| 1163 | system.cpu0.rename.RenameLookups 384969647 # Number of register rename lookups that rename has made |
| 1164 | system.cpu0.rename.int_rename_lookups 93192750 # Number of integer rename lookups |
| 1165 | system.cpu0.rename.fp_rename_lookups 5702 # Number of floating rename lookups |
| 1166 | system.cpu0.rename.CommittedMaps 72438827 # Number of HB maps that are committed |
| 1167 | system.cpu0.rename.UndoneMaps 13796341 # Number of HB maps that are undone due to squashing |
| 1168 | system.cpu0.rename.serializingInsts 1547496 # count of serializing insts renamed |
| 1169 | system.cpu0.rename.tempSerializingInsts 1453336 # count of temporary serializing insts renamed |
| 1170 | system.cpu0.rename.skidInsts 8912532 # count of insts added to the skid buffer |
| 1171 | system.cpu0.memDep0.insertedLoads 15029778 # Number of loads inserted to the mem dependence unit. |
| 1172 | system.cpu0.memDep0.insertedStores 11466004 # Number of stores inserted to the mem dependence unit. |
| 1173 | system.cpu0.memDep0.conflictingLoads 1956224 # Number of conflicting loads. |
| 1174 | system.cpu0.memDep0.conflictingStores 2714292 # Number of conflicting stores. |
| 1175 | system.cpu0.iq.iqInstsAdded 80433839 # Number of instructions added to the IQ (excludes non-spec) |
| 1176 | system.cpu0.iq.iqNonSpecInstsAdded 1054374 # Number of non-speculative instructions added to the IQ |
| 1177 | system.cpu0.iq.iqInstsIssued 77107853 # Number of instructions issued |
| 1178 | system.cpu0.iq.iqSquashedInstsIssued 91926 # Number of squashed instructions issued |
| 1179 | system.cpu0.iq.iqSquashedInstsExamined 10053145 # Number of squashed instructions iterated over during squash; mainly for profiling |
| 1180 | system.cpu0.iq.iqSquashedOperandsExamined 24795847 # Number of squashed operands that are examined and possibly removed from graph |
| 1181 | system.cpu0.iq.iqSquashedNonSpecRemoved 115089 # Number of squashed non-spec instructions that were removed |
| 1182 | system.cpu0.iq.issued_per_cycle::samples 105069976 # Number of insts issued each cycle |
| 1183 | system.cpu0.iq.issued_per_cycle::mean 0.733871 # Number of insts issued each cycle |
| 1184 | system.cpu0.iq.issued_per_cycle::stdev 1.427930 # Number of insts issued each cycle |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1185 | system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1186 | system.cpu0.iq.issued_per_cycle::0 74334112 70.75% 70.75% # Number of insts issued each cycle |
| 1187 | system.cpu0.iq.issued_per_cycle::1 10187384 9.70% 80.44% # Number of insts issued each cycle |
| 1188 | system.cpu0.iq.issued_per_cycle::2 7871575 7.49% 87.93% # Number of insts issued each cycle |
| 1189 | system.cpu0.iq.issued_per_cycle::3 6574512 6.26% 94.19% # Number of insts issued each cycle |
| 1190 | system.cpu0.iq.issued_per_cycle::4 2321319 2.21% 96.40% # Number of insts issued each cycle |
| 1191 | system.cpu0.iq.issued_per_cycle::5 1487177 1.42% 97.82% # Number of insts issued each cycle |
| 1192 | system.cpu0.iq.issued_per_cycle::6 1563743 1.49% 99.31% # Number of insts issued each cycle |
| 1193 | system.cpu0.iq.issued_per_cycle::7 491068 0.47% 99.77% # Number of insts issued each cycle |
| 1194 | system.cpu0.iq.issued_per_cycle::8 239086 0.23% 100.00% # Number of insts issued each cycle |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1195 | system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle |
| 1196 | system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle |
| 1197 | system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1198 | system.cpu0.iq.issued_per_cycle::total 105069976 # Number of insts issued each cycle |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1199 | system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1200 | system.cpu0.iq.fu_full::IntAlu 112390 9.87% 9.87% # attempts to use FU when none available |
| 1201 | system.cpu0.iq.fu_full::IntMult 3 0.00% 9.87% # attempts to use FU when none available |
| 1202 | system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.87% # attempts to use FU when none available |
| 1203 | system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.87% # attempts to use FU when none available |
| 1204 | system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.87% # attempts to use FU when none available |
| 1205 | system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.87% # attempts to use FU when none available |
| 1206 | system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.87% # attempts to use FU when none available |
| 1207 | system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.87% # attempts to use FU when none available |
| 1208 | system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.87% # attempts to use FU when none available |
| 1209 | system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.87% # attempts to use FU when none available |
| 1210 | system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.87% # attempts to use FU when none available |
| 1211 | system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.87% # attempts to use FU when none available |
| 1212 | system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.87% # attempts to use FU when none available |
| 1213 | system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.87% # attempts to use FU when none available |
| 1214 | system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.87% # attempts to use FU when none available |
| 1215 | system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.87% # attempts to use FU when none available |
| 1216 | system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.87% # attempts to use FU when none available |
| 1217 | system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.87% # attempts to use FU when none available |
| 1218 | system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.87% # attempts to use FU when none available |
| 1219 | system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.87% # attempts to use FU when none available |
| 1220 | system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.87% # attempts to use FU when none available |
| 1221 | system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.87% # attempts to use FU when none available |
| 1222 | system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.87% # attempts to use FU when none available |
| 1223 | system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.87% # attempts to use FU when none available |
| 1224 | system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.87% # attempts to use FU when none available |
| 1225 | system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.87% # attempts to use FU when none available |
| 1226 | system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.87% # attempts to use FU when none available |
| 1227 | system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.87% # attempts to use FU when none available |
| 1228 | system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.87% # attempts to use FU when none available |
| 1229 | system.cpu0.iq.fu_full::MemRead 534190 46.93% 56.80% # attempts to use FU when none available |
| 1230 | system.cpu0.iq.fu_full::MemWrite 491756 43.20% 100.00% # attempts to use FU when none available |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1231 | system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available |
| 1232 | system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1233 | system.cpu0.iq.FU_type_0::No_OpClass 2199 0.00% 0.00% # Type of FU issued |
| 1234 | system.cpu0.iq.FU_type_0::IntAlu 51438430 66.71% 66.71% # Type of FU issued |
| 1235 | system.cpu0.iq.FU_type_0::IntMult 57761 0.07% 66.79% # Type of FU issued |
| 1236 | system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued |
| 1237 | system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.79% # Type of FU issued |
| 1238 | system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.79% # Type of FU issued |
| 1239 | system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.79% # Type of FU issued |
| 1240 | system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.79% # Type of FU issued |
| 1241 | system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.79% # Type of FU issued |
| 1242 | system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.79% # Type of FU issued |
| 1243 | system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.79% # Type of FU issued |
| 1244 | system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.79% # Type of FU issued |
| 1245 | system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 66.79% # Type of FU issued |
| 1246 | system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.79% # Type of FU issued |
| 1247 | system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.79% # Type of FU issued |
| 1248 | system.cpu0.iq.FU_type_0::SimdMisc 1 0.00% 66.79% # Type of FU issued |
| 1249 | system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.79% # Type of FU issued |
| 1250 | system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.79% # Type of FU issued |
| 1251 | system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.79% # Type of FU issued |
| 1252 | system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.79% # Type of FU issued |
| 1253 | system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.79% # Type of FU issued |
| 1254 | system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.79% # Type of FU issued |
| 1255 | system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.79% # Type of FU issued |
| 1256 | system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.79% # Type of FU issued |
| 1257 | system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.79% # Type of FU issued |
| 1258 | system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.79% # Type of FU issued |
| 1259 | system.cpu0.iq.FU_type_0::SimdFloatMisc 4468 0.01% 66.79% # Type of FU issued |
| 1260 | system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.79% # Type of FU issued |
| 1261 | system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 66.79% # Type of FU issued |
| 1262 | system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.79% # Type of FU issued |
| 1263 | system.cpu0.iq.FU_type_0::MemRead 14680887 19.04% 85.83% # Type of FU issued |
| 1264 | system.cpu0.iq.FU_type_0::MemWrite 10924099 14.17% 100.00% # Type of FU issued |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1265 | system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued |
| 1266 | system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1267 | system.cpu0.iq.FU_type_0::total 77107853 # Type of FU issued |
| 1268 | system.cpu0.iq.rate 0.714838 # Inst issue rate |
| 1269 | system.cpu0.iq.fu_busy_cnt 1138339 # FU busy when requested |
| 1270 | system.cpu0.iq.fu_busy_rate 0.014763 # FU busy rate (busy events/executed inst) |
| 1271 | system.cpu0.iq.int_inst_queue_reads 260503389 # Number of integer instruction queue reads |
| 1272 | system.cpu0.iq.int_inst_queue_writes 91586031 # Number of integer instruction queue writes |
| 1273 | system.cpu0.iq.int_inst_queue_wakeup_accesses 74660496 # Number of integer instruction queue wakeup accesses |
| 1274 | system.cpu0.iq.fp_inst_queue_reads 12558 # Number of floating instruction queue reads |
| 1275 | system.cpu0.iq.fp_inst_queue_writes 6677 # Number of floating instruction queue writes |
| 1276 | system.cpu0.iq.fp_inst_queue_wakeup_accesses 5497 # Number of floating instruction queue wakeup accesses |
| 1277 | system.cpu0.iq.int_alu_accesses 78237256 # Number of integer alu accesses |
| 1278 | system.cpu0.iq.fp_alu_accesses 6737 # Number of floating point alu accesses |
| 1279 | system.cpu0.iew.lsq.thread0.forwLoads 345558 # Number of loads that had data forwarded from stores |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1280 | system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1281 | system.cpu0.iew.lsq.thread0.squashedLoads 2209259 # Number of loads squashed |
| 1282 | system.cpu0.iew.lsq.thread0.ignoredResponses 2417 # Number of memory responses ignored because the instruction is squashed |
| 1283 | system.cpu0.iew.lsq.thread0.memOrderViolation 52309 # Number of memory ordering violations |
| 1284 | system.cpu0.iew.lsq.thread0.squashedStores 1126312 # Number of stores squashed |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1285 | system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address |
| 1286 | system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1287 | system.cpu0.iew.lsq.thread0.rescheduledLoads 207644 # Number of loads that were rescheduled |
| 1288 | system.cpu0.iew.lsq.thread0.cacheBlocked 205299 # Number of times an access to memory failed due to the cache being blocked |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1289 | system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1290 | system.cpu0.iew.iewSquashCycles 1473111 # Number of cycles IEW is squashing |
| 1291 | system.cpu0.iew.iewBlockCycles 5378277 # Number of cycles IEW is blocking |
| 1292 | system.cpu0.iew.iewUnblockCycles 2195764 # Number of cycles IEW is unblocking |
| 1293 | system.cpu0.iew.iewDispatchedInsts 81614966 # Number of instructions dispatched to IQ |
| 1294 | system.cpu0.iew.iewDispSquashedInsts 130944 # Number of squashed instructions skipped by dispatch |
| 1295 | system.cpu0.iew.iewDispLoadInsts 15029778 # Number of dispatched load instructions |
| 1296 | system.cpu0.iew.iewDispStoreInsts 11466004 # Number of dispatched store instructions |
| 1297 | system.cpu0.iew.iewDispNonSpecInsts 550994 # Number of dispatched non-speculative instructions |
| 1298 | system.cpu0.iew.iewIQFullEvents 44204 # Number of times the IQ has become full, causing a stall |
| 1299 | system.cpu0.iew.iewLSQFullEvents 2139047 # Number of times the LSQ has become full, causing a stall |
| 1300 | system.cpu0.iew.memOrderViolationEvents 52309 # Number of memory order violations |
| 1301 | system.cpu0.iew.predictedTakenIncorrect 254090 # Number of branches that were predicted taken incorrectly |
| 1302 | system.cpu0.iew.predictedNotTakenIncorrect 219689 # Number of branches that were predicted not taken incorrectly |
| 1303 | system.cpu0.iew.branchMispredicts 473779 # Number of branch mispredicts detected at execute |
| 1304 | system.cpu0.iew.iewExecutedInsts 76503781 # Number of executed instructions |
| 1305 | system.cpu0.iew.iewExecLoadInsts 14445333 # Number of load instructions executed |
| 1306 | system.cpu0.iew.iewExecSquashedInsts 547436 # Number of squashed instructions skipped in execute |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1307 | system.cpu0.iew.exec_swp 0 # number of swp insts executed |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1308 | system.cpu0.iew.exec_nop 126753 # number of nop insts executed |
| 1309 | system.cpu0.iew.exec_refs 25264055 # number of memory reference insts executed |
| 1310 | system.cpu0.iew.exec_branches 14430009 # Number of branches executed |
| 1311 | system.cpu0.iew.exec_stores 10818722 # Number of stores executed |
| 1312 | system.cpu0.iew.exec_rate 0.709238 # Inst execution rate |
| 1313 | system.cpu0.iew.wb_sent 75844960 # cumulative count of insts sent to commit |
| 1314 | system.cpu0.iew.wb_count 74665993 # cumulative count of insts written-back |
| 1315 | system.cpu0.iew.wb_producers 39001048 # num instructions producing a value |
| 1316 | system.cpu0.iew.wb_consumers 67639279 # num instructions consuming a value |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1317 | system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1318 | system.cpu0.iew.wb_rate 0.692200 # insts written-back per cycle |
| 1319 | system.cpu0.iew.wb_fanout 0.576604 # average fanout of values written-back |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1320 | system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1321 | system.cpu0.commit.commitSquashedInsts 11323076 # The number of squashed insts skipped by commit |
| 1322 | system.cpu0.commit.commitNonSpecStalls 939285 # The number of times commit has been forced to stall to communicate backwards |
| 1323 | system.cpu0.commit.branchMispredicts 399913 # The number of times a branch was mispredicted |
| 1324 | system.cpu0.commit.committed_per_cycle::samples 102514186 # Number of insts commited each cycle |
| 1325 | system.cpu0.commit.committed_per_cycle::mean 0.684864 # Number of insts commited each cycle |
| 1326 | system.cpu0.commit.committed_per_cycle::stdev 1.574695 # Number of insts commited each cycle |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1327 | system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1328 | system.cpu0.commit.committed_per_cycle::0 75189561 73.35% 73.35% # Number of insts commited each cycle |
| 1329 | system.cpu0.commit.committed_per_cycle::1 12242134 11.94% 85.29% # Number of insts commited each cycle |
| 1330 | system.cpu0.commit.committed_per_cycle::2 6265138 6.11% 91.40% # Number of insts commited each cycle |
| 1331 | system.cpu0.commit.committed_per_cycle::3 2642512 2.58% 93.98% # Number of insts commited each cycle |
| 1332 | system.cpu0.commit.committed_per_cycle::4 1297372 1.27% 95.24% # Number of insts commited each cycle |
| 1333 | system.cpu0.commit.committed_per_cycle::5 836423 0.82% 96.06% # Number of insts commited each cycle |
| 1334 | system.cpu0.commit.committed_per_cycle::6 1889134 1.84% 97.90% # Number of insts commited each cycle |
| 1335 | system.cpu0.commit.committed_per_cycle::7 413413 0.40% 98.30% # Number of insts commited each cycle |
| 1336 | system.cpu0.commit.committed_per_cycle::8 1738499 1.70% 100.00% # Number of insts commited each cycle |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1337 | system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle |
| 1338 | system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle |
| 1339 | system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1340 | system.cpu0.commit.committed_per_cycle::total 102514186 # Number of insts commited each cycle |
| 1341 | system.cpu0.commit.committedInsts 57883100 # Number of instructions committed |
| 1342 | system.cpu0.commit.committedOps 70208236 # Number of ops (including micro ops) committed |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1343 | system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1344 | system.cpu0.commit.refs 23160211 # Number of memory references committed |
| 1345 | system.cpu0.commit.loads 12820519 # Number of loads committed |
| 1346 | system.cpu0.commit.membars 372556 # Number of memory barriers committed |
| 1347 | system.cpu0.commit.branches 13646736 # Number of branches committed |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1348 | system.cpu0.commit.fp_insts 5463 # Number of committed floating point instructions. |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1349 | system.cpu0.commit.int_insts 61470931 # Number of committed integer instructions. |
| 1350 | system.cpu0.commit.function_calls 2656843 # Number of function calls committed. |
Andreas Hansson | 57e5401 | 2014-05-09 18:58:50 -0400 | [diff] [blame] | 1351 | system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1352 | system.cpu0.commit.op_class_0::IntAlu 46987548 66.93% 66.93% # Class of committed instruction |
| 1353 | system.cpu0.commit.op_class_0::IntMult 56009 0.08% 67.01% # Class of committed instruction |
| 1354 | system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.01% # Class of committed instruction |
| 1355 | system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.01% # Class of committed instruction |
| 1356 | system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.01% # Class of committed instruction |
| 1357 | system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.01% # Class of committed instruction |
| 1358 | system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.01% # Class of committed instruction |
| 1359 | system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.01% # Class of committed instruction |
| 1360 | system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.01% # Class of committed instruction |
| 1361 | system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.01% # Class of committed instruction |
| 1362 | system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.01% # Class of committed instruction |
| 1363 | system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.01% # Class of committed instruction |
| 1364 | system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.01% # Class of committed instruction |
| 1365 | system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.01% # Class of committed instruction |
| 1366 | system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.01% # Class of committed instruction |
| 1367 | system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.01% # Class of committed instruction |
| 1368 | system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.01% # Class of committed instruction |
| 1369 | system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.01% # Class of committed instruction |
| 1370 | system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.01% # Class of committed instruction |
| 1371 | system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.01% # Class of committed instruction |
| 1372 | system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.01% # Class of committed instruction |
| 1373 | system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.01% # Class of committed instruction |
| 1374 | system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.01% # Class of committed instruction |
| 1375 | system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.01% # Class of committed instruction |
| 1376 | system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.01% # Class of committed instruction |
| 1377 | system.cpu0.commit.op_class_0::SimdFloatMisc 4468 0.01% 67.01% # Class of committed instruction |
| 1378 | system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.01% # Class of committed instruction |
| 1379 | system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.01% # Class of committed instruction |
| 1380 | system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.01% # Class of committed instruction |
| 1381 | system.cpu0.commit.op_class_0::MemRead 12820519 18.26% 85.27% # Class of committed instruction |
| 1382 | system.cpu0.commit.op_class_0::MemWrite 10339692 14.73% 100.00% # Class of committed instruction |
Andreas Hansson | 57e5401 | 2014-05-09 18:58:50 -0400 | [diff] [blame] | 1383 | system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction |
| 1384 | system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1385 | system.cpu0.commit.op_class_0::total 70208236 # Class of committed instruction |
| 1386 | system.cpu0.commit.bw_lim_events 1738499 # number cycles where commit BW limit reached |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1387 | system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1388 | system.cpu0.rob.rob_reads 169645518 # The number of ROB reads |
| 1389 | system.cpu0.rob.rob_writes 165622521 # The number of ROB writes |
| 1390 | system.cpu0.timesIdled 399235 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 1391 | system.cpu0.idleCycles 2797631 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 1392 | system.cpu0.quiesceCycles 2442097834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt |
| 1393 | system.cpu0.committedInsts 57811199 # Number of Instructions Simulated |
| 1394 | system.cpu0.committedOps 70136335 # Number of Ops (including micro ops) Simulated |
| 1395 | system.cpu0.cpi 1.865860 # CPI: Cycles Per Instruction |
| 1396 | system.cpu0.cpi_total 1.865860 # CPI: Total CPI of All Threads |
| 1397 | system.cpu0.ipc 0.535946 # IPC: Instructions Per Cycle |
| 1398 | system.cpu0.ipc_total 0.535946 # IPC: Total IPC of All Threads |
| 1399 | system.cpu0.int_regfile_reads 83226933 # number of integer regfile reads |
| 1400 | system.cpu0.int_regfile_writes 47573974 # number of integer regfile writes |
| 1401 | system.cpu0.fp_regfile_reads 16207 # number of floating regfile reads |
| 1402 | system.cpu0.fp_regfile_writes 13000 # number of floating regfile writes |
| 1403 | system.cpu0.cc_regfile_reads 270444340 # number of cc regfile reads |
| 1404 | system.cpu0.cc_regfile_writes 28203341 # number of cc regfile writes |
| 1405 | system.cpu0.misc_regfile_reads 191459430 # number of misc regfile reads |
| 1406 | system.cpu0.misc_regfile_writes 720407 # number of misc regfile writes |
| 1407 | system.cpu0.icache.tags.replacements 1944509 # number of replacements |
| 1408 | system.cpu0.icache.tags.tagsinuse 511.580286 # Cycle average of tags in use |
| 1409 | system.cpu0.icache.tags.total_refs 39079293 # Total number of references to valid blocks. |
| 1410 | system.cpu0.icache.tags.sampled_refs 1945021 # Sample count of references to valid blocks. |
| 1411 | system.cpu0.icache.tags.avg_refs 20.091965 # Average number of references to valid blocks. |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1412 | system.cpu0.icache.tags.warmup_cycle 9481344250 # Cycle when the warmup percentage was hit. |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1413 | system.cpu0.icache.tags.occ_blocks::cpu0.inst 277.092053 # Average occupied blocks per requestor |
| 1414 | system.cpu0.icache.tags.occ_blocks::cpu1.inst 234.488233 # Average occupied blocks per requestor |
| 1415 | system.cpu0.icache.tags.occ_percent::cpu0.inst 0.541195 # Average percentage of cache occupancy |
| 1416 | system.cpu0.icache.tags.occ_percent::cpu1.inst 0.457985 # Average percentage of cache occupancy |
| 1417 | system.cpu0.icache.tags.occ_percent::total 0.999180 # Average percentage of cache occupancy |
Ali Saidi | f3585c8 | 2014-01-24 15:29:33 -0600 | [diff] [blame] | 1418 | system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1419 | system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1420 | system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id |
| 1421 | system.cpu0.icache.tags.age_task_id_blocks_1024::2 154 # Occupied blocks per task id |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1422 | system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id |
Ali Saidi | f3585c8 | 2014-01-24 15:29:33 -0600 | [diff] [blame] | 1423 | system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1424 | system.cpu0.icache.tags.tag_accesses 43109447 # Number of tag accesses |
| 1425 | system.cpu0.icache.tags.data_accesses 43109447 # Number of data accesses |
| 1426 | system.cpu0.icache.ReadReq_hits::cpu0.inst 19472177 # number of ReadReq hits |
| 1427 | system.cpu0.icache.ReadReq_hits::cpu1.inst 19607116 # number of ReadReq hits |
| 1428 | system.cpu0.icache.ReadReq_hits::total 39079293 # number of ReadReq hits |
| 1429 | system.cpu0.icache.demand_hits::cpu0.inst 19472177 # number of demand (read+write) hits |
| 1430 | system.cpu0.icache.demand_hits::cpu1.inst 19607116 # number of demand (read+write) hits |
| 1431 | system.cpu0.icache.demand_hits::total 39079293 # number of demand (read+write) hits |
| 1432 | system.cpu0.icache.overall_hits::cpu0.inst 19472177 # number of overall hits |
| 1433 | system.cpu0.icache.overall_hits::cpu1.inst 19607116 # number of overall hits |
| 1434 | system.cpu0.icache.overall_hits::total 39079293 # number of overall hits |
| 1435 | system.cpu0.icache.ReadReq_misses::cpu0.inst 1040272 # number of ReadReq misses |
| 1436 | system.cpu0.icache.ReadReq_misses::cpu1.inst 1044765 # number of ReadReq misses |
| 1437 | system.cpu0.icache.ReadReq_misses::total 2085037 # number of ReadReq misses |
| 1438 | system.cpu0.icache.demand_misses::cpu0.inst 1040272 # number of demand (read+write) misses |
| 1439 | system.cpu0.icache.demand_misses::cpu1.inst 1044765 # number of demand (read+write) misses |
| 1440 | system.cpu0.icache.demand_misses::total 2085037 # number of demand (read+write) misses |
| 1441 | system.cpu0.icache.overall_misses::cpu0.inst 1040272 # number of overall misses |
| 1442 | system.cpu0.icache.overall_misses::cpu1.inst 1044765 # number of overall misses |
| 1443 | system.cpu0.icache.overall_misses::total 2085037 # number of overall misses |
| 1444 | system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14234369484 # number of ReadReq miss cycles |
| 1445 | system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14196293397 # number of ReadReq miss cycles |
| 1446 | system.cpu0.icache.ReadReq_miss_latency::total 28430662881 # number of ReadReq miss cycles |
| 1447 | system.cpu0.icache.demand_miss_latency::cpu0.inst 14234369484 # number of demand (read+write) miss cycles |
| 1448 | system.cpu0.icache.demand_miss_latency::cpu1.inst 14196293397 # number of demand (read+write) miss cycles |
| 1449 | system.cpu0.icache.demand_miss_latency::total 28430662881 # number of demand (read+write) miss cycles |
| 1450 | system.cpu0.icache.overall_miss_latency::cpu0.inst 14234369484 # number of overall miss cycles |
| 1451 | system.cpu0.icache.overall_miss_latency::cpu1.inst 14196293397 # number of overall miss cycles |
| 1452 | system.cpu0.icache.overall_miss_latency::total 28430662881 # number of overall miss cycles |
| 1453 | system.cpu0.icache.ReadReq_accesses::cpu0.inst 20512449 # number of ReadReq accesses(hits+misses) |
| 1454 | system.cpu0.icache.ReadReq_accesses::cpu1.inst 20651881 # number of ReadReq accesses(hits+misses) |
| 1455 | system.cpu0.icache.ReadReq_accesses::total 41164330 # number of ReadReq accesses(hits+misses) |
| 1456 | system.cpu0.icache.demand_accesses::cpu0.inst 20512449 # number of demand (read+write) accesses |
| 1457 | system.cpu0.icache.demand_accesses::cpu1.inst 20651881 # number of demand (read+write) accesses |
| 1458 | system.cpu0.icache.demand_accesses::total 41164330 # number of demand (read+write) accesses |
| 1459 | system.cpu0.icache.overall_accesses::cpu0.inst 20512449 # number of overall (read+write) accesses |
| 1460 | system.cpu0.icache.overall_accesses::cpu1.inst 20651881 # number of overall (read+write) accesses |
| 1461 | system.cpu0.icache.overall_accesses::total 41164330 # number of overall (read+write) accesses |
| 1462 | system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050714 # miss rate for ReadReq accesses |
| 1463 | system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050589 # miss rate for ReadReq accesses |
| 1464 | system.cpu0.icache.ReadReq_miss_rate::total 0.050652 # miss rate for ReadReq accesses |
| 1465 | system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050714 # miss rate for demand accesses |
| 1466 | system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050589 # miss rate for demand accesses |
| 1467 | system.cpu0.icache.demand_miss_rate::total 0.050652 # miss rate for demand accesses |
| 1468 | system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050714 # miss rate for overall accesses |
| 1469 | system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050589 # miss rate for overall accesses |
| 1470 | system.cpu0.icache.overall_miss_rate::total 0.050652 # miss rate for overall accesses |
| 1471 | system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13683.315021 # average ReadReq miss latency |
| 1472 | system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13588.025438 # average ReadReq miss latency |
| 1473 | system.cpu0.icache.ReadReq_avg_miss_latency::total 13635.567561 # average ReadReq miss latency |
| 1474 | system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13683.315021 # average overall miss latency |
| 1475 | system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13588.025438 # average overall miss latency |
| 1476 | system.cpu0.icache.demand_avg_miss_latency::total 13635.567561 # average overall miss latency |
| 1477 | system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13683.315021 # average overall miss latency |
| 1478 | system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13588.025438 # average overall miss latency |
| 1479 | system.cpu0.icache.overall_avg_miss_latency::total 13635.567561 # average overall miss latency |
| 1480 | system.cpu0.icache.blocked_cycles::no_mshrs 8976 # number of cycles access was blocked |
Steve Reinhardt | 5b08e21 | 2014-06-22 14:33:09 -0700 | [diff] [blame] | 1481 | system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1482 | system.cpu0.icache.blocked::no_mshrs 503 # number of cycles access was blocked |
Steve Reinhardt | 5b08e21 | 2014-06-22 14:33:09 -0700 | [diff] [blame] | 1483 | system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1484 | system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.844930 # average number of cycles each access was blocked |
Steve Reinhardt | 5b08e21 | 2014-06-22 14:33:09 -0700 | [diff] [blame] | 1485 | system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1486 | system.cpu0.icache.fast_writes 0 # number of fast writes performed |
| 1487 | system.cpu0.icache.cache_copies 0 # number of cache copies performed |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1488 | system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 69341 # number of ReadReq MSHR hits |
| 1489 | system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 70578 # number of ReadReq MSHR hits |
| 1490 | system.cpu0.icache.ReadReq_mshr_hits::total 139919 # number of ReadReq MSHR hits |
| 1491 | system.cpu0.icache.demand_mshr_hits::cpu0.inst 69341 # number of demand (read+write) MSHR hits |
| 1492 | system.cpu0.icache.demand_mshr_hits::cpu1.inst 70578 # number of demand (read+write) MSHR hits |
| 1493 | system.cpu0.icache.demand_mshr_hits::total 139919 # number of demand (read+write) MSHR hits |
| 1494 | system.cpu0.icache.overall_mshr_hits::cpu0.inst 69341 # number of overall MSHR hits |
| 1495 | system.cpu0.icache.overall_mshr_hits::cpu1.inst 70578 # number of overall MSHR hits |
| 1496 | system.cpu0.icache.overall_mshr_hits::total 139919 # number of overall MSHR hits |
| 1497 | system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 970931 # number of ReadReq MSHR misses |
| 1498 | system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 974187 # number of ReadReq MSHR misses |
| 1499 | system.cpu0.icache.ReadReq_mshr_misses::total 1945118 # number of ReadReq MSHR misses |
| 1500 | system.cpu0.icache.demand_mshr_misses::cpu0.inst 970931 # number of demand (read+write) MSHR misses |
| 1501 | system.cpu0.icache.demand_mshr_misses::cpu1.inst 974187 # number of demand (read+write) MSHR misses |
| 1502 | system.cpu0.icache.demand_mshr_misses::total 1945118 # number of demand (read+write) MSHR misses |
| 1503 | system.cpu0.icache.overall_mshr_misses::cpu0.inst 970931 # number of overall MSHR misses |
| 1504 | system.cpu0.icache.overall_mshr_misses::cpu1.inst 974187 # number of overall MSHR misses |
| 1505 | system.cpu0.icache.overall_mshr_misses::total 1945118 # number of overall MSHR misses |
| 1506 | system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11624310724 # number of ReadReq MSHR miss cycles |
| 1507 | system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11588912543 # number of ReadReq MSHR miss cycles |
| 1508 | system.cpu0.icache.ReadReq_mshr_miss_latency::total 23213223267 # number of ReadReq MSHR miss cycles |
| 1509 | system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11624310724 # number of demand (read+write) MSHR miss cycles |
| 1510 | system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11588912543 # number of demand (read+write) MSHR miss cycles |
| 1511 | system.cpu0.icache.demand_mshr_miss_latency::total 23213223267 # number of demand (read+write) MSHR miss cycles |
| 1512 | system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11624310724 # number of overall MSHR miss cycles |
| 1513 | system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11588912543 # number of overall MSHR miss cycles |
| 1514 | system.cpu0.icache.overall_mshr_miss_latency::total 23213223267 # number of overall MSHR miss cycles |
| 1515 | system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 49455500 # number of ReadReq MSHR uncacheable cycles |
| 1516 | system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 49455500 # number of ReadReq MSHR uncacheable cycles |
| 1517 | system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 49455500 # number of overall MSHR uncacheable cycles |
| 1518 | system.cpu0.icache.overall_mshr_uncacheable_latency::total 49455500 # number of overall MSHR uncacheable cycles |
| 1519 | system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047334 # mshr miss rate for ReadReq accesses |
| 1520 | system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047172 # mshr miss rate for ReadReq accesses |
| 1521 | system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047253 # mshr miss rate for ReadReq accesses |
| 1522 | system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047334 # mshr miss rate for demand accesses |
| 1523 | system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.047172 # mshr miss rate for demand accesses |
| 1524 | system.cpu0.icache.demand_mshr_miss_rate::total 0.047253 # mshr miss rate for demand accesses |
| 1525 | system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047334 # mshr miss rate for overall accesses |
| 1526 | system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.047172 # mshr miss rate for overall accesses |
| 1527 | system.cpu0.icache.overall_mshr_miss_rate::total 0.047253 # mshr miss rate for overall accesses |
| 1528 | system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11972.334516 # average ReadReq mshr miss latency |
| 1529 | system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.983567 # average ReadReq mshr miss latency |
| 1530 | system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11934.095138 # average ReadReq mshr miss latency |
| 1531 | system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11972.334516 # average overall mshr miss latency |
| 1532 | system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.983567 # average overall mshr miss latency |
| 1533 | system.cpu0.icache.demand_avg_mshr_miss_latency::total 11934.095138 # average overall mshr miss latency |
| 1534 | system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11972.334516 # average overall mshr miss latency |
| 1535 | system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.983567 # average overall mshr miss latency |
| 1536 | system.cpu0.icache.overall_avg_mshr_miss_latency::total 11934.095138 # average overall mshr miss latency |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1537 | system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency |
| 1538 | system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
| 1539 | system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency |
| 1540 | system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
| 1541 | system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1542 | system.cpu0.dcache.tags.replacements 852532 # number of replacements |
| 1543 | system.cpu0.dcache.tags.tagsinuse 511.984435 # Cycle average of tags in use |
| 1544 | system.cpu0.dcache.tags.total_refs 42510984 # Total number of references to valid blocks. |
| 1545 | system.cpu0.dcache.tags.sampled_refs 853044 # Sample count of references to valid blocks. |
| 1546 | system.cpu0.dcache.tags.avg_refs 49.834456 # Average number of references to valid blocks. |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1547 | system.cpu0.dcache.tags.warmup_cycle 91705250 # Cycle when the warmup percentage was hit. |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1548 | system.cpu0.dcache.tags.occ_blocks::cpu0.data 328.580964 # Average occupied blocks per requestor |
| 1549 | system.cpu0.dcache.tags.occ_blocks::cpu1.data 183.403471 # Average occupied blocks per requestor |
| 1550 | system.cpu0.dcache.tags.occ_percent::cpu0.data 0.641760 # Average percentage of cache occupancy |
| 1551 | system.cpu0.dcache.tags.occ_percent::cpu1.data 0.358210 # Average percentage of cache occupancy |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1552 | system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy |
Ali Saidi | f3585c8 | 2014-01-24 15:29:33 -0600 | [diff] [blame] | 1553 | system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1554 | system.cpu0.dcache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1555 | system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1556 | system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id |
Ali Saidi | f3585c8 | 2014-01-24 15:29:33 -0600 | [diff] [blame] | 1557 | system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1558 | system.cpu0.dcache.tags.tag_accesses 189858417 # Number of tag accesses |
| 1559 | system.cpu0.dcache.tags.data_accesses 189858417 # Number of data accesses |
| 1560 | system.cpu0.dcache.ReadReq_hits::cpu0.data 12600621 # number of ReadReq hits |
| 1561 | system.cpu0.dcache.ReadReq_hits::cpu1.data 12736293 # number of ReadReq hits |
| 1562 | system.cpu0.dcache.ReadReq_hits::total 25336914 # number of ReadReq hits |
| 1563 | system.cpu0.dcache.WriteReq_hits::cpu0.data 7729736 # number of WriteReq hits |
| 1564 | system.cpu0.dcache.WriteReq_hits::cpu1.data 8172690 # number of WriteReq hits |
| 1565 | system.cpu0.dcache.WriteReq_hits::total 15902426 # number of WriteReq hits |
| 1566 | system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180938 # number of SoftPFReq hits |
| 1567 | system.cpu0.dcache.SoftPFReq_hits::cpu1.data 181427 # number of SoftPFReq hits |
| 1568 | system.cpu0.dcache.SoftPFReq_hits::total 362365 # number of SoftPFReq hits |
| 1569 | system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 207885 # number of LoadLockedReq hits |
| 1570 | system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 238844 # number of LoadLockedReq hits |
| 1571 | system.cpu0.dcache.LoadLockedReq_hits::total 446729 # number of LoadLockedReq hits |
| 1572 | system.cpu0.dcache.StoreCondReq_hits::cpu0.data 213819 # number of StoreCondReq hits |
| 1573 | system.cpu0.dcache.StoreCondReq_hits::cpu1.data 245596 # number of StoreCondReq hits |
| 1574 | system.cpu0.dcache.StoreCondReq_hits::total 459415 # number of StoreCondReq hits |
| 1575 | system.cpu0.dcache.demand_hits::cpu0.data 20330357 # number of demand (read+write) hits |
| 1576 | system.cpu0.dcache.demand_hits::cpu1.data 20908983 # number of demand (read+write) hits |
| 1577 | system.cpu0.dcache.demand_hits::total 41239340 # number of demand (read+write) hits |
| 1578 | system.cpu0.dcache.overall_hits::cpu0.data 20511295 # number of overall hits |
| 1579 | system.cpu0.dcache.overall_hits::cpu1.data 21090410 # number of overall hits |
| 1580 | system.cpu0.dcache.overall_hits::total 41601705 # number of overall hits |
| 1581 | system.cpu0.dcache.ReadReq_misses::cpu0.data 423569 # number of ReadReq misses |
| 1582 | system.cpu0.dcache.ReadReq_misses::cpu1.data 406804 # number of ReadReq misses |
| 1583 | system.cpu0.dcache.ReadReq_misses::total 830373 # number of ReadReq misses |
| 1584 | system.cpu0.dcache.WriteReq_misses::cpu0.data 1914715 # number of WriteReq misses |
| 1585 | system.cpu0.dcache.WriteReq_misses::cpu1.data 1788827 # number of WriteReq misses |
| 1586 | system.cpu0.dcache.WriteReq_misses::total 3703542 # number of WriteReq misses |
| 1587 | system.cpu0.dcache.SoftPFReq_misses::cpu0.data 96924 # number of SoftPFReq misses |
| 1588 | system.cpu0.dcache.SoftPFReq_misses::cpu1.data 84951 # number of SoftPFReq misses |
| 1589 | system.cpu0.dcache.SoftPFReq_misses::total 181875 # number of SoftPFReq misses |
| 1590 | system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13440 # number of LoadLockedReq misses |
| 1591 | system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14180 # number of LoadLockedReq misses |
| 1592 | system.cpu0.dcache.LoadLockedReq_misses::total 27620 # number of LoadLockedReq misses |
| 1593 | system.cpu0.dcache.StoreCondReq_misses::cpu0.data 29 # number of StoreCondReq misses |
| 1594 | system.cpu0.dcache.StoreCondReq_misses::cpu1.data 50 # number of StoreCondReq misses |
| 1595 | system.cpu0.dcache.StoreCondReq_misses::total 79 # number of StoreCondReq misses |
| 1596 | system.cpu0.dcache.demand_misses::cpu0.data 2338284 # number of demand (read+write) misses |
| 1597 | system.cpu0.dcache.demand_misses::cpu1.data 2195631 # number of demand (read+write) misses |
| 1598 | system.cpu0.dcache.demand_misses::total 4533915 # number of demand (read+write) misses |
| 1599 | system.cpu0.dcache.overall_misses::cpu0.data 2435208 # number of overall misses |
| 1600 | system.cpu0.dcache.overall_misses::cpu1.data 2280582 # number of overall misses |
| 1601 | system.cpu0.dcache.overall_misses::total 4715790 # number of overall misses |
| 1602 | system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7009049435 # number of ReadReq miss cycles |
| 1603 | system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6678797631 # number of ReadReq miss cycles |
| 1604 | system.cpu0.dcache.ReadReq_miss_latency::total 13687847066 # number of ReadReq miss cycles |
| 1605 | system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84691128349 # number of WriteReq miss cycles |
| 1606 | system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 74764779722 # number of WriteReq miss cycles |
| 1607 | system.cpu0.dcache.WriteReq_miss_latency::total 159455908071 # number of WriteReq miss cycles |
| 1608 | system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 183084493 # number of LoadLockedReq miss cycles |
| 1609 | system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 209418995 # number of LoadLockedReq miss cycles |
| 1610 | system.cpu0.dcache.LoadLockedReq_miss_latency::total 392503488 # number of LoadLockedReq miss cycles |
| 1611 | system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 480508 # number of StoreCondReq miss cycles |
| 1612 | system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 880018 # number of StoreCondReq miss cycles |
| 1613 | system.cpu0.dcache.StoreCondReq_miss_latency::total 1360526 # number of StoreCondReq miss cycles |
| 1614 | system.cpu0.dcache.demand_miss_latency::cpu0.data 91700177784 # number of demand (read+write) miss cycles |
| 1615 | system.cpu0.dcache.demand_miss_latency::cpu1.data 81443577353 # number of demand (read+write) miss cycles |
| 1616 | system.cpu0.dcache.demand_miss_latency::total 173143755137 # number of demand (read+write) miss cycles |
| 1617 | system.cpu0.dcache.overall_miss_latency::cpu0.data 91700177784 # number of overall miss cycles |
| 1618 | system.cpu0.dcache.overall_miss_latency::cpu1.data 81443577353 # number of overall miss cycles |
| 1619 | system.cpu0.dcache.overall_miss_latency::total 173143755137 # number of overall miss cycles |
| 1620 | system.cpu0.dcache.ReadReq_accesses::cpu0.data 13024190 # number of ReadReq accesses(hits+misses) |
| 1621 | system.cpu0.dcache.ReadReq_accesses::cpu1.data 13143097 # number of ReadReq accesses(hits+misses) |
| 1622 | system.cpu0.dcache.ReadReq_accesses::total 26167287 # number of ReadReq accesses(hits+misses) |
| 1623 | system.cpu0.dcache.WriteReq_accesses::cpu0.data 9644451 # number of WriteReq accesses(hits+misses) |
| 1624 | system.cpu0.dcache.WriteReq_accesses::cpu1.data 9961517 # number of WriteReq accesses(hits+misses) |
| 1625 | system.cpu0.dcache.WriteReq_accesses::total 19605968 # number of WriteReq accesses(hits+misses) |
| 1626 | system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 277862 # number of SoftPFReq accesses(hits+misses) |
| 1627 | system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 266378 # number of SoftPFReq accesses(hits+misses) |
| 1628 | system.cpu0.dcache.SoftPFReq_accesses::total 544240 # number of SoftPFReq accesses(hits+misses) |
| 1629 | system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 221325 # number of LoadLockedReq accesses(hits+misses) |
| 1630 | system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 253024 # number of LoadLockedReq accesses(hits+misses) |
| 1631 | system.cpu0.dcache.LoadLockedReq_accesses::total 474349 # number of LoadLockedReq accesses(hits+misses) |
| 1632 | system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 213848 # number of StoreCondReq accesses(hits+misses) |
| 1633 | system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 245646 # number of StoreCondReq accesses(hits+misses) |
| 1634 | system.cpu0.dcache.StoreCondReq_accesses::total 459494 # number of StoreCondReq accesses(hits+misses) |
| 1635 | system.cpu0.dcache.demand_accesses::cpu0.data 22668641 # number of demand (read+write) accesses |
| 1636 | system.cpu0.dcache.demand_accesses::cpu1.data 23104614 # number of demand (read+write) accesses |
| 1637 | system.cpu0.dcache.demand_accesses::total 45773255 # number of demand (read+write) accesses |
| 1638 | system.cpu0.dcache.overall_accesses::cpu0.data 22946503 # number of overall (read+write) accesses |
| 1639 | system.cpu0.dcache.overall_accesses::cpu1.data 23370992 # number of overall (read+write) accesses |
| 1640 | system.cpu0.dcache.overall_accesses::total 46317495 # number of overall (read+write) accesses |
| 1641 | system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032522 # miss rate for ReadReq accesses |
| 1642 | system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030952 # miss rate for ReadReq accesses |
| 1643 | system.cpu0.dcache.ReadReq_miss_rate::total 0.031733 # miss rate for ReadReq accesses |
| 1644 | system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.198530 # miss rate for WriteReq accesses |
| 1645 | system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.179574 # miss rate for WriteReq accesses |
| 1646 | system.cpu0.dcache.WriteReq_miss_rate::total 0.188899 # miss rate for WriteReq accesses |
| 1647 | system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.348821 # miss rate for SoftPFReq accesses |
| 1648 | system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.318911 # miss rate for SoftPFReq accesses |
| 1649 | system.cpu0.dcache.SoftPFReq_miss_rate::total 0.334182 # miss rate for SoftPFReq accesses |
| 1650 | system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060725 # miss rate for LoadLockedReq accesses |
| 1651 | system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056042 # miss rate for LoadLockedReq accesses |
| 1652 | system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058227 # miss rate for LoadLockedReq accesses |
| 1653 | system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000136 # miss rate for StoreCondReq accesses |
| 1654 | system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000204 # miss rate for StoreCondReq accesses |
| 1655 | system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000172 # miss rate for StoreCondReq accesses |
| 1656 | system.cpu0.dcache.demand_miss_rate::cpu0.data 0.103151 # miss rate for demand accesses |
| 1657 | system.cpu0.dcache.demand_miss_rate::cpu1.data 0.095030 # miss rate for demand accesses |
| 1658 | system.cpu0.dcache.demand_miss_rate::total 0.099052 # miss rate for demand accesses |
| 1659 | system.cpu0.dcache.overall_miss_rate::cpu0.data 0.106125 # miss rate for overall accesses |
| 1660 | system.cpu0.dcache.overall_miss_rate::cpu1.data 0.097582 # miss rate for overall accesses |
| 1661 | system.cpu0.dcache.overall_miss_rate::total 0.101814 # miss rate for overall accesses |
| 1662 | system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16547.597759 # average ReadReq miss latency |
| 1663 | system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16417.728515 # average ReadReq miss latency |
| 1664 | system.cpu0.dcache.ReadReq_avg_miss_latency::total 16483.974149 # average ReadReq miss latency |
| 1665 | system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44231.715085 # average WriteReq miss latency |
| 1666 | system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41795.422208 # average WriteReq miss latency |
| 1667 | system.cpu0.dcache.WriteReq_avg_miss_latency::total 43054.974959 # average WriteReq miss latency |
| 1668 | system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13622.358110 # average LoadLockedReq miss latency |
| 1669 | system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14768.617419 # average LoadLockedReq miss latency |
| 1670 | system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14210.843157 # average LoadLockedReq miss latency |
| 1671 | system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16569.241379 # average StoreCondReq miss latency |
| 1672 | system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 17600.360000 # average StoreCondReq miss latency |
| 1673 | system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17221.848101 # average StoreCondReq miss latency |
| 1674 | system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39216.869202 # average overall miss latency |
| 1675 | system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37093.472151 # average overall miss latency |
| 1676 | system.cpu0.dcache.demand_avg_miss_latency::total 38188.575467 # average overall miss latency |
| 1677 | system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37655.993978 # average overall miss latency |
| 1678 | system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35711.751366 # average overall miss latency |
| 1679 | system.cpu0.dcache.overall_avg_miss_latency::total 36715.747550 # average overall miss latency |
| 1680 | system.cpu0.dcache.blocked_cycles::no_mshrs 1113759 # number of cycles access was blocked |
| 1681 | system.cpu0.dcache.blocked_cycles::no_targets 155988 # number of cycles access was blocked |
| 1682 | system.cpu0.dcache.blocked::no_mshrs 70298 # number of cycles access was blocked |
| 1683 | system.cpu0.dcache.blocked::no_targets 2399 # number of cycles access was blocked |
| 1684 | system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.843395 # average number of cycles each access was blocked |
| 1685 | system.cpu0.dcache.avg_blocked_cycles::no_targets 65.022093 # average number of cycles each access was blocked |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1686 | system.cpu0.dcache.fast_writes 0 # number of fast writes performed |
| 1687 | system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1688 | system.cpu0.dcache.writebacks::writebacks 703423 # number of writebacks |
| 1689 | system.cpu0.dcache.writebacks::total 703423 # number of writebacks |
| 1690 | system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211999 # number of ReadReq MSHR hits |
| 1691 | system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 192913 # number of ReadReq MSHR hits |
| 1692 | system.cpu0.dcache.ReadReq_mshr_hits::total 404912 # number of ReadReq MSHR hits |
| 1693 | system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1760835 # number of WriteReq MSHR hits |
| 1694 | system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1643027 # number of WriteReq MSHR hits |
| 1695 | system.cpu0.dcache.WriteReq_mshr_hits::total 3403862 # number of WriteReq MSHR hits |
| 1696 | system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9519 # number of LoadLockedReq MSHR hits |
| 1697 | system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8988 # number of LoadLockedReq MSHR hits |
| 1698 | system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18507 # number of LoadLockedReq MSHR hits |
| 1699 | system.cpu0.dcache.demand_mshr_hits::cpu0.data 1972834 # number of demand (read+write) MSHR hits |
| 1700 | system.cpu0.dcache.demand_mshr_hits::cpu1.data 1835940 # number of demand (read+write) MSHR hits |
| 1701 | system.cpu0.dcache.demand_mshr_hits::total 3808774 # number of demand (read+write) MSHR hits |
| 1702 | system.cpu0.dcache.overall_mshr_hits::cpu0.data 1972834 # number of overall MSHR hits |
| 1703 | system.cpu0.dcache.overall_mshr_hits::cpu1.data 1835940 # number of overall MSHR hits |
| 1704 | system.cpu0.dcache.overall_mshr_hits::total 3808774 # number of overall MSHR hits |
| 1705 | system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 211570 # number of ReadReq MSHR misses |
| 1706 | system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 213891 # number of ReadReq MSHR misses |
| 1707 | system.cpu0.dcache.ReadReq_mshr_misses::total 425461 # number of ReadReq MSHR misses |
| 1708 | system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 153880 # number of WriteReq MSHR misses |
| 1709 | system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 145800 # number of WriteReq MSHR misses |
| 1710 | system.cpu0.dcache.WriteReq_mshr_misses::total 299680 # number of WriteReq MSHR misses |
| 1711 | system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 63289 # number of SoftPFReq MSHR misses |
| 1712 | system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58360 # number of SoftPFReq MSHR misses |
| 1713 | system.cpu0.dcache.SoftPFReq_mshr_misses::total 121649 # number of SoftPFReq MSHR misses |
| 1714 | system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 3921 # number of LoadLockedReq MSHR misses |
| 1715 | system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5192 # number of LoadLockedReq MSHR misses |
| 1716 | system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9113 # number of LoadLockedReq MSHR misses |
| 1717 | system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 29 # number of StoreCondReq MSHR misses |
| 1718 | system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 50 # number of StoreCondReq MSHR misses |
| 1719 | system.cpu0.dcache.StoreCondReq_mshr_misses::total 79 # number of StoreCondReq MSHR misses |
| 1720 | system.cpu0.dcache.demand_mshr_misses::cpu0.data 365450 # number of demand (read+write) MSHR misses |
| 1721 | system.cpu0.dcache.demand_mshr_misses::cpu1.data 359691 # number of demand (read+write) MSHR misses |
| 1722 | system.cpu0.dcache.demand_mshr_misses::total 725141 # number of demand (read+write) MSHR misses |
| 1723 | system.cpu0.dcache.overall_mshr_misses::cpu0.data 428739 # number of overall MSHR misses |
| 1724 | system.cpu0.dcache.overall_mshr_misses::cpu1.data 418051 # number of overall MSHR misses |
| 1725 | system.cpu0.dcache.overall_mshr_misses::total 846790 # number of overall MSHR misses |
| 1726 | system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2855948132 # number of ReadReq MSHR miss cycles |
| 1727 | system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2928153928 # number of ReadReq MSHR miss cycles |
| 1728 | system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5784102060 # number of ReadReq MSHR miss cycles |
| 1729 | system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6788973337 # number of WriteReq MSHR miss cycles |
| 1730 | system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6163703908 # number of WriteReq MSHR miss cycles |
| 1731 | system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12952677245 # number of WriteReq MSHR miss cycles |
| 1732 | system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 974890008 # number of SoftPFReq MSHR miss cycles |
| 1733 | system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 904686758 # number of SoftPFReq MSHR miss cycles |
| 1734 | system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1879576766 # number of SoftPFReq MSHR miss cycles |
| 1735 | system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 46893501 # number of LoadLockedReq MSHR miss cycles |
| 1736 | system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79693003 # number of LoadLockedReq MSHR miss cycles |
| 1737 | system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 126586504 # number of LoadLockedReq MSHR miss cycles |
| 1738 | system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 422492 # number of StoreCondReq MSHR miss cycles |
| 1739 | system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 779982 # number of StoreCondReq MSHR miss cycles |
| 1740 | system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1202474 # number of StoreCondReq MSHR miss cycles |
| 1741 | system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9644921469 # number of demand (read+write) MSHR miss cycles |
| 1742 | system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9091857836 # number of demand (read+write) MSHR miss cycles |
| 1743 | system.cpu0.dcache.demand_mshr_miss_latency::total 18736779305 # number of demand (read+write) MSHR miss cycles |
| 1744 | system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10619811477 # number of overall MSHR miss cycles |
| 1745 | system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9996544594 # number of overall MSHR miss cycles |
| 1746 | system.cpu0.dcache.overall_mshr_miss_latency::total 20616356071 # number of overall MSHR miss cycles |
| 1747 | system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3173945001 # number of ReadReq MSHR uncacheable cycles |
| 1748 | system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2610547002 # number of ReadReq MSHR uncacheable cycles |
| 1749 | system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5784492003 # number of ReadReq MSHR uncacheable cycles |
| 1750 | system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2430732877 # number of WriteReq MSHR uncacheable cycles |
| 1751 | system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2005306500 # number of WriteReq MSHR uncacheable cycles |
| 1752 | system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4436039377 # number of WriteReq MSHR uncacheable cycles |
| 1753 | system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5604677878 # number of overall MSHR uncacheable cycles |
| 1754 | system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4615853502 # number of overall MSHR uncacheable cycles |
| 1755 | system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220531380 # number of overall MSHR uncacheable cycles |
| 1756 | system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016244 # mshr miss rate for ReadReq accesses |
| 1757 | system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016274 # mshr miss rate for ReadReq accesses |
| 1758 | system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016259 # mshr miss rate for ReadReq accesses |
| 1759 | system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015955 # mshr miss rate for WriteReq accesses |
| 1760 | system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014636 # mshr miss rate for WriteReq accesses |
| 1761 | system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015285 # mshr miss rate for WriteReq accesses |
| 1762 | system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.227771 # mshr miss rate for SoftPFReq accesses |
| 1763 | system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.219087 # mshr miss rate for SoftPFReq accesses |
| 1764 | system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223521 # mshr miss rate for SoftPFReq accesses |
| 1765 | system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017716 # mshr miss rate for LoadLockedReq accesses |
| 1766 | system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020520 # mshr miss rate for LoadLockedReq accesses |
| 1767 | system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019212 # mshr miss rate for LoadLockedReq accesses |
| 1768 | system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000136 # mshr miss rate for StoreCondReq accesses |
| 1769 | system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000204 # mshr miss rate for StoreCondReq accesses |
| 1770 | system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000172 # mshr miss rate for StoreCondReq accesses |
| 1771 | system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016121 # mshr miss rate for demand accesses |
| 1772 | system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015568 # mshr miss rate for demand accesses |
| 1773 | system.cpu0.dcache.demand_mshr_miss_rate::total 0.015842 # mshr miss rate for demand accesses |
| 1774 | system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018684 # mshr miss rate for overall accesses |
| 1775 | system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017888 # mshr miss rate for overall accesses |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1776 | system.cpu0.dcache.overall_mshr_miss_rate::total 0.018282 # mshr miss rate for overall accesses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1777 | system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13498.833162 # average ReadReq mshr miss latency |
| 1778 | system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13689.935191 # average ReadReq mshr miss latency |
| 1779 | system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13594.905432 # average ReadReq mshr miss latency |
| 1780 | system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44118.620594 # average WriteReq mshr miss latency |
| 1781 | system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42275.061097 # average WriteReq mshr miss latency |
| 1782 | system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43221.693957 # average WriteReq mshr miss latency |
| 1783 | system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15403.782774 # average SoftPFReq mshr miss latency |
| 1784 | system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15501.829301 # average SoftPFReq mshr miss latency |
| 1785 | system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15450.819703 # average SoftPFReq mshr miss latency |
| 1786 | system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11959.576894 # average LoadLockedReq mshr miss latency |
| 1787 | system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15349.191641 # average LoadLockedReq mshr miss latency |
| 1788 | system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13890.760891 # average LoadLockedReq mshr miss latency |
| 1789 | system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14568.689655 # average StoreCondReq mshr miss latency |
| 1790 | system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15599.640000 # average StoreCondReq mshr miss latency |
| 1791 | system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15221.189873 # average StoreCondReq mshr miss latency |
| 1792 | system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26391.904416 # average overall mshr miss latency |
| 1793 | system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25276.856624 # average overall mshr miss latency |
| 1794 | system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25838.808321 # average overall mshr miss latency |
| 1795 | system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24769.875092 # average overall mshr miss latency |
| 1796 | system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23912.260930 # average overall mshr miss latency |
| 1797 | system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24346.480321 # average overall mshr miss latency |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1798 | system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency |
| 1799 | system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency |
| 1800 | system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
| 1801 | system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency |
| 1802 | system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency |
| 1803 | system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1804 | system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency |
| 1805 | system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency |
| 1806 | system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
| 1807 | system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1808 | system.cpu1.branchPred.lookups 27353552 # Number of BP lookups |
| 1809 | system.cpu1.branchPred.condPredicted 14236577 # Number of conditional branches predicted |
| 1810 | system.cpu1.branchPred.condIncorrect 553412 # Number of conditional branches incorrect |
| 1811 | system.cpu1.branchPred.BTBLookups 17312116 # Number of BTB lookups |
| 1812 | system.cpu1.branchPred.BTBHits 12843593 # Number of BTB hits |
Nilay Vaish | 9bc132e | 2013-01-24 12:29:00 -0600 | [diff] [blame] | 1813 | system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1814 | system.cpu1.branchPred.BTBHitPct 74.188464 # BTB Hit Percentage |
| 1815 | system.cpu1.branchPred.usedRAS 6764103 # Number of times the RAS was used to get a target. |
| 1816 | system.cpu1.branchPred.RASInCorrect 29805 # Number of incorrect RAS predictions. |
Ali Saidi | cfb805c | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 1817 | system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits |
| 1818 | system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses |
| 1819 | system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits |
| 1820 | system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses |
| 1821 | system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits |
| 1822 | system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses |
| 1823 | system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed |
| 1824 | system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 1825 | system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| 1826 | system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1827 | system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB |
| 1828 | system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1829 | system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| 1830 | system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1831 | system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| 1832 | system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses |
| 1833 | system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses |
| 1834 | system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses |
| 1835 | system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits |
| 1836 | system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses |
| 1837 | system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1838 | system.cpu1.dtb.inst_hits 0 # ITB inst hits |
| 1839 | system.cpu1.dtb.inst_misses 0 # ITB inst misses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1840 | system.cpu1.dtb.read_hits 14379922 # DTB read hits |
| 1841 | system.cpu1.dtb.read_misses 49648 # DTB read misses |
| 1842 | system.cpu1.dtb.write_hits 10687800 # DTB write hits |
| 1843 | system.cpu1.dtb.write_misses 9435 # DTB write misses |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1844 | system.cpu1.dtb.flush_tlb 178 # Number of times complete TLB was flushed |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1845 | system.cpu1.dtb.flush_tlb_mva 444 # Number of times TLB was flushed by MVA |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1846 | system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| 1847 | system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1848 | system.cpu1.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB |
| 1849 | system.cpu1.dtb.align_faults 765 # Number of TLB faults due to alignment restrictions |
| 1850 | system.cpu1.dtb.prefetch_faults 1285 # Number of TLB faults due to prefetch |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1851 | system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1852 | system.cpu1.dtb.perms_faults 532 # Number of TLB faults due to permissions restrictions |
| 1853 | system.cpu1.dtb.read_accesses 14429570 # DTB read accesses |
| 1854 | system.cpu1.dtb.write_accesses 10697235 # DTB write accesses |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1855 | system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1856 | system.cpu1.dtb.hits 25067722 # DTB hits |
| 1857 | system.cpu1.dtb.misses 59083 # DTB misses |
| 1858 | system.cpu1.dtb.accesses 25126805 # DTB accesses |
Ali Saidi | cfb805c | 2014-01-24 15:29:34 -0600 | [diff] [blame] | 1859 | system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits |
| 1860 | system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses |
| 1861 | system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits |
| 1862 | system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses |
| 1863 | system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits |
| 1864 | system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses |
| 1865 | system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed |
| 1866 | system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 1867 | system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| 1868 | system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 1869 | system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB |
| 1870 | system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1871 | system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| 1872 | system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1873 | system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| 1874 | system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses |
| 1875 | system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses |
| 1876 | system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses |
| 1877 | system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits |
| 1878 | system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses |
| 1879 | system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1880 | system.cpu1.itb.inst_hits 20653653 # ITB inst hits |
| 1881 | system.cpu1.itb.inst_misses 7569 # ITB inst misses |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1882 | system.cpu1.itb.read_hits 0 # DTB read hits |
| 1883 | system.cpu1.itb.read_misses 0 # DTB read misses |
| 1884 | system.cpu1.itb.write_hits 0 # DTB write hits |
| 1885 | system.cpu1.itb.write_misses 0 # DTB write misses |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1886 | system.cpu1.itb.flush_tlb 178 # Number of times complete TLB was flushed |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1887 | system.cpu1.itb.flush_tlb_mva 444 # Number of times TLB was flushed by MVA |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 1888 | system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| 1889 | system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1890 | system.cpu1.itb.flush_entries 2278 # Number of entries that have been flushed from TLB |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1891 | system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 1892 | system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| 1893 | system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1894 | system.cpu1.itb.perms_faults 1323 # Number of TLB faults due to permissions restrictions |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1895 | system.cpu1.itb.read_accesses 0 # DTB read accesses |
| 1896 | system.cpu1.itb.write_accesses 0 # DTB write accesses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1897 | system.cpu1.itb.inst_accesses 20661222 # ITB inst accesses |
| 1898 | system.cpu1.itb.hits 20653653 # DTB hits |
| 1899 | system.cpu1.itb.misses 7569 # DTB misses |
| 1900 | system.cpu1.itb.accesses 20661222 # DTB accesses |
| 1901 | system.cpu1.numCycles 107242523 # number of cpu cycles simulated |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1902 | system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started |
| 1903 | system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1904 | system.cpu1.fetch.icacheStallCycles 40712684 # Number of cycles fetch is stalled on an Icache miss |
| 1905 | system.cpu1.fetch.Insts 106782026 # Number of instructions fetch has processed |
| 1906 | system.cpu1.fetch.Branches 27353552 # Number of branches that fetch encountered |
| 1907 | system.cpu1.fetch.predictedBranches 19607696 # Number of branches that fetch has predicted taken |
| 1908 | system.cpu1.fetch.Cycles 61803081 # Number of cycles fetch has run and was not squashing or blocked |
| 1909 | system.cpu1.fetch.SquashCycles 3231443 # Number of cycles fetch has spent squashing |
| 1910 | system.cpu1.fetch.TlbCycles 109598 # Number of cycles fetch has spent waiting for tlb |
| 1911 | system.cpu1.fetch.MiscStallCycles 4239 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 1912 | system.cpu1.fetch.PendingDrainCycles 431 # Number of cycles fetch has spent waiting on pipes to drain |
| 1913 | system.cpu1.fetch.PendingTrapStallCycles 249521 # Number of stall cycles due to pending traps |
| 1914 | system.cpu1.fetch.PendingQuiesceStallCycles 135474 # Number of stall cycles due to pending quiesce instructions |
| 1915 | system.cpu1.fetch.IcacheWaitRetryStallCycles 174 # Number of stall cycles due to full MSHR |
| 1916 | system.cpu1.fetch.CacheLines 20651884 # Number of cache lines fetched |
| 1917 | system.cpu1.fetch.IcacheSquashes 381778 # Number of outstanding Icache misses that were squashed |
| 1918 | system.cpu1.fetch.ItlbSquashes 3230 # Number of outstanding ITLB misses that were squashed |
| 1919 | system.cpu1.fetch.rateDist::samples 104630887 # Number of instructions fetched each cycle (Total) |
| 1920 | system.cpu1.fetch.rateDist::mean 1.228118 # Number of instructions fetched each cycle (Total) |
| 1921 | system.cpu1.fetch.rateDist::stdev 2.325936 # Number of instructions fetched each cycle (Total) |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1922 | system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1923 | system.cpu1.fetch.rateDist::0 75276432 71.94% 71.94% # Number of instructions fetched each cycle (Total) |
| 1924 | system.cpu1.fetch.rateDist::1 3916697 3.74% 75.69% # Number of instructions fetched each cycle (Total) |
| 1925 | system.cpu1.fetch.rateDist::2 2503204 2.39% 78.08% # Number of instructions fetched each cycle (Total) |
| 1926 | system.cpu1.fetch.rateDist::3 8106458 7.75% 85.83% # Number of instructions fetched each cycle (Total) |
| 1927 | system.cpu1.fetch.rateDist::4 1592842 1.52% 87.35% # Number of instructions fetched each cycle (Total) |
| 1928 | system.cpu1.fetch.rateDist::5 1179592 1.13% 88.48% # Number of instructions fetched each cycle (Total) |
| 1929 | system.cpu1.fetch.rateDist::6 6154126 5.88% 94.36% # Number of instructions fetched each cycle (Total) |
| 1930 | system.cpu1.fetch.rateDist::7 1149786 1.10% 95.46% # Number of instructions fetched each cycle (Total) |
| 1931 | system.cpu1.fetch.rateDist::8 4751750 4.54% 100.00% # Number of instructions fetched each cycle (Total) |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1932 | system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) |
| 1933 | system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) |
| 1934 | system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1935 | system.cpu1.fetch.rateDist::total 104630887 # Number of instructions fetched each cycle (Total) |
| 1936 | system.cpu1.fetch.branchRate 0.255063 # Number of branch fetches per cycle |
| 1937 | system.cpu1.fetch.rate 0.995706 # Number of inst fetches per cycle |
| 1938 | system.cpu1.decode.IdleCycles 27864157 # Number of cycles decode is idle |
| 1939 | system.cpu1.decode.BlockedCycles 57830739 # Number of cycles decode is blocked |
| 1940 | system.cpu1.decode.RunCycles 15747454 # Number of cycles decode is running |
| 1941 | system.cpu1.decode.UnblockCycles 1722658 # Number of cycles decode is unblocking |
| 1942 | system.cpu1.decode.SquashCycles 1465635 # Number of cycles decode is squashing |
| 1943 | system.cpu1.decode.BranchResolved 1976909 # Number of times decode resolved a branch |
| 1944 | system.cpu1.decode.BranchMispred 152146 # Number of times decode detected a branch misprediction |
| 1945 | system.cpu1.decode.DecodedInsts 89229365 # Number of instructions handled by decode |
| 1946 | system.cpu1.decode.SquashedInsts 493204 # Number of squashed instructions handled by decode |
| 1947 | system.cpu1.rename.SquashCycles 1465635 # Number of cycles rename is squashing |
| 1948 | system.cpu1.rename.IdleCycles 28812184 # Number of cycles rename is idle |
| 1949 | system.cpu1.rename.BlockCycles 6716141 # Number of cycles rename is blocking |
| 1950 | system.cpu1.rename.serializeStallCycles 45339545 # count of cycles rename stalled for serializing inst |
| 1951 | system.cpu1.rename.RunCycles 16513270 # Number of cycles rename is running |
| 1952 | system.cpu1.rename.UnblockCycles 5783839 # Number of cycles rename is unblocking |
| 1953 | system.cpu1.rename.RenamedInsts 85351560 # Number of instructions processed by rename |
| 1954 | system.cpu1.rename.ROBFullEvents 2174 # Number of times rename has blocked due to ROB full |
| 1955 | system.cpu1.rename.IQFullEvents 1570337 # Number of times rename has blocked due to IQ full |
| 1956 | system.cpu1.rename.LQFullEvents 239520 # Number of times rename has blocked due to LQ full |
| 1957 | system.cpu1.rename.SQFullEvents 3169707 # Number of times rename has blocked due to SQ full |
| 1958 | system.cpu1.rename.RenamedOperands 88205068 # Number of destination operands rename has renamed |
| 1959 | system.cpu1.rename.RenameLookups 393510505 # Number of register rename lookups that rename has made |
| 1960 | system.cpu1.rename.int_rename_lookups 95333289 # Number of integer rename lookups |
| 1961 | system.cpu1.rename.fp_rename_lookups 6152 # Number of floating rename lookups |
| 1962 | system.cpu1.rename.CommittedMaps 74299663 # Number of HB maps that are committed |
| 1963 | system.cpu1.rename.UndoneMaps 13905405 # Number of HB maps that are undone due to squashing |
| 1964 | system.cpu1.rename.serializingInsts 1590806 # count of serializing insts renamed |
| 1965 | system.cpu1.rename.tempSerializingInsts 1489461 # count of temporary serializing insts renamed |
| 1966 | system.cpu1.rename.skidInsts 10064978 # count of insts added to the skid buffer |
| 1967 | system.cpu1.memDep0.insertedLoads 15196570 # Number of loads inserted to the mem dependence unit. |
| 1968 | system.cpu1.memDep0.insertedStores 11856807 # Number of stores inserted to the mem dependence unit. |
| 1969 | system.cpu1.memDep0.conflictingLoads 2179914 # Number of conflicting loads. |
| 1970 | system.cpu1.memDep0.conflictingStores 2787279 # Number of conflicting stores. |
| 1971 | system.cpu1.iq.iqInstsAdded 82067057 # Number of instructions added to the IQ (excludes non-spec) |
| 1972 | system.cpu1.iq.iqNonSpecInstsAdded 1161463 # Number of non-speculative instructions added to the IQ |
| 1973 | system.cpu1.iq.iqInstsIssued 78685046 # Number of instructions issued |
| 1974 | system.cpu1.iq.iqSquashedInstsIssued 94868 # Number of squashed instructions issued |
| 1975 | system.cpu1.iq.iqSquashedInstsExamined 10122036 # Number of squashed instructions iterated over during squash; mainly for profiling |
| 1976 | system.cpu1.iq.iqSquashedOperandsExamined 25487135 # Number of squashed operands that are examined and possibly removed from graph |
| 1977 | system.cpu1.iq.iqSquashedNonSpecRemoved 106552 # Number of squashed non-spec instructions that were removed |
| 1978 | system.cpu1.iq.issued_per_cycle::samples 104630887 # Number of insts issued each cycle |
| 1979 | system.cpu1.iq.issued_per_cycle::mean 0.752025 # Number of insts issued each cycle |
| 1980 | system.cpu1.iq.issued_per_cycle::stdev 1.430826 # Number of insts issued each cycle |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1981 | system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1982 | system.cpu1.iq.issued_per_cycle::0 72948465 69.72% 69.72% # Number of insts issued each cycle |
| 1983 | system.cpu1.iq.issued_per_cycle::1 10708543 10.23% 79.95% # Number of insts issued each cycle |
| 1984 | system.cpu1.iq.issued_per_cycle::2 8057357 7.70% 87.66% # Number of insts issued each cycle |
| 1985 | system.cpu1.iq.issued_per_cycle::3 6681907 6.39% 94.04% # Number of insts issued each cycle |
| 1986 | system.cpu1.iq.issued_per_cycle::4 2500436 2.39% 96.43% # Number of insts issued each cycle |
| 1987 | system.cpu1.iq.issued_per_cycle::5 1544614 1.48% 97.91% # Number of insts issued each cycle |
| 1988 | system.cpu1.iq.issued_per_cycle::6 1464658 1.40% 99.31% # Number of insts issued each cycle |
| 1989 | system.cpu1.iq.issued_per_cycle::7 495950 0.47% 99.78% # Number of insts issued each cycle |
| 1990 | system.cpu1.iq.issued_per_cycle::8 228957 0.22% 100.00% # Number of insts issued each cycle |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1991 | system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle |
| 1992 | system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle |
| 1993 | system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1994 | system.cpu1.iq.issued_per_cycle::total 104630887 # Number of insts issued each cycle |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1995 | system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 1996 | system.cpu1.iq.fu_full::IntAlu 103296 8.95% 8.95% # attempts to use FU when none available |
| 1997 | system.cpu1.iq.fu_full::IntMult 5 0.00% 8.95% # attempts to use FU when none available |
| 1998 | system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.95% # attempts to use FU when none available |
| 1999 | system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.95% # attempts to use FU when none available |
| 2000 | system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.95% # attempts to use FU when none available |
| 2001 | system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.95% # attempts to use FU when none available |
| 2002 | system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.95% # attempts to use FU when none available |
| 2003 | system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.95% # attempts to use FU when none available |
| 2004 | system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.95% # attempts to use FU when none available |
| 2005 | system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.95% # attempts to use FU when none available |
| 2006 | system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.95% # attempts to use FU when none available |
| 2007 | system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.95% # attempts to use FU when none available |
| 2008 | system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.95% # attempts to use FU when none available |
| 2009 | system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.95% # attempts to use FU when none available |
| 2010 | system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.95% # attempts to use FU when none available |
| 2011 | system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.95% # attempts to use FU when none available |
| 2012 | system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.95% # attempts to use FU when none available |
| 2013 | system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.95% # attempts to use FU when none available |
| 2014 | system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.95% # attempts to use FU when none available |
| 2015 | system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.95% # attempts to use FU when none available |
| 2016 | system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.95% # attempts to use FU when none available |
| 2017 | system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.95% # attempts to use FU when none available |
| 2018 | system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.95% # attempts to use FU when none available |
| 2019 | system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.95% # attempts to use FU when none available |
| 2020 | system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.95% # attempts to use FU when none available |
| 2021 | system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.95% # attempts to use FU when none available |
| 2022 | system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.95% # attempts to use FU when none available |
| 2023 | system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.95% # attempts to use FU when none available |
| 2024 | system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.95% # attempts to use FU when none available |
| 2025 | system.cpu1.iq.fu_full::MemRead 535211 46.35% 55.30% # attempts to use FU when none available |
| 2026 | system.cpu1.iq.fu_full::MemWrite 516097 44.70% 100.00% # attempts to use FU when none available |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 2027 | system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available |
| 2028 | system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2029 | system.cpu1.iq.FU_type_0::No_OpClass 138 0.00% 0.00% # Type of FU issued |
| 2030 | system.cpu1.iq.FU_type_0::IntAlu 52538123 66.77% 66.77% # Type of FU issued |
| 2031 | system.cpu1.iq.FU_type_0::IntMult 58820 0.07% 66.85% # Type of FU issued |
| 2032 | system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.85% # Type of FU issued |
| 2033 | system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.85% # Type of FU issued |
| 2034 | system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.85% # Type of FU issued |
| 2035 | system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.85% # Type of FU issued |
| 2036 | system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.85% # Type of FU issued |
| 2037 | system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.85% # Type of FU issued |
| 2038 | system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.85% # Type of FU issued |
| 2039 | system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.85% # Type of FU issued |
| 2040 | system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.85% # Type of FU issued |
| 2041 | system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.85% # Type of FU issued |
| 2042 | system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.85% # Type of FU issued |
| 2043 | system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.85% # Type of FU issued |
| 2044 | system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.85% # Type of FU issued |
| 2045 | system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.85% # Type of FU issued |
| 2046 | system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.85% # Type of FU issued |
| 2047 | system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.85% # Type of FU issued |
| 2048 | system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.85% # Type of FU issued |
| 2049 | system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.85% # Type of FU issued |
| 2050 | system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.85% # Type of FU issued |
| 2051 | system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.85% # Type of FU issued |
| 2052 | system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.85% # Type of FU issued |
| 2053 | system.cpu1.iq.FU_type_0::SimdFloatCvt 1 0.00% 66.85% # Type of FU issued |
| 2054 | system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.85% # Type of FU issued |
| 2055 | system.cpu1.iq.FU_type_0::SimdFloatMisc 4114 0.01% 66.85% # Type of FU issued |
| 2056 | system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.85% # Type of FU issued |
| 2057 | system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 66.85% # Type of FU issued |
| 2058 | system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.85% # Type of FU issued |
| 2059 | system.cpu1.iq.FU_type_0::MemRead 14784683 18.79% 85.64% # Type of FU issued |
| 2060 | system.cpu1.iq.FU_type_0::MemWrite 11299162 14.36% 100.00% # Type of FU issued |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 2061 | system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued |
| 2062 | system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2063 | system.cpu1.iq.FU_type_0::total 78685046 # Type of FU issued |
| 2064 | system.cpu1.iq.rate 0.733711 # Inst issue rate |
| 2065 | system.cpu1.iq.fu_busy_cnt 1154609 # FU busy when requested |
| 2066 | system.cpu1.iq.fu_busy_rate 0.014674 # FU busy rate (busy events/executed inst) |
| 2067 | system.cpu1.iq.int_inst_queue_reads 263236691 # Number of integer instruction queue reads |
| 2068 | system.cpu1.iq.int_inst_queue_writes 93395575 # Number of integer instruction queue writes |
| 2069 | system.cpu1.iq.int_inst_queue_wakeup_accesses 76291766 # Number of integer instruction queue wakeup accesses |
| 2070 | system.cpu1.iq.fp_inst_queue_reads 13765 # Number of floating instruction queue reads |
| 2071 | system.cpu1.iq.fp_inst_queue_writes 7276 # Number of floating instruction queue writes |
| 2072 | system.cpu1.iq.fp_inst_queue_wakeup_accesses 6039 # Number of floating instruction queue wakeup accesses |
| 2073 | system.cpu1.iq.int_alu_accesses 79832108 # Number of integer alu accesses |
| 2074 | system.cpu1.iq.fp_alu_accesses 7409 # Number of floating point alu accesses |
| 2075 | system.cpu1.iew.lsq.thread0.forwLoads 367192 # Number of loads that had data forwarded from stores |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 2076 | system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2077 | system.cpu1.iew.lsq.thread0.squashedLoads 2204039 # Number of loads squashed |
| 2078 | system.cpu1.iew.lsq.thread0.ignoredResponses 2671 # Number of memory responses ignored because the instruction is squashed |
| 2079 | system.cpu1.iew.lsq.thread0.memOrderViolation 53511 # Number of memory ordering violations |
| 2080 | system.cpu1.iew.lsq.thread0.squashedStores 1150974 # Number of stores squashed |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 2081 | system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address |
| 2082 | system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2083 | system.cpu1.iew.lsq.thread0.rescheduledLoads 193750 # Number of loads that were rescheduled |
| 2084 | system.cpu1.iew.lsq.thread0.cacheBlocked 155367 # Number of times an access to memory failed due to the cache being blocked |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 2085 | system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2086 | system.cpu1.iew.iewSquashCycles 1465635 # Number of cycles IEW is squashing |
| 2087 | system.cpu1.iew.iewBlockCycles 4317272 # Number of cycles IEW is blocking |
| 2088 | system.cpu1.iew.iewUnblockCycles 2160865 # Number of cycles IEW is unblocking |
| 2089 | system.cpu1.iew.iewDispatchedInsts 83369977 # Number of instructions dispatched to IQ |
| 2090 | system.cpu1.iew.iewDispSquashedInsts 136369 # Number of squashed instructions skipped by dispatch |
| 2091 | system.cpu1.iew.iewDispLoadInsts 15196570 # Number of dispatched load instructions |
| 2092 | system.cpu1.iew.iewDispStoreInsts 11856807 # Number of dispatched store instructions |
| 2093 | system.cpu1.iew.iewDispNonSpecInsts 585220 # Number of dispatched non-speculative instructions |
| 2094 | system.cpu1.iew.iewIQFullEvents 46964 # Number of times the IQ has become full, causing a stall |
| 2095 | system.cpu1.iew.iewLSQFullEvents 2101356 # Number of times the LSQ has become full, causing a stall |
| 2096 | system.cpu1.iew.memOrderViolationEvents 53511 # Number of memory order violations |
| 2097 | system.cpu1.iew.predictedTakenIncorrect 256264 # Number of branches that were predicted taken incorrectly |
| 2098 | system.cpu1.iew.predictedNotTakenIncorrect 221755 # Number of branches that were predicted not taken incorrectly |
| 2099 | system.cpu1.iew.branchMispredicts 478019 # Number of branch mispredicts detected at execute |
| 2100 | system.cpu1.iew.iewExecutedInsts 78073190 # Number of executed instructions |
| 2101 | system.cpu1.iew.iewExecLoadInsts 14542904 # Number of load instructions executed |
| 2102 | system.cpu1.iew.iewExecSquashedInsts 552934 # Number of squashed instructions skipped in execute |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 2103 | system.cpu1.iew.exec_swp 0 # number of swp insts executed |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2104 | system.cpu1.iew.exec_nop 141457 # number of nop insts executed |
| 2105 | system.cpu1.iew.exec_refs 25733696 # number of memory reference insts executed |
| 2106 | system.cpu1.iew.exec_branches 14521478 # Number of branches executed |
| 2107 | system.cpu1.iew.exec_stores 11190792 # Number of stores executed |
| 2108 | system.cpu1.iew.exec_rate 0.728006 # Inst execution rate |
| 2109 | system.cpu1.iew.wb_sent 77444186 # cumulative count of insts sent to commit |
| 2110 | system.cpu1.iew.wb_count 76297805 # cumulative count of insts written-back |
| 2111 | system.cpu1.iew.wb_producers 39935797 # num instructions producing a value |
| 2112 | system.cpu1.iew.wb_consumers 69997959 # num instructions consuming a value |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 2113 | system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2114 | system.cpu1.iew.wb_rate 0.711451 # insts written-back per cycle |
| 2115 | system.cpu1.iew.wb_fanout 0.570528 # average fanout of values written-back |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 2116 | system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2117 | system.cpu1.commit.commitSquashedInsts 11451015 # The number of squashed insts skipped by commit |
| 2118 | system.cpu1.commit.commitNonSpecStalls 1054911 # The number of times commit has been forced to stall to communicate backwards |
| 2119 | system.cpu1.commit.branchMispredicts 403289 # The number of times a branch was mispredicted |
| 2120 | system.cpu1.commit.committed_per_cycle::samples 102066180 # Number of insts commited each cycle |
| 2121 | system.cpu1.commit.committed_per_cycle::mean 0.704508 # Number of insts commited each cycle |
| 2122 | system.cpu1.commit.committed_per_cycle::stdev 1.588054 # Number of insts commited each cycle |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 2123 | system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2124 | system.cpu1.commit.committed_per_cycle::0 73979517 72.48% 72.48% # Number of insts commited each cycle |
| 2125 | system.cpu1.commit.committed_per_cycle::1 12597540 12.34% 84.82% # Number of insts commited each cycle |
| 2126 | system.cpu1.commit.committed_per_cycle::2 6450417 6.32% 91.14% # Number of insts commited each cycle |
| 2127 | system.cpu1.commit.committed_per_cycle::3 2677104 2.62% 93.77% # Number of insts commited each cycle |
| 2128 | system.cpu1.commit.committed_per_cycle::4 1410201 1.38% 95.15% # Number of insts commited each cycle |
| 2129 | system.cpu1.commit.committed_per_cycle::5 931945 0.91% 96.06% # Number of insts commited each cycle |
| 2130 | system.cpu1.commit.committed_per_cycle::6 1826334 1.79% 97.85% # Number of insts commited each cycle |
| 2131 | system.cpu1.commit.committed_per_cycle::7 426802 0.42% 98.27% # Number of insts commited each cycle |
| 2132 | system.cpu1.commit.committed_per_cycle::8 1766320 1.73% 100.00% # Number of insts commited each cycle |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 2133 | system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle |
| 2134 | system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle |
| 2135 | system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2136 | system.cpu1.commit.committed_per_cycle::total 102066180 # Number of insts commited each cycle |
| 2137 | system.cpu1.commit.committedInsts 59233366 # Number of instructions committed |
| 2138 | system.cpu1.commit.committedOps 71906393 # Number of ops (including micro ops) committed |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 2139 | system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2140 | system.cpu1.commit.refs 23698364 # Number of memory references committed |
| 2141 | system.cpu1.commit.loads 12992531 # Number of loads committed |
| 2142 | system.cpu1.commit.membars 441834 # Number of memory barriers committed |
| 2143 | system.cpu1.commit.branches 13745002 # Number of branches committed |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 2144 | system.cpu1.commit.fp_insts 5965 # Number of committed floating point instructions. |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2145 | system.cpu1.commit.int_insts 63017798 # Number of committed integer instructions. |
| 2146 | system.cpu1.commit.function_calls 2684230 # Number of function calls committed. |
Andreas Hansson | 57e5401 | 2014-05-09 18:58:50 -0400 | [diff] [blame] | 2147 | system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2148 | system.cpu1.commit.op_class_0::IntAlu 48146836 66.96% 66.96% # Class of committed instruction |
| 2149 | system.cpu1.commit.op_class_0::IntMult 57080 0.08% 67.04% # Class of committed instruction |
| 2150 | system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.04% # Class of committed instruction |
| 2151 | system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.04% # Class of committed instruction |
| 2152 | system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.04% # Class of committed instruction |
| 2153 | system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.04% # Class of committed instruction |
| 2154 | system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.04% # Class of committed instruction |
| 2155 | system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.04% # Class of committed instruction |
| 2156 | system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.04% # Class of committed instruction |
| 2157 | system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.04% # Class of committed instruction |
| 2158 | system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.04% # Class of committed instruction |
| 2159 | system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.04% # Class of committed instruction |
| 2160 | system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.04% # Class of committed instruction |
| 2161 | system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.04% # Class of committed instruction |
| 2162 | system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.04% # Class of committed instruction |
| 2163 | system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.04% # Class of committed instruction |
| 2164 | system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.04% # Class of committed instruction |
| 2165 | system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.04% # Class of committed instruction |
| 2166 | system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.04% # Class of committed instruction |
| 2167 | system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.04% # Class of committed instruction |
| 2168 | system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.04% # Class of committed instruction |
| 2169 | system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.04% # Class of committed instruction |
| 2170 | system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.04% # Class of committed instruction |
| 2171 | system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.04% # Class of committed instruction |
| 2172 | system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.04% # Class of committed instruction |
| 2173 | system.cpu1.commit.op_class_0::SimdFloatMisc 4113 0.01% 67.04% # Class of committed instruction |
| 2174 | system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.04% # Class of committed instruction |
| 2175 | system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.04% # Class of committed instruction |
| 2176 | system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.04% # Class of committed instruction |
| 2177 | system.cpu1.commit.op_class_0::MemRead 12992531 18.07% 85.11% # Class of committed instruction |
| 2178 | system.cpu1.commit.op_class_0::MemWrite 10705833 14.89% 100.00% # Class of committed instruction |
Andreas Hansson | 57e5401 | 2014-05-09 18:58:50 -0400 | [diff] [blame] | 2179 | system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction |
| 2180 | system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2181 | system.cpu1.commit.op_class_0::total 71906393 # Class of committed instruction |
| 2182 | system.cpu1.commit.bw_lim_events 1766320 # number cycles where commit BW limit reached |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 2183 | system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2184 | system.cpu1.rob.rob_reads 171177235 # The number of ROB reads |
| 2185 | system.cpu1.rob.rob_writes 169283950 # The number of ROB writes |
| 2186 | system.cpu1.timesIdled 392418 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 2187 | system.cpu1.idleCycles 2611636 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 2188 | system.cpu1.quiesceCycles 2951410112 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt |
| 2189 | system.cpu1.committedInsts 59150362 # Number of Instructions Simulated |
| 2190 | system.cpu1.committedOps 71823389 # Number of Ops (including micro ops) Simulated |
| 2191 | system.cpu1.cpi 1.813049 # CPI: Cycles Per Instruction |
| 2192 | system.cpu1.cpi_total 1.813049 # CPI: Total CPI of All Threads |
| 2193 | system.cpu1.ipc 0.551557 # IPC: Instructions Per Cycle |
| 2194 | system.cpu1.ipc_total 0.551557 # IPC: Total IPC of All Threads |
| 2195 | system.cpu1.int_regfile_reads 84951910 # number of integer regfile reads |
| 2196 | system.cpu1.int_regfile_writes 48574213 # number of integer regfile writes |
| 2197 | system.cpu1.fp_regfile_reads 16611 # number of floating regfile reads |
| 2198 | system.cpu1.fp_regfile_writes 13102 # number of floating regfile writes |
| 2199 | system.cpu1.cc_regfile_reads 275725718 # number of cc regfile reads |
| 2200 | system.cpu1.cc_regfile_writes 28996859 # number of cc regfile writes |
| 2201 | system.cpu1.misc_regfile_reads 192674093 # number of misc regfile reads |
| 2202 | system.cpu1.misc_regfile_writes 799402 # number of misc regfile writes |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 2203 | system.iocache.tags.replacements 36423 # number of replacements |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2204 | system.iocache.tags.tagsinuse 0.982061 # Cycle average of tags in use |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 2205 | system.iocache.tags.total_refs 16 # Total number of references to valid blocks. |
| 2206 | system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. |
| 2207 | system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks. |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2208 | system.iocache.tags.warmup_cycle 234012764000 # Cycle when the warmup percentage was hit. |
| 2209 | system.iocache.tags.occ_blocks::realview.ide 0.982061 # Average occupied blocks per requestor |
| 2210 | system.iocache.tags.occ_percent::realview.ide 0.061379 # Average percentage of cache occupancy |
| 2211 | system.iocache.tags.occ_percent::total 0.061379 # Average percentage of cache occupancy |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 2212 | system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id |
| 2213 | system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id |
| 2214 | system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2215 | system.iocache.tags.tag_accesses 328305 # Number of tag accesses |
| 2216 | system.iocache.tags.data_accesses 328305 # Number of data accesses |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 2217 | system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits |
| 2218 | system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits |
| 2219 | system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses |
| 2220 | system.iocache.ReadReq_misses::total 249 # number of ReadReq misses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2221 | system.iocache.WriteInvalidateReq_misses::realview.ide 8 # number of WriteInvalidateReq misses |
| 2222 | system.iocache.WriteInvalidateReq_misses::total 8 # number of WriteInvalidateReq misses |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 2223 | system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses |
| 2224 | system.iocache.demand_misses::total 249 # number of demand (read+write) misses |
| 2225 | system.iocache.overall_misses::realview.ide 249 # number of overall misses |
| 2226 | system.iocache.overall_misses::total 249 # number of overall misses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2227 | system.iocache.ReadReq_miss_latency::realview.ide 29662377 # number of ReadReq miss cycles |
| 2228 | system.iocache.ReadReq_miss_latency::total 29662377 # number of ReadReq miss cycles |
| 2229 | system.iocache.demand_miss_latency::realview.ide 29662377 # number of demand (read+write) miss cycles |
| 2230 | system.iocache.demand_miss_latency::total 29662377 # number of demand (read+write) miss cycles |
| 2231 | system.iocache.overall_miss_latency::realview.ide 29662377 # number of overall miss cycles |
| 2232 | system.iocache.overall_miss_latency::total 29662377 # number of overall miss cycles |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 2233 | system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) |
| 2234 | system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2235 | system.iocache.WriteInvalidateReq_accesses::realview.ide 36232 # number of WriteInvalidateReq accesses(hits+misses) |
| 2236 | system.iocache.WriteInvalidateReq_accesses::total 36232 # number of WriteInvalidateReq accesses(hits+misses) |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 2237 | system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses |
| 2238 | system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses |
| 2239 | system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses |
| 2240 | system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses |
| 2241 | system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses |
| 2242 | system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2243 | system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000221 # miss rate for WriteInvalidateReq accesses |
| 2244 | system.iocache.WriteInvalidateReq_miss_rate::total 0.000221 # miss rate for WriteInvalidateReq accesses |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 2245 | system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses |
| 2246 | system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses |
| 2247 | system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses |
| 2248 | system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2249 | system.iocache.ReadReq_avg_miss_latency::realview.ide 119126.012048 # average ReadReq miss latency |
| 2250 | system.iocache.ReadReq_avg_miss_latency::total 119126.012048 # average ReadReq miss latency |
| 2251 | system.iocache.demand_avg_miss_latency::realview.ide 119126.012048 # average overall miss latency |
| 2252 | system.iocache.demand_avg_miss_latency::total 119126.012048 # average overall miss latency |
| 2253 | system.iocache.overall_avg_miss_latency::realview.ide 119126.012048 # average overall miss latency |
| 2254 | system.iocache.overall_avg_miss_latency::total 119126.012048 # average overall miss latency |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 2255 | system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 2256 | system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2257 | system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 2258 | system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 2259 | system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 2260 | system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 2261 | system.iocache.fast_writes 36224 # number of fast writes performed |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 2262 | system.iocache.cache_copies 0 # number of cache copies performed |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 2263 | system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses |
| 2264 | system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses |
| 2265 | system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses |
| 2266 | system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses |
| 2267 | system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses |
| 2268 | system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2269 | system.iocache.ReadReq_mshr_miss_latency::realview.ide 16713377 # number of ReadReq MSHR miss cycles |
| 2270 | system.iocache.ReadReq_mshr_miss_latency::total 16713377 # number of ReadReq MSHR miss cycles |
| 2271 | system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2228741309 # number of WriteInvalidateReq MSHR miss cycles |
| 2272 | system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2228741309 # number of WriteInvalidateReq MSHR miss cycles |
| 2273 | system.iocache.demand_mshr_miss_latency::realview.ide 16713377 # number of demand (read+write) MSHR miss cycles |
| 2274 | system.iocache.demand_mshr_miss_latency::total 16713377 # number of demand (read+write) MSHR miss cycles |
| 2275 | system.iocache.overall_mshr_miss_latency::realview.ide 16713377 # number of overall MSHR miss cycles |
| 2276 | system.iocache.overall_mshr_miss_latency::total 16713377 # number of overall MSHR miss cycles |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 2277 | system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses |
| 2278 | system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 2279 | system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses |
| 2280 | system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses |
| 2281 | system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses |
| 2282 | system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2283 | system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67121.995984 # average ReadReq mshr miss latency |
| 2284 | system.iocache.ReadReq_avg_mshr_miss_latency::total 67121.995984 # average ReadReq mshr miss latency |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 2285 | system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency |
| 2286 | system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency |
Ali Saidi | ae82551 | 2014-11-03 10:14:42 -0600 | [diff] [blame^] | 2287 | system.iocache.demand_avg_mshr_miss_latency::realview.ide 67121.995984 # average overall mshr miss latency |
| 2288 | system.iocache.demand_avg_mshr_miss_latency::total 67121.995984 # average overall mshr miss latency |
| 2289 | system.iocache.overall_avg_mshr_miss_latency::realview.ide 67121.995984 # average overall mshr miss latency |
| 2290 | system.iocache.overall_avg_mshr_miss_latency::total 67121.995984 # average overall mshr miss latency |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 2291 | system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2292 | system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
Ali Saidi | 93c0307 | 2014-10-29 23:18:29 -0500 | [diff] [blame] | 2293 | system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 2294 | system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 2295 | system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |
| 2296 | |
| 2297 | ---------- End Simulation Statistics ---------- |