blob: 99f08345051cae507acf2b263c5d2c40783dee08 [file] [log] [blame]
Nathan Binkert35147172007-05-27 19:21:17 -07001# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Gabe Black
28
Gabe Blackbc4d15d2006-11-14 15:14:27 -050029from m5.params import *
30from m5.proxy import *
Ali Saidi1694c652007-03-03 19:02:31 -050031from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
Gabe Blackcd5b33b2006-11-16 12:34:10 -050032from Platform import Platform
Nathan Binkert00df9012008-06-17 20:29:06 -070033from Terminal import Terminal
34from Uart import Uart8250
Gabe Blackbc4d15d2006-11-14 15:14:27 -050035
Ali Saidi7933aad2007-01-09 22:16:49 -050036
37class MmDisk(BasicPioDevice):
38 type = 'MmDisk'
Andreas Sandbergc0ab5272012-11-02 11:32:01 -050039 cxx_header = "dev/sparc/mm_disk.hh"
Ali Saidi7933aad2007-01-09 22:16:49 -050040 image = Param.DiskImage("Disk Image")
41 pio_addr = 0x1F40000000
42
Ali Saidi3af36102007-01-21 18:04:40 -050043class DumbTOD(BasicPioDevice):
44 type = 'DumbTOD'
Andreas Sandbergc0ab5272012-11-02 11:32:01 -050045 cxx_header = "dev/sparc/dtod.hh"
Ali Saidi3af36102007-01-21 18:04:40 -050046 time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
47 pio_addr = 0xfff0c1fff8
48
Ali Saidi1694c652007-03-03 19:02:31 -050049class Iob(PioDevice):
50 type = 'Iob'
Andreas Sandbergc0ab5272012-11-02 11:32:01 -050051 cxx_header = "dev/sparc/iob.hh"
Gabe Blackd3683442011-10-04 02:26:03 -070052 platform = Param.Platform(Parent.any, "Platform this device is part of.")
Andreas Hansson70e99e02012-08-21 05:50:03 -040053 pio_latency = Param.Latency('1ns', "Programed IO latency")
Ali Saidi1694c652007-03-03 19:02:31 -050054
Ali Saidi3af36102007-01-21 18:04:40 -050055
Gabe Blackbc4d15d2006-11-14 15:14:27 -050056class T1000(Platform):
57 type = 'T1000'
Andreas Sandbergc0ab5272012-11-02 11:32:01 -050058 cxx_header = "dev/sparc/t1000.hh"
Gabe Blackbc4d15d2006-11-14 15:14:27 -050059 system = Param.System(Parent.any, "system")
60
Ali Saidi5c7192d2007-01-31 18:32:27 -050061 fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
62 #warn_access="Accessing Clock Unit -- Unimplemented!")
Gabe Blackbc4d15d2006-11-14 15:14:27 -050063
Ali Saidi92c5a5c2006-12-04 00:54:40 -050064 fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
Ali Saidi5c7192d2007-01-31 18:32:27 -050065 ret_data64=0x0000000000000000, update_data=False)
66 #warn_access="Accessing Memory Banks -- Unimplemented!")
Ali Saidi92c5a5c2006-12-04 00:54:40 -050067
Ali Saidi5c7192d2007-01-31 18:32:27 -050068 fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
69 #warn_access="Accessing JBI -- Unimplemented!")
Ali Saidi92c5a5c2006-12-04 00:54:40 -050070
71 fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
Ali Saidi5c7192d2007-01-31 18:32:27 -050072 ret_data64=0x0000000000000001, update_data=True)
73 #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
Ali Saidi92c5a5c2006-12-04 00:54:40 -050074
75 fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
Ali Saidi5c7192d2007-01-31 18:32:27 -050076 ret_data64=0x0000000000000001, update_data=True)
77 #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
Ali Saidi92c5a5c2006-12-04 00:54:40 -050078
79 fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
Ali Saidi5c7192d2007-01-31 18:32:27 -050080 ret_data64=0x0000000000000001, update_data=True)
81 #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
Ali Saidi92c5a5c2006-12-04 00:54:40 -050082
83 fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
Ali Saidi5c7192d2007-01-31 18:32:27 -050084 ret_data64=0x0000000000000001, update_data=True)
85 #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
Ali Saidi92c5a5c2006-12-04 00:54:40 -050086
Ali Saidied22eb72006-12-07 18:50:33 -050087 fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
Ali Saidi5c7192d2007-01-31 18:32:27 -050088 ret_data64=0x0000000000000000, update_data=True)
89 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
Ali Saidied22eb72006-12-07 18:50:33 -050090
91 fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
Ali Saidi5c7192d2007-01-31 18:32:27 -050092 ret_data64=0x0000000000000000, update_data=True)
93 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
Ali Saidied22eb72006-12-07 18:50:33 -050094
95 fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
Ali Saidi5c7192d2007-01-31 18:32:27 -050096 ret_data64=0x0000000000000000, update_data=True)
97 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
Ali Saidied22eb72006-12-07 18:50:33 -050098
99 fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
Ali Saidi5c7192d2007-01-31 18:32:27 -0500100 ret_data64=0x0000000000000000, update_data=True)
101 #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
Ali Saidied22eb72006-12-07 18:50:33 -0500102
Ali Saidi5c7192d2007-01-31 18:32:27 -0500103 fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
104 #warn_access="Accessing SSI -- Unimplemented!")
Ali Saidi92c5a5c2006-12-04 00:54:40 -0500105
Nathan Binkert00df9012008-06-17 20:29:06 -0700106 hterm = Terminal()
Ali Saidi92c5a5c2006-12-04 00:54:40 -0500107 hvuart = Uart8250(pio_addr=0xfff0c2c000)
Ali Saidi3af36102007-01-21 18:04:40 -0500108 htod = DumbTOD()
109
Nathan Binkert00df9012008-06-17 20:29:06 -0700110 pterm = Terminal()
Ali Saidi92c5a5c2006-12-04 00:54:40 -0500111 puart0 = Uart8250(pio_addr=0x1f10000000)
Gabe Blackbc4d15d2006-11-14 15:14:27 -0500112
Ali Saidi1694c652007-03-03 19:02:31 -0500113 iob = Iob()
114 # Attach I/O devices that are on chip
115 def attachOnChipIO(self, bus):
Andreas Hansson6cf9f182012-02-14 14:15:30 -0500116 self.iob.pio = bus.master
117 self.htod.pio = bus.master
Ali Saidi1694c652007-03-03 19:02:31 -0500118
119
Gabe Blackbc4d15d2006-11-14 15:14:27 -0500120 # Attach I/O devices to specified bus object. Can't do this
121 # earlier, since the bus object itself is typically defined at the
122 # System level.
123 def attachIO(self, bus):
Gabe Black205add52017-11-17 15:24:28 -0800124 self.hvuart.device = self.hterm
125 self.puart0.device = self.pterm
Andreas Hansson6cf9f182012-02-14 14:15:30 -0500126 self.fake_clk.pio = bus.master
127 self.fake_membnks.pio = bus.master
128 self.fake_l2_1.pio = bus.master
129 self.fake_l2_2.pio = bus.master
130 self.fake_l2_3.pio = bus.master
131 self.fake_l2_4.pio = bus.master
132 self.fake_l2esr_1.pio = bus.master
133 self.fake_l2esr_2.pio = bus.master
134 self.fake_l2esr_3.pio = bus.master
135 self.fake_l2esr_4.pio = bus.master
136 self.fake_ssi.pio = bus.master
137 self.fake_jbi.pio = bus.master
138 self.puart0.pio = bus.master
139 self.hvuart.pio = bus.master