Nathan Binkert | 3514717 | 2007-05-27 19:21:17 -0700 | [diff] [blame] | 1 | # Copyright (c) 2006-2007 The Regents of The University of Michigan |
| 2 | # All rights reserved. |
| 3 | # |
| 4 | # Redistribution and use in source and binary forms, with or without |
| 5 | # modification, are permitted provided that the following conditions are |
| 6 | # met: redistributions of source code must retain the above copyright |
| 7 | # notice, this list of conditions and the following disclaimer; |
| 8 | # redistributions in binary form must reproduce the above copyright |
| 9 | # notice, this list of conditions and the following disclaimer in the |
| 10 | # documentation and/or other materials provided with the distribution; |
| 11 | # neither the name of the copyright holders nor the names of its |
| 12 | # contributors may be used to endorse or promote products derived from |
| 13 | # this software without specific prior written permission. |
| 14 | # |
| 15 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 16 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 17 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 18 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 19 | # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 20 | # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 21 | # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 22 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 23 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 24 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 25 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | # |
| 27 | # Authors: Gabe Black |
| 28 | |
Gabe Black | bc4d15d | 2006-11-14 15:14:27 -0500 | [diff] [blame] | 29 | from m5.params import * |
| 30 | from m5.proxy import * |
Ali Saidi | 1694c65 | 2007-03-03 19:02:31 -0500 | [diff] [blame] | 31 | from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr |
Gabe Black | cd5b33b | 2006-11-16 12:34:10 -0500 | [diff] [blame] | 32 | from Platform import Platform |
Nathan Binkert | 00df901 | 2008-06-17 20:29:06 -0700 | [diff] [blame] | 33 | from Terminal import Terminal |
| 34 | from Uart import Uart8250 |
Gabe Black | bc4d15d | 2006-11-14 15:14:27 -0500 | [diff] [blame] | 35 | |
Ali Saidi | 7933aad | 2007-01-09 22:16:49 -0500 | [diff] [blame] | 36 | |
| 37 | class MmDisk(BasicPioDevice): |
| 38 | type = 'MmDisk' |
Andreas Sandberg | c0ab527 | 2012-11-02 11:32:01 -0500 | [diff] [blame] | 39 | cxx_header = "dev/sparc/mm_disk.hh" |
Ali Saidi | 7933aad | 2007-01-09 22:16:49 -0500 | [diff] [blame] | 40 | image = Param.DiskImage("Disk Image") |
| 41 | pio_addr = 0x1F40000000 |
| 42 | |
Ali Saidi | 3af3610 | 2007-01-21 18:04:40 -0500 | [diff] [blame] | 43 | class DumbTOD(BasicPioDevice): |
| 44 | type = 'DumbTOD' |
Andreas Sandberg | c0ab527 | 2012-11-02 11:32:01 -0500 | [diff] [blame] | 45 | cxx_header = "dev/sparc/dtod.hh" |
Ali Saidi | 3af3610 | 2007-01-21 18:04:40 -0500 | [diff] [blame] | 46 | time = Param.Time('01/01/2009', "System time to use ('Now' for real time)") |
| 47 | pio_addr = 0xfff0c1fff8 |
| 48 | |
Ali Saidi | 1694c65 | 2007-03-03 19:02:31 -0500 | [diff] [blame] | 49 | class Iob(PioDevice): |
| 50 | type = 'Iob' |
Andreas Sandberg | c0ab527 | 2012-11-02 11:32:01 -0500 | [diff] [blame] | 51 | cxx_header = "dev/sparc/iob.hh" |
Gabe Black | d368344 | 2011-10-04 02:26:03 -0700 | [diff] [blame] | 52 | platform = Param.Platform(Parent.any, "Platform this device is part of.") |
Andreas Hansson | 70e99e0 | 2012-08-21 05:50:03 -0400 | [diff] [blame] | 53 | pio_latency = Param.Latency('1ns', "Programed IO latency") |
Ali Saidi | 1694c65 | 2007-03-03 19:02:31 -0500 | [diff] [blame] | 54 | |
Ali Saidi | 3af3610 | 2007-01-21 18:04:40 -0500 | [diff] [blame] | 55 | |
Gabe Black | bc4d15d | 2006-11-14 15:14:27 -0500 | [diff] [blame] | 56 | class T1000(Platform): |
| 57 | type = 'T1000' |
Andreas Sandberg | c0ab527 | 2012-11-02 11:32:01 -0500 | [diff] [blame] | 58 | cxx_header = "dev/sparc/t1000.hh" |
Gabe Black | bc4d15d | 2006-11-14 15:14:27 -0500 | [diff] [blame] | 59 | system = Param.System(Parent.any, "system") |
| 60 | |
Ali Saidi | 5c7192d | 2007-01-31 18:32:27 -0500 | [diff] [blame] | 61 | fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000) |
| 62 | #warn_access="Accessing Clock Unit -- Unimplemented!") |
Gabe Black | bc4d15d | 2006-11-14 15:14:27 -0500 | [diff] [blame] | 63 | |
Ali Saidi | 92c5a5c | 2006-12-04 00:54:40 -0500 | [diff] [blame] | 64 | fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, |
Ali Saidi | 5c7192d | 2007-01-31 18:32:27 -0500 | [diff] [blame] | 65 | ret_data64=0x0000000000000000, update_data=False) |
| 66 | #warn_access="Accessing Memory Banks -- Unimplemented!") |
Ali Saidi | 92c5a5c | 2006-12-04 00:54:40 -0500 | [diff] [blame] | 67 | |
Ali Saidi | 5c7192d | 2007-01-31 18:32:27 -0500 | [diff] [blame] | 68 | fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000) |
| 69 | #warn_access="Accessing JBI -- Unimplemented!") |
Ali Saidi | 92c5a5c | 2006-12-04 00:54:40 -0500 | [diff] [blame] | 70 | |
| 71 | fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, |
Ali Saidi | 5c7192d | 2007-01-31 18:32:27 -0500 | [diff] [blame] | 72 | ret_data64=0x0000000000000001, update_data=True) |
| 73 | #warn_access="Accessing L2 Cache Banks -- Unimplemented!") |
Ali Saidi | 92c5a5c | 2006-12-04 00:54:40 -0500 | [diff] [blame] | 74 | |
| 75 | fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, |
Ali Saidi | 5c7192d | 2007-01-31 18:32:27 -0500 | [diff] [blame] | 76 | ret_data64=0x0000000000000001, update_data=True) |
| 77 | #warn_access="Accessing L2 Cache Banks -- Unimplemented!") |
Ali Saidi | 92c5a5c | 2006-12-04 00:54:40 -0500 | [diff] [blame] | 78 | |
| 79 | fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, |
Ali Saidi | 5c7192d | 2007-01-31 18:32:27 -0500 | [diff] [blame] | 80 | ret_data64=0x0000000000000001, update_data=True) |
| 81 | #warn_access="Accessing L2 Cache Banks -- Unimplemented!") |
Ali Saidi | 92c5a5c | 2006-12-04 00:54:40 -0500 | [diff] [blame] | 82 | |
| 83 | fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, |
Ali Saidi | 5c7192d | 2007-01-31 18:32:27 -0500 | [diff] [blame] | 84 | ret_data64=0x0000000000000001, update_data=True) |
| 85 | #warn_access="Accessing L2 Cache Banks -- Unimplemented!") |
Ali Saidi | 92c5a5c | 2006-12-04 00:54:40 -0500 | [diff] [blame] | 86 | |
Ali Saidi | ed22eb7 | 2006-12-07 18:50:33 -0500 | [diff] [blame] | 87 | fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8, |
Ali Saidi | 5c7192d | 2007-01-31 18:32:27 -0500 | [diff] [blame] | 88 | ret_data64=0x0000000000000000, update_data=True) |
| 89 | #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") |
Ali Saidi | ed22eb7 | 2006-12-07 18:50:33 -0500 | [diff] [blame] | 90 | |
| 91 | fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8, |
Ali Saidi | 5c7192d | 2007-01-31 18:32:27 -0500 | [diff] [blame] | 92 | ret_data64=0x0000000000000000, update_data=True) |
| 93 | #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") |
Ali Saidi | ed22eb7 | 2006-12-07 18:50:33 -0500 | [diff] [blame] | 94 | |
| 95 | fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8, |
Ali Saidi | 5c7192d | 2007-01-31 18:32:27 -0500 | [diff] [blame] | 96 | ret_data64=0x0000000000000000, update_data=True) |
| 97 | #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") |
Ali Saidi | ed22eb7 | 2006-12-07 18:50:33 -0500 | [diff] [blame] | 98 | |
| 99 | fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8, |
Ali Saidi | 5c7192d | 2007-01-31 18:32:27 -0500 | [diff] [blame] | 100 | ret_data64=0x0000000000000000, update_data=True) |
| 101 | #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") |
Ali Saidi | ed22eb7 | 2006-12-07 18:50:33 -0500 | [diff] [blame] | 102 | |
Ali Saidi | 5c7192d | 2007-01-31 18:32:27 -0500 | [diff] [blame] | 103 | fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) |
| 104 | #warn_access="Accessing SSI -- Unimplemented!") |
Ali Saidi | 92c5a5c | 2006-12-04 00:54:40 -0500 | [diff] [blame] | 105 | |
Nathan Binkert | 00df901 | 2008-06-17 20:29:06 -0700 | [diff] [blame] | 106 | hterm = Terminal() |
Ali Saidi | 92c5a5c | 2006-12-04 00:54:40 -0500 | [diff] [blame] | 107 | hvuart = Uart8250(pio_addr=0xfff0c2c000) |
Ali Saidi | 3af3610 | 2007-01-21 18:04:40 -0500 | [diff] [blame] | 108 | htod = DumbTOD() |
| 109 | |
Nathan Binkert | 00df901 | 2008-06-17 20:29:06 -0700 | [diff] [blame] | 110 | pterm = Terminal() |
Ali Saidi | 92c5a5c | 2006-12-04 00:54:40 -0500 | [diff] [blame] | 111 | puart0 = Uart8250(pio_addr=0x1f10000000) |
Gabe Black | bc4d15d | 2006-11-14 15:14:27 -0500 | [diff] [blame] | 112 | |
Ali Saidi | 1694c65 | 2007-03-03 19:02:31 -0500 | [diff] [blame] | 113 | iob = Iob() |
| 114 | # Attach I/O devices that are on chip |
| 115 | def attachOnChipIO(self, bus): |
Andreas Hansson | 6cf9f18 | 2012-02-14 14:15:30 -0500 | [diff] [blame] | 116 | self.iob.pio = bus.master |
| 117 | self.htod.pio = bus.master |
Ali Saidi | 1694c65 | 2007-03-03 19:02:31 -0500 | [diff] [blame] | 118 | |
| 119 | |
Gabe Black | bc4d15d | 2006-11-14 15:14:27 -0500 | [diff] [blame] | 120 | # Attach I/O devices to specified bus object. Can't do this |
| 121 | # earlier, since the bus object itself is typically defined at the |
| 122 | # System level. |
| 123 | def attachIO(self, bus): |
Gabe Black | 205add5 | 2017-11-17 15:24:28 -0800 | [diff] [blame] | 124 | self.hvuart.device = self.hterm |
| 125 | self.puart0.device = self.pterm |
Andreas Hansson | 6cf9f18 | 2012-02-14 14:15:30 -0500 | [diff] [blame] | 126 | self.fake_clk.pio = bus.master |
| 127 | self.fake_membnks.pio = bus.master |
| 128 | self.fake_l2_1.pio = bus.master |
| 129 | self.fake_l2_2.pio = bus.master |
| 130 | self.fake_l2_3.pio = bus.master |
| 131 | self.fake_l2_4.pio = bus.master |
| 132 | self.fake_l2esr_1.pio = bus.master |
| 133 | self.fake_l2esr_2.pio = bus.master |
| 134 | self.fake_l2esr_3.pio = bus.master |
| 135 | self.fake_l2esr_4.pio = bus.master |
| 136 | self.fake_ssi.pio = bus.master |
| 137 | self.fake_jbi.pio = bus.master |
| 138 | self.puart0.pio = bus.master |
| 139 | self.hvuart.pio = bus.master |