Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem.head
--HG--
extra : convert_revision : 14ac24236ff65b7e489c1ce4b4e9a295966013b8
diff --git a/build_opts/ALPHA_SE b/build_opts/ALPHA_SE
index 3fedc22..a082717 100644
--- a/build_opts/ALPHA_SE
+++ b/build_opts/ALPHA_SE
@@ -1,2 +1,3 @@
FULL_SYSTEM = 0
SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 193d3a5..67a1e57 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -66,11 +66,7 @@
self.tsunami = BaseTsunami()
self.tsunami.attachIO(self.iobus)
self.tsunami.ide.pio = self.iobus.port
- self.tsunami.ide.dma = self.iobus.port
- self.tsunami.ide.config = self.iobus.port
self.tsunami.ethernet.pio = self.iobus.port
- self.tsunami.ethernet.dma = self.iobus.port
- self.tsunami.ethernet.config = self.iobus.port
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index 72e38ae..4f439b8 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -42,7 +42,6 @@
namespace AlphaISA
{
-
using namespace LittleEndianGuest;
// These enumerate all the registers for dependence tracking.
@@ -60,12 +59,14 @@
StaticInstPtr decodeInst(ExtMachInst);
+ // Alpha Does NOT have a delay slot
+ #define ISA_HAS_DELAY_SLOT 0
+
const Addr PageShift = 13;
const Addr PageBytes = ULL(1) << PageShift;
const Addr PageMask = ~(PageBytes - 1);
const Addr PageOffset = PageBytes - 1;
-
#if FULL_SYSTEM
////////////////////////////////////////////////////////////////////////
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index fd484e3..f85fc5b 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -47,6 +47,9 @@
StaticInstPtr decodeInst(ExtMachInst);
+ // MIPS DOES a delay slot
+ #define ISA_HAS_DELAY_SLOT 1
+
const Addr PageShift = 13;
const Addr PageBytes = ULL(1) << PageShift;
const Addr PageMask = ~(PageBytes - 1);
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 7f830eb..6d5aa42 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -57,6 +57,9 @@
//This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest;
+ // Alpha Does NOT have a delay slot
+ #define ISA_HAS_DELAY_SLOT 1
+
//TODO this needs to be a SPARC Noop
// Alpha UNOP (ldq_u r31,0(r0))
const MachInst NoopMachInst = 0x2ffe0000;
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 40611ab..3158aa9 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -291,18 +291,18 @@
/** Returns whether the instruction was predicted taken or not. */
bool predTaken()
-#if THE_ISA == ALPHA_ISA
- { return predPC != (PC + sizeof(MachInst)); }
-#else
+#if ISA_HAS_DELAY_SLOT
{ return predPC != (nextPC + sizeof(MachInst)); }
+#else
+ { return predPC != (PC + sizeof(MachInst)); }
#endif
/** Returns whether the instruction mispredicted. */
bool mispredicted()
-#if THE_ISA == ALPHA_ISA
- { return predPC != nextPC; }
-#else
+#if ISA_HAS_DELAY_SLOT
{ return predPC != nextNPC; }
+#else
+ { return predPC != nextPC; }
#endif
//
// Instruction types. Forward checks to StaticInst object.
diff --git a/src/cpu/o3/bpred_unit_impl.hh b/src/cpu/o3/bpred_unit_impl.hh
index e4e6566..477c8e4 100644
--- a/src/cpu/o3/bpred_unit_impl.hh
+++ b/src/cpu/o3/bpred_unit_impl.hh
@@ -29,6 +29,7 @@
*/
#include "arch/types.hh"
+#include "arch/isa_traits.hh"
#include "base/trace.hh"
#include "base/traceflags.hh"
#include "cpu/o3/bpred_unit.hh"
@@ -197,10 +198,10 @@
++BTBLookups;
if (inst->isCall()) {
-#if THE_ISA == ALPHA_ISA
- Addr ras_pc = PC + sizeof(MachInst); // Next PC
-#else
+#if ISA_HAS_DELAY_SLOT
Addr ras_pc = PC + (2 * sizeof(MachInst)); // Next Next PC
+#else
+ Addr ras_pc = PC + sizeof(MachInst); // Next PC
#endif
RAS[tid].push(ras_pc);
@@ -209,8 +210,8 @@
predict_record.wasCall = true;
DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %#x was a call"
- ", adding %#x to the RAS.\n",
- tid, inst->readPC(), ras_pc);
+ ", adding %#x to the RAS index: %i.\n",
+ tid, inst->readPC(), ras_pc, RAS[tid].topIdx());
}
if (BTB.valid(PC, tid)) {
@@ -283,7 +284,6 @@
RAS[tid].restore(pred_hist.front().RASIndex,
pred_hist.front().RASTarget);
-
} else if (pred_hist.front().wasCall) {
DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing speculative entry "
"added to the RAS.\n",tid);
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index f200f5f..34f487e 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -722,7 +722,7 @@
// then use one older sequence number.
InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
-#if THE_ISA != ALPHA_ISA
+#if ISA_HAS_DELAY_SLOT
InstSeqNum bdelay_done_seq_num;
bool squash_bdelay_slot;
@@ -748,7 +748,7 @@
if (fromIEW->includeSquashInst[tid] == true) {
squashed_inst--;
-#if THE_ISA != ALPHA_ISA
+#if ISA_HAS_DELAY_SLOT
bdelay_done_seq_num--;
#endif
}
@@ -756,13 +756,13 @@
// number as the youngest instruction in the ROB.
youngestSeqNum[tid] = squashed_inst;
-#if THE_ISA == ALPHA_ISA
- rob->squash(squashed_inst, tid);
- toIEW->commitInfo[tid].squashDelaySlot = true;
-#else
+#if ISA_HAS_DELAY_SLOT
rob->squash(bdelay_done_seq_num, tid);
toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
+#else
+ rob->squash(squashed_inst, tid);
+ toIEW->commitInfo[tid].squashDelaySlot = true;
#endif
changedROBNumEntries[tid] = true;
@@ -800,7 +800,7 @@
// Try to commit any instructions.
commitInsts();
} else {
-#if THE_ISA != ALPHA_ISA
+#if ISA_HAS_DELAY_SLOT
skidInsert();
#endif
}
@@ -906,11 +906,11 @@
}
PC[tid] = nextPC[tid];
-#if THE_ISA == ALPHA_ISA
- nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
-#else
+#if ISA_HAS_DELAY_SLOT
nextPC[tid] = nextNPC[tid];
nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
+#else
+ nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
#endif
#if FULL_SYSTEM
@@ -1115,10 +1115,7 @@
{
DPRINTF(Commit, "Getting instructions from Rename stage.\n");
-#if THE_ISA == ALPHA_ISA
- // Read any renamed instructions and place them into the ROB.
- int insts_to_process = std::min((int)renameWidth, fromRename->size);
-#else
+#if ISA_HAS_DELAY_SLOT
// Read any renamed instructions and place them into the ROB.
int insts_to_process = std::min((int)renameWidth,
(int)(fromRename->size + skidBuffer.size()));
@@ -1127,15 +1124,16 @@
DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
"SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
skidBuffer.size());
+#else
+ // Read any renamed instructions and place them into the ROB.
+ int insts_to_process = std::min((int)renameWidth, fromRename->size);
#endif
for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
DynInstPtr inst;
-#if THE_ISA == ALPHA_ISA
- inst = fromRename->insts[inst_num];
-#else
+#if ISA_HAS_DELAY_SLOT
// Get insts from skidBuffer or from Rename
if (skidBuffer.size() > 0) {
DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
@@ -1145,6 +1143,8 @@
DPRINTF(Commit, "Grabbing rename inst.\n");
inst = fromRename->insts[rename_idx++];
}
+#else
+ inst = fromRename->insts[inst_num];
#endif
int tid = inst->threadNumber;
@@ -1167,7 +1167,7 @@
}
}
-#if THE_ISA != ALPHA_ISA
+#if ISA_HAS_DELAY_SLOT
if (rename_idx < fromRename->size) {
DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index af03213..19ab7f4 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -181,7 +181,6 @@
params->activity),
globalSeqNum(1),
-
#if FULL_SYSTEM
system(params->system),
physmem(system->physmem),
@@ -322,6 +321,11 @@
lastActivatedCycle = -1;
+ // Give renameMap & rename stage access to the freeList;
+ //for (int i=0; i < numThreads; i++) {
+ //globalSeqNum[i] = 1;
+ //}
+
contextSwitch = false;
}
@@ -627,7 +631,7 @@
//Set PC/NPC/NNPC
setPC(src_tc->readPC(), tid);
setNextPC(src_tc->readNextPC(), tid);
-#if THE_ISA != ALPHA_ISA
+#if ISA_HAS_DELAY_SLOT
setNextNPC(src_tc->readNextNPC(), tid);
#endif
@@ -1197,7 +1201,7 @@
while (inst_it != end_it) {
assert(!instList.empty());
-#if THE_ISA != ALPHA_ISA
+#if ISA_HAS_DELAY_SLOT
if(!squash_delay_slot &&
delay_slot_seq_num >= (*inst_it)->seqNum) {
break;
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 7e18571..dcdcd1f 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -598,7 +598,7 @@
}
/** The global sequence number counter. */
- InstSeqNum globalSeqNum;
+ InstSeqNum globalSeqNum;//[Impl::MaxThreads];
/** Pointer to the checker, which can dynamically verify
* instruction results at run time. This can be set to NULL if it
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 1608453..80b6cc4 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -282,12 +282,7 @@
toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
toFetch->decodeInfo[tid].squash = true;
toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
-#if THE_ISA == ALPHA_ISA
- toFetch->decodeInfo[tid].branchTaken =
- inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
-
- InstSeqNum squash_seq_num = inst->seqNum;
-#else
+#if ISA_HAS_DELAY_SLOT
toFetch->decodeInfo[tid].branchTaken = inst->readNextNPC() !=
(inst->readNextPC() + sizeof(TheISA::MachInst));
@@ -295,6 +290,11 @@
squashAfterDelaySlot[tid] = false;
InstSeqNum squash_seq_num = bdelayDoneSeqNum[tid];
+#else
+ toFetch->decodeInfo[tid].branchTaken =
+ inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst));
+
+ InstSeqNum squash_seq_num = inst->seqNum;
#endif
// Might have to tell fetch to unblock.
@@ -317,7 +317,7 @@
// insts in them.
while (!insts[tid].empty()) {
-#if THE_ISA != ALPHA_ISA
+#if ISA_HAS_DELAY_SLOT
if (insts[tid].front()->seqNum <= squash_seq_num) {
DPRINTF(Decode, "[tid:%i]: Cannot remove incoming decode "
"instructions before delay slot [sn:%i]. %i insts"
@@ -331,7 +331,7 @@
while (!skidBuffer[tid].empty()) {
-#if THE_ISA != ALPHA_ISA
+#if ISA_HAS_DELAY_SLOT
if (skidBuffer[tid].front()->seqNum <= squash_seq_num) {
DPRINTF(Decode, "[tid:%i]: Cannot remove skidBuffer "
"instructions before delay slot [sn:%i]. %i insts"
@@ -765,7 +765,7 @@
// Might want to set some sort of boolean and just do
// a check at the end
-#if THE_ISA == ALPHA_ISA
+#if !ISA_HAS_DELAY_SLOT
squash(inst, inst->threadNumber);
inst->setPredTarg(inst->branchTarget());
break;
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 25be9d4..bf9a739 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -339,7 +339,7 @@
for (int tid = 0; tid < numThreads; tid++) {
PC[tid] = cpu->readPC(tid);
nextPC[tid] = cpu->readNextPC(tid);
-#if THE_ISA != ALPHA_ISA
+#if ISA_HAS_DELAY_SLOT
nextNPC[tid] = cpu->readNextNPC(tid);
#endif
}
@@ -429,7 +429,7 @@
stalls[i].commit = 0;
PC[i] = cpu->readPC(i);
nextPC[i] = cpu->readNextPC(i);
-#if THE_ISA != ALPHA_ISA
+#if ISA_HAS_DELAY_SLOT
nextNPC[i] = cpu->readNextNPC(i);
delaySlotInfo[i].branchSeqNum = -1;
delaySlotInfo[i].numInsts = 0;
@@ -492,22 +492,20 @@
bool predict_taken;
if (!inst->isControl()) {
-#if THE_ISA == ALPHA_ISA
- next_PC = next_PC + instSize;
- inst->setPredTarg(next_PC);
-#else
+#if ISA_HAS_DELAY_SLOT
Addr cur_PC = next_PC;
next_PC = cur_PC + instSize; //next_NPC;
next_NPC = cur_PC + (2 * instSize);//next_NPC + instSize;
inst->setPredTarg(next_NPC);
+#else
+ next_PC = next_PC + instSize;
+ inst->setPredTarg(next_PC);
#endif
return false;
}
int tid = inst->threadNumber;
-#if THE_ISA == ALPHA_ISA
- predict_taken = branchPred.predict(inst, next_PC, tid);
-#else
+#if ISA_HAS_DELAY_SLOT
Addr pred_PC = next_PC;
predict_taken = branchPred.predict(inst, pred_PC, tid);
@@ -539,6 +537,8 @@
next_NPC = next_NPC + instSize;
}
+#else
+ predict_taken = branchPred.predict(inst, next_PC, tid);
#endif
++fetchedBranches;
@@ -692,7 +692,7 @@
doSquash(new_PC, tid);
-#if THE_ISA != ALPHA_ISA
+#if ISA_HAS_DELAY_SLOT
if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
delaySlotInfo[tid].numInsts = 0;
delaySlotInfo[tid].targetAddr = 0;
@@ -780,10 +780,7 @@
doSquash(new_PC, tid);
-#if THE_ISA == ALPHA_ISA
- // Tell the CPU to remove any instructions that are not in the ROB.
- cpu->removeInstsNotInROB(tid, true, 0);
-#else
+#if ISA_HAS_DELAY_SLOT
if (seq_num <= delaySlotInfo[tid].branchSeqNum) {
delaySlotInfo[tid].numInsts = 0;
delaySlotInfo[tid].targetAddr = 0;
@@ -792,6 +789,9 @@
// Tell the CPU to remove any instructions that are not in the ROB.
cpu->removeInstsNotInROB(tid, squash_delay_slot, seq_num);
+#else
+ // Tell the CPU to remove any instructions that are not in the ROB.
+ cpu->removeInstsNotInROB(tid, true, 0);
#endif
}
@@ -901,10 +901,10 @@
DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
"from commit.\n",tid);
-#if THE_ISA == ALPHA_ISA
- InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
+#if ISA_HAS_DELAY_SLOT
+ InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
#else
- InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
+ InstSeqNum doneSeqNum = fromCommit->commitInfo[tid].doneSeqNum;
#endif
// In any case, squash.
squash(fromCommit->commitInfo[tid].nextPC,
@@ -958,10 +958,10 @@
if (fetchStatus[tid] != Squashing) {
-#if THE_ISA == ALPHA_ISA
- InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
-#else
+#if ISA_HAS_DELAY_SLOT
InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].bdelayDoneSeqNum;
+#else
+ InstSeqNum doneSeqNum = fromDecode->decodeInfo[tid].doneSeqNum;
#endif
// Squash unless we're already squashing
squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
@@ -1162,7 +1162,7 @@
offset += instSize;
-#if THE_ISA != ALPHA_ISA
+#if ISA_HAS_DELAY_SLOT
if (predicted_branch) {
delaySlotInfo[tid].branchSeqNum = inst_seq;
@@ -1205,11 +1205,7 @@
// Now that fetching is completed, update the PC to signify what the next
// cycle will be.
if (fault == NoFault) {
-#if THE_ISA == ALPHA_ISA
- DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
- PC[tid] = next_PC;
- nextPC[tid] = next_PC + instSize;
-#else
+#if ISA_HAS_DELAY_SLOT
if (delaySlotInfo[tid].targetReady &&
delaySlotInfo[tid].numInsts == 0) {
// Set PC to target
@@ -1225,6 +1221,10 @@
}
DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n", tid, PC[tid]);
+#else
+ DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
+ PC[tid] = next_PC;
+ nextPC[tid] = next_PC + instSize;
#endif
} else {
// We shouldn't be in an icache miss and also have a fault (an ITB
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index cdc36c6..e9b24a6 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -427,10 +427,10 @@
instQueue.squash(tid);
// Tell the LDSTQ to start squashing.
-#if THE_ISA == ALPHA_ISA
- ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
-#else
+#if ISA_HAS_DELAY_SLOT
ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid);
+#else
+ ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
#endif
updatedQueues = true;
@@ -439,7 +439,7 @@
tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum);
while (!skidBuffer[tid].empty()) {
-#if THE_ISA != ALPHA_ISA
+#if ISA_HAS_DELAY_SLOT
if (skidBuffer[tid].front()->seqNum <=
fromCommit->commitInfo[tid].bdelayDoneSeqNum) {
DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions "
@@ -479,11 +479,7 @@
toCommit->mispredPC[tid] = inst->readPC();
toCommit->branchMispredict[tid] = true;
-#if THE_ISA == ALPHA_ISA
- toCommit->branchTaken[tid] = inst->readNextPC() !=
- (inst->readPC() + sizeof(TheISA::MachInst));
- toCommit->nextPC[tid] = inst->readNextPC();
-#else
+#if ISA_HAS_DELAY_SLOT
bool branch_taken = inst->readNextNPC() !=
(inst->readNextPC() + sizeof(TheISA::MachInst));
@@ -496,6 +492,10 @@
} else {
toCommit->nextPC[tid] = inst->readNextNPC();
}
+#else
+ toCommit->branchTaken[tid] = inst->readNextPC() !=
+ (inst->readPC() + sizeof(TheISA::MachInst));
+ toCommit->nextPC[tid] = inst->readNextPC();
#endif
toCommit->includeSquashInst[tid] = false;
@@ -860,7 +860,7 @@
{
int insts_from_rename = fromRename->size;
#ifdef DEBUG
-#if THE_ISA == ALPHA_ISA
+#if !ISA_HAS_DELAY_SLOT
for (int i = 0; i < numThreads; i++)
assert(insts[i].empty());
#endif
@@ -878,8 +878,7 @@
"[sn:%i].\n", tid, bdelayDoneSeqNum[tid]);
while (!insts[tid].empty()) {
-
-#if THE_ISA != ALPHA_ISA
+#if ISA_HAS_DELAY_SLOT
if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) {
DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction"
" that occurs at or before delay slot [sn:%i].\n",
@@ -1316,12 +1315,12 @@
fetchRedirect[tid] = true;
DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
-#if THE_ISA == ALPHA_ISA
- DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
- inst->nextPC);
-#else
+#if ISA_HAS_DELAY_SLOT
DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
inst->nextNPC);
+#else
+ DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
+ inst->nextPC);
#endif
// If incorrect, then signal the ROB that it must be squashed.
squashDueToBranch(inst, tid);
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index e799166..47634f6 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -991,10 +991,10 @@
// Read instruction sequence number of last instruction out of the
// time buffer.
-#if THE_ISA == ALPHA_ISA
- squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
-#else
+#if ISA_HAS_DELAY_SLOT
squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
+#else
+ squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
#endif
// Call doSquash if there are insts in the IQ
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 892eb12..782c0fe 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -355,9 +355,7 @@
// "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
// a possible delay slot inst for different architectures
// insts[tid].clear();
-#if THE_ISA == ALPHA_ISA
- insts[tid].clear();
-#else
+#if ISA_HAS_DELAY_SLOT
DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
"[sn:%i].\n",tid, squash_seq_num);
ListIt ilist_it = insts[tid].begin();
@@ -369,14 +367,14 @@
}
ilist_it++;
}
+#else
+ insts[tid].clear();
#endif
// Clear the skid buffer in case it has any data in it.
// See comments above.
// skidBuffer[tid].clear();
-#if THE_ISA == ALPHA_ISA
- skidBuffer[tid].clear();
-#else
+#if ISA_HAS_DELAY_SLOT
DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
"until [sn:%i].\n", tid, squash_seq_num);
ListIt slist_it = skidBuffer[tid].begin();
@@ -388,6 +386,8 @@
}
slist_it++;
}
+#else
+ skidBuffer[tid].clear();
#endif
doSquash(squash_seq_num, tid);
}
@@ -743,7 +743,7 @@
{
int insts_from_decode = fromDecode->size;
#ifdef DEBUG
-#if THE_ISA == ALPHA_ISA
+#if !ISA_HAS_DELAY_SLOT
for (int i=0; i < numThreads; i++)
assert(insts[i].empty());
#endif
@@ -1182,10 +1182,10 @@
DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
"commit.\n", tid);
-#if THE_ISA == ALPHA_ISA
- InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
-#else
+#if ISA_HAS_DELAY_SLOT
InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
+#else
+ InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
#endif
squash(squashed_seq_num, tid);
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 801c96c..22a2101 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -358,12 +358,12 @@
BaseSimpleCPU::setupFetchRequest(Request *req)
{
// set up memory request for instruction fetch
-#if THE_ISA == ALPHA_ISA
- DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
- thread->readNextPC());
-#else
+#if ISA_HAS_DELAY_SLOT
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(),
thread->readNextPC(),thread->readNextNPC());
+#else
+ DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
+ thread->readNextPC());
#endif
req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst),
@@ -450,12 +450,12 @@
else {
// go to the next instruction
thread->setPC(thread->readNextPC());
-#if THE_ISA == ALPHA_ISA
- thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
-#else
+#if ISA_HAS_DELAY_SLOT
thread->setNextPC(thread->readNextNPC());
thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
assert(thread->readNextPC() != thread->readNextNPC());
+#else
+ thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
#endif
}
diff --git a/src/dev/ide_disk.hh b/src/dev/ide_disk.hh
index fb0614d..0bc0b73 100644
--- a/src/dev/ide_disk.hh
+++ b/src/dev/ide_disk.hh
@@ -43,6 +43,8 @@
#include "dev/io_device.hh"
#include "sim/eventq.hh"
+class ChunkGenerator;
+
#define DMA_BACKOFF_PERIOD 200
#define MAX_DMA_SIZE (131072) // 128K
diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc
index b51a931..408d8de 100644
--- a/src/dev/io_device.cc
+++ b/src/dev/io_device.cc
@@ -29,6 +29,7 @@
* Nathan Binkert
*/
+#include "base/chunk_generator.hh"
#include "base/trace.hh"
#include "dev/io_device.hh"
#include "sim/builder.hh"
@@ -36,20 +37,14 @@
PioPort::PioPort(PioDevice *dev, System *s, std::string pname)
- : SimpleTimingPort(dev->name() + pname), device(dev), sys(s)
+ : SimpleTimingPort(dev->name() + pname), device(dev)
{ }
Tick
PioPort::recvAtomic(Packet *pkt)
{
- return device->recvAtomic(pkt);
-}
-
-void
-PioPort::recvFunctional(Packet *pkt)
-{
- device->recvAtomic(pkt);
+ return pkt->isRead() ? device->read(pkt) : device->write(pkt);
}
void
@@ -60,20 +55,6 @@
}
-bool
-PioPort::recvTiming(Packet *pkt)
-{
- if (pkt->result == Packet::Nacked) {
- resendNacked(pkt);
- } else {
- Tick latency = device->recvAtomic(pkt);
- // turn packet around to go back to requester
- pkt->makeTimingResponse();
- sendTiming(pkt, latency);
- }
- return true;
-}
-
PioDevice::~PioDevice()
{
if (pioPort)
diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh
index 710b22b..df4f494 100644
--- a/src/dev/io_device.hh
+++ b/src/dev/io_device.hh
@@ -32,13 +32,12 @@
#ifndef __DEV_IO_DEVICE_HH__
#define __DEV_IO_DEVICE_HH__
-#include "base/chunk_generator.hh"
#include "mem/mem_object.hh"
#include "mem/packet_impl.hh"
-#include "sim/eventq.hh"
#include "sim/sim_object.hh"
#include "mem/tport.hh"
+class Event;
class Platform;
class PioDevice;
class DmaDevice;
@@ -49,35 +48,22 @@
* sensitive to an address range use. The port takes all the memory
* access types and roles them into one read() and write() call that the device
* must respond to. The device must also provide the addressRanges() function
- * with which it returns the address ranges it is interested in. */
-
+ * with which it returns the address ranges it is interested in.
+ */
class PioPort : public SimpleTimingPort
{
protected:
/** The device that this port serves. */
PioDevice *device;
- /** The system that device/port are in. This is used to select which mode
- * we are currently operating in. */
- System *sys;
-
- /** The current status of the peer(bus) that we are connected to. */
- Status peerStatus;
-
- virtual bool recvTiming(Packet *pkt);
-
virtual Tick recvAtomic(Packet *pkt);
- virtual void recvFunctional(Packet *pkt) ;
-
- virtual void recvStatusChange(Status status)
- { peerStatus = status; }
-
- virtual void getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop);
+ virtual void getDeviceAddressRanges(AddrRangeList &resp,
+ AddrRangeList &snoop);
public:
- PioPort(PioDevice *dev, System *s, std::string pname = "-pioport");
+ PioPort(PioDevice *dev, System *s, std::string pname = "-pioport");
};
@@ -132,7 +118,8 @@
virtual void recvRetry() ;
- virtual void getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop)
+ virtual void getDeviceAddressRanges(AddrRangeList &resp,
+ AddrRangeList &snoop)
{ resp.clear(); snoop.clear(); }
void sendDma(Packet *pkt, bool front = false);
@@ -155,7 +142,6 @@
* mode we are in, etc is handled by the PioPort so the device doesn't have to
* bother.
*/
-
class PioDevice : public MemObject
{
protected:
@@ -172,13 +158,8 @@
virtual void addressRanges(AddrRangeList &range_list) = 0;
- /** As far as the devices are concerned they only accept atomic transactions
- * which are converted to either a write or a read. */
- Tick recvAtomic(Packet *pkt)
- { return pkt->isRead() ? this->read(pkt) : this->write(pkt); }
-
- /** Pure virtual function that the device must implement. Called when a read
- * command is recieved by the port.
+ /** Pure virtual function that the device must implement. Called
+ * when a read command is recieved by the port.
* @param pkt Packet describing this request
* @return number of ticks it took to complete
*/
@@ -192,10 +173,9 @@
virtual Tick write(Packet *pkt) = 0;
public:
- /** Params struct which is extended through each device based on the
- * parameters it needs. Since we are re-writing everything, we might as well
- * start from the bottom this time. */
-
+ /** Params struct which is extended through each device based on
+ * the parameters it needs. Since we are re-writing everything, we
+ * might as well start from the bottom this time. */
struct Params
{
std::string name;
@@ -255,7 +235,8 @@
public:
BasicPioDevice(Params *p)
- : PioDevice(p), pioAddr(p->pio_addr), pioSize(0), pioDelay(p->pio_delay)
+ : PioDevice(p), pioAddr(p->pio_addr), pioSize(0),
+ pioDelay(p->pio_delay)
{}
/** return the address ranges that this device responds to.
diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc
index d0e9d75..8ea22cb 100644
--- a/src/dev/pcidev.cc
+++ b/src/dev/pcidev.cc
@@ -39,6 +39,7 @@
#include <vector>
#include "base/inifile.hh"
+#include "base/intmath.hh" // for isPowerOf2(
#include "base/misc.hh"
#include "base/str.hh" // for to_number
#include "base/trace.hh"
@@ -56,8 +57,8 @@
PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
int funcid, Platform *p)
- : PioPort(dev,p->system,"-pciconf"), device(dev), platform(p),
- busId(busid), deviceId(devid), functionId(funcid)
+ : SimpleTimingPort(dev->name() + "-pciconf"), device(dev), platform(p),
+ busId(busid), deviceId(devid), functionId(funcid)
{
configAddr = platform->calcConfigAddr(busId, deviceId, functionId);
}
@@ -67,18 +68,9 @@
PciDev::PciConfigPort::recvAtomic(Packet *pkt)
{
assert(pkt->result == Packet::Unknown);
- assert(pkt->getAddr() >= configAddr && pkt->getAddr() < configAddr +
- PCI_CONFIG_SIZE);
- return device->recvConfig(pkt);
-}
-
-void
-PciDev::PciConfigPort::recvFunctional(Packet *pkt)
-{
- assert(pkt->result == Packet::Unknown);
- assert(pkt->getAddr() >= configAddr && pkt->getAddr() < configAddr +
- PCI_CONFIG_SIZE);
- device->recvConfig(pkt);
+ assert(pkt->getAddr() >= configAddr &&
+ pkt->getAddr() < configAddr + PCI_CONFIG_SIZE);
+ return pkt->isRead() ? device->readConfig(pkt) : device->writeConfig(pkt);
}
void
@@ -90,23 +82,6 @@
}
-bool
-PciDev::PciConfigPort::recvTiming(Packet *pkt)
-{
- if (pkt->result == Packet::Nacked) {
- resendNacked(pkt);
- } else {
- assert(pkt->result == Packet::Unknown);
- assert(pkt->getAddr() >= configAddr && pkt->getAddr() < configAddr +
- PCI_CONFIG_SIZE);
- Tick latency = device->recvConfig(pkt);
- // turn packet around to go back to requester
- pkt->makeTimingResponse();
- sendTiming(pkt, latency);
- }
- return true;
-}
-
PciDev::PciDev(Params *p)
: DmaDevice(p), plat(p->platform), configData(p->configData),
pioDelay(p->pio_delay), configDelay(p->config_delay),
diff --git a/src/dev/pcidev.hh b/src/dev/pcidev.hh
index 8e4f003..22dd629 100644
--- a/src/dev/pcidev.hh
+++ b/src/dev/pcidev.hh
@@ -78,17 +78,13 @@
*/
class PciDev : public DmaDevice
{
- class PciConfigPort : public PioPort
+ class PciConfigPort : public SimpleTimingPort
{
protected:
PciDev *device;
- virtual bool recvTiming(Packet *pkt);
-
virtual Tick recvAtomic(Packet *pkt);
- virtual void recvFunctional(Packet *pkt) ;
-
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop);
@@ -102,9 +98,7 @@
public:
PciConfigPort(PciDev *dev, int busid, int devid, int funcid,
- Platform *p);
-
- friend class PioPort::SendEvent;
+ Platform *p);
};
public:
@@ -239,10 +233,6 @@
*/
void addressRanges(AddrRangeList &range_list);
- /** Do a PCI Configspace memory access. */
- Tick recvConfig(Packet *pkt)
- { return pkt->isRead() ? readConfig(pkt) : writeConfig(pkt); }
-
/**
* Constructor for PCI Dev. This function copies data from the
* config file object PCIConfigData and registers the device with
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index f4fbd2f..8fea733 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -182,7 +182,8 @@
{
snoop.clear();
resp.clear();
- resp.push_back(RangeSize(params()->addrRange.start, params()->addrRange.size()));
+ resp.push_back(RangeSize(params()->addrRange.start,
+ params()->addrRange.size()));
}
int
@@ -191,21 +192,6 @@
return memory->deviceBlockSize();
}
-bool
-PhysicalMemory::MemoryPort::recvTiming(Packet *pkt)
-{
- assert(pkt->result != Packet::Nacked);
-
- Tick latency = memory->calculateLatency(pkt);
-
- memory->doFunctionalAccess(pkt);
-
- pkt->makeTimingResponse();
- sendTiming(pkt, latency);
-
- return true;
-}
-
Tick
PhysicalMemory::MemoryPort::recvAtomic(Packet *pkt)
{
@@ -216,6 +202,9 @@
void
PhysicalMemory::MemoryPort::recvFunctional(Packet *pkt)
{
+ // Default implementation of SimpleTimingPort::recvFunctional()
+ // calls recvAtomic() and throws away the latency; we can save a
+ // little here by just not calculating the latency.
memory->doFunctionalAccess(pkt);
}
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 1489e67..02308b2 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -57,8 +57,6 @@
protected:
- virtual bool recvTiming(Packet *pkt);
-
virtual Tick recvAtomic(Packet *pkt);
virtual void recvFunctional(Packet *pkt);
diff --git a/src/mem/port.hh b/src/mem/port.hh
index 80c591f..6b41840 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -252,11 +252,13 @@
: Port(_name)
{}
+ protected:
virtual bool recvTiming(Packet *pkt) { panic("FuncPort is UniDir"); }
virtual Tick recvAtomic(Packet *pkt) { panic("FuncPort is UniDir"); }
virtual void recvFunctional(Packet *pkt) { panic("FuncPort is UniDir"); }
virtual void recvStatusChange(Status status) {}
+ public:
/** a write function that also does an endian conversion. */
template <typename T>
inline void writeHtoG(Addr addr, T d);
diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index 90cf68f..55c301c 100644
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -31,18 +31,41 @@
#include "mem/tport.hh"
void
+SimpleTimingPort::recvFunctional(Packet *pkt)
+{
+ // just do an atomic access and throw away the returned latency
+ recvAtomic(pkt);
+}
+
+bool
+SimpleTimingPort::recvTiming(Packet *pkt)
+{
+ // If the device is only a slave, it should only be sending
+ // responses, which should never get nacked. There used to be
+ // code to hanldle nacks here, but I'm pretty sure it didn't work
+ // correctly with the drain code, so that would need to be fixed
+ // if we ever added it back.
+ assert(pkt->result != Packet::Nacked);
+ Tick latency = recvAtomic(pkt);
+ // turn packet around to go back to requester
+ pkt->makeTimingResponse();
+ sendTimingLater(pkt, latency);
+ return true;
+}
+
+void
SimpleTimingPort::recvRetry()
{
bool result = true;
while (result && transmitList.size()) {
- result = Port::sendTiming(transmitList.front());
+ result = sendTiming(transmitList.front());
if (result)
transmitList.pop_front();
}
- if (transmitList.size() == 0 && drainEvent) {
- drainEvent->process();
- drainEvent = NULL;
- }
+ if (transmitList.size() == 0 && drainEvent) {
+ drainEvent->process();
+ drainEvent = NULL;
+ }
}
void
@@ -50,26 +73,18 @@
{
port->outTiming--;
assert(port->outTiming >= 0);
- if (port->Port::sendTiming(packet))
- if (port->transmitList.size() == 0 && port->drainEvent) {
- port->drainEvent->process();
- port->drainEvent = NULL;
- }
- return;
-
- port->transmitList.push_back(packet);
-}
-
-void
-SimpleTimingPort::resendNacked(Packet *pkt) {
- pkt->reinitNacked();
- if (transmitList.size()) {
- transmitList.push_front(pkt);
+ if (port->sendTiming(packet)) {
+ // send successfule
+ if (port->transmitList.size() == 0 && port->drainEvent) {
+ port->drainEvent->process();
+ port->drainEvent = NULL;
+ }
} else {
- if (!Port::sendTiming(pkt))
- transmitList.push_front(pkt);
+ // send unsuccessful (due to flow control). Will get retry
+ // callback later; save for then.
+ port->transmitList.push_back(packet);
}
-};
+}
unsigned int
diff --git a/src/mem/tport.hh b/src/mem/tport.hh
index 5473e94..df6d481 100644
--- a/src/mem/tport.hh
+++ b/src/mem/tport.hh
@@ -28,67 +28,52 @@
* Authors: Ali Saidi
*/
-/**
- * @file
- * Implement a port which adds simple support of a sendTiming() function that
- * takes a delay. In this way the * device can immediatly call
- * sendTiming(pkt, time) after processing a request and the request will be
- * handled by the port even if the port bus the device connects to is blocked.
- */
-
-/** recvTiming and drain should be implemented something like this when this
- * class is used.
-
-bool
-PioPort::recvTiming(Packet *pkt)
-{
- if (pkt->result == Packet::Nacked) {
- resendNacked(pkt);
- } else {
- Tick latency = device->recvAtomic(pkt);
- // turn packet around to go back to requester
- pkt->makeTimingResponse();
- sendTiming(pkt, latency);
- }
- return true;
-}
-
-PioDevice::drain(Event *de)
-{
- unsigned int count;
- count = SimpleTimingPort->drain(de);
- if (count)
- changeState(Draining);
- else
- changeState(Drained);
- return count;
-}
-*/
-
#ifndef __MEM_TPORT_HH__
#define __MEM_TPORT_HH__
+/**
+ * @file
+ *
+ * Declaration of SimpleTimingPort.
+ */
+
#include "mem/port.hh"
#include "sim/eventq.hh"
#include <list>
#include <string>
+/**
+ * A simple port for interfacing objects that basically have only
+ * functional memory behavior (e.g. I/O devices) to the memory system.
+ * Both timing and functional accesses are implemented in terms of
+ * atomic accesses. A derived port class thus only needs to provide
+ * recvAtomic() to support all memory access modes.
+ *
+ * The tricky part is handling recvTiming(), where the response must
+ * be scheduled separately via a later call to sendTiming(). This
+ * feature is handled by scheduling an internal event that calls
+ * sendTiming() after a delay, and optionally rescheduling the
+ * response if it is nacked.
+ */
class SimpleTimingPort : public Port
{
protected:
- /** A list of outgoing timing response packets that haven't been serviced
- * yet. */
+ /** A list of outgoing timing response packets that haven't been
+ * serviced yet. */
std::list<Packet*> transmitList;
+
/**
- * This class is used to implemented sendTiming() with a delay. When a delay
- * is requested a new event is created. When the event time expires it
- * attempts to send the packet. If it cannot, the packet is pushed onto the
- * transmit list to be sent when recvRetry() is called. */
+ * This class is used to implemented sendTiming() with a delay. When
+ * a delay is requested a new event is created. When the event time
+ * expires it attempts to send the packet. If it cannot, the packet
+ * is pushed onto the transmit list to be sent when recvRetry() is
+ * called. */
class SendEvent : public Event
{
SimpleTimingPort *port;
Packet *packet;
+ public:
SendEvent(SimpleTimingPort *p, Packet *pkt, Tick t)
: Event(&mainEventQueue), port(p), packet(pkt)
{ setFlags(AutoDelete); schedule(curTick + t); }
@@ -97,8 +82,6 @@
virtual const char *description()
{ return "Future scheduled sendTiming event"; }
-
- friend class SimpleTimingPort;
};
@@ -112,23 +95,49 @@
Event *drainEvent;
/** Schedule a sendTiming() event to be called in the future. */
- void sendTiming(Packet *pkt, Tick time)
- { outTiming++; new SimpleTimingPort::SendEvent(this, pkt, time); }
+ void sendTimingLater(Packet *pkt, Tick time)
+ { outTiming++; new SendEvent(this, pkt, time); }
/** This function is notification that the device should attempt to send a
* packet again. */
virtual void recvRetry();
- void resendNacked(Packet *pkt);
+ /** Implemented using recvAtomic(). */
+ void recvFunctional(Packet *pkt);
+
+ /** Implemented using recvAtomic(). */
+ bool recvTiming(Packet *pkt);
+
+ /**
+ * Simple ports generally don't care about any status
+ * changes... can always override this in cases where that's not
+ * true. */
+ virtual void recvStatusChange(Status status) { }
+
+
public:
SimpleTimingPort(std::string pname)
: Port(pname), outTiming(0), drainEvent(NULL)
{}
+ /** Hook for draining timing accesses from the system. The
+ * associated SimObject's drain() functions should be implemented
+ * something like this when this class is used:
+ \code
+ PioDevice::drain(Event *de)
+ {
+ unsigned int count;
+ count = SimpleTimingPort->drain(de);
+ if (count)
+ changeState(Draining);
+ else
+ changeState(Drained);
+ return count;
+ }
+ \endcode
+ */
unsigned int drain(Event *de);
-
- friend class SimpleTimingPort::SendEvent;
};
#endif // __MEM_TPORT_HH__
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
new file mode 100644
index 0000000..a0d66e6
--- /dev/null
+++ b/src/python/m5/SimObject.py
@@ -0,0 +1,798 @@
+# Copyright (c) 2004-2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+# Nathan Binkert
+
+import sys, types
+
+from util import *
+from multidict import multidict
+
+# These utility functions have to come first because they're
+# referenced in params.py... otherwise they won't be defined when we
+# import params below, and the recursive import of this file from
+# params.py will not find these names.
+def isSimObject(value):
+ return isinstance(value, SimObject)
+
+def isSimObjectClass(value):
+ return issubclass(value, SimObject)
+
+def isSimObjectSequence(value):
+ if not isinstance(value, (list, tuple)) or len(value) == 0:
+ return False
+
+ for val in value:
+ if not isNullPointer(val) and not isSimObject(val):
+ return False
+
+ return True
+
+def isSimObjectOrSequence(value):
+ return isSimObject(value) or isSimObjectSequence(value)
+
+# Have to import params up top since Param is referenced on initial
+# load (when SimObject class references Param to create a class
+# variable, the 'name' param)...
+from params import *
+# There are a few things we need that aren't in params.__all__ since
+# normal users don't need them
+from params import ParamDesc, isNullPointer, SimObjVector
+
+noDot = False
+try:
+ import pydot
+except:
+ noDot = True
+
+#####################################################################
+#
+# M5 Python Configuration Utility
+#
+# The basic idea is to write simple Python programs that build Python
+# objects corresponding to M5 SimObjects for the desired simulation
+# configuration. For now, the Python emits a .ini file that can be
+# parsed by M5. In the future, some tighter integration between M5
+# and the Python interpreter may allow bypassing the .ini file.
+#
+# Each SimObject class in M5 is represented by a Python class with the
+# same name. The Python inheritance tree mirrors the M5 C++ tree
+# (e.g., SimpleCPU derives from BaseCPU in both cases, and all
+# SimObjects inherit from a single SimObject base class). To specify
+# an instance of an M5 SimObject in a configuration, the user simply
+# instantiates the corresponding Python object. The parameters for
+# that SimObject are given by assigning to attributes of the Python
+# object, either using keyword assignment in the constructor or in
+# separate assignment statements. For example:
+#
+# cache = BaseCache(size='64KB')
+# cache.hit_latency = 3
+# cache.assoc = 8
+#
+# The magic lies in the mapping of the Python attributes for SimObject
+# classes to the actual SimObject parameter specifications. This
+# allows parameter validity checking in the Python code. Continuing
+# the example above, the statements "cache.blurfl=3" or
+# "cache.assoc='hello'" would both result in runtime errors in Python,
+# since the BaseCache object has no 'blurfl' parameter and the 'assoc'
+# parameter requires an integer, respectively. This magic is done
+# primarily by overriding the special __setattr__ method that controls
+# assignment to object attributes.
+#
+# Once a set of Python objects have been instantiated in a hierarchy,
+# calling 'instantiate(obj)' (where obj is the root of the hierarchy)
+# will generate a .ini file.
+#
+#####################################################################
+
+# dict to look up SimObjects based on path
+instanceDict = {}
+
+# The metaclass for SimObject. This class controls how new classes
+# that derive from SimObject are instantiated, and provides inherited
+# class behavior (just like a class controls how instances of that
+# class are instantiated, and provides inherited instance behavior).
+class MetaSimObject(type):
+ # Attributes that can be set only at initialization time
+ init_keywords = { 'abstract' : types.BooleanType,
+ 'type' : types.StringType }
+ # Attributes that can be set any time
+ keywords = { 'check' : types.FunctionType,
+ 'cxx_type' : types.StringType,
+ 'cxx_predecls' : types.ListType,
+ 'swig_predecls' : types.ListType }
+
+ # __new__ is called before __init__, and is where the statements
+ # in the body of the class definition get loaded into the class's
+ # __dict__. We intercept this to filter out parameter & port assignments
+ # and only allow "private" attributes to be passed to the base
+ # __new__ (starting with underscore).
+ def __new__(mcls, name, bases, dict):
+ # Copy "private" attributes, functions, and classes to the
+ # official dict. Everything else goes in _init_dict to be
+ # filtered in __init__.
+ cls_dict = {}
+ value_dict = {}
+ for key,val in dict.items():
+ if key.startswith('_') or isinstance(val, (types.FunctionType,
+ types.TypeType)):
+ cls_dict[key] = val
+ else:
+ # must be a param/port setting
+ value_dict[key] = val
+ cls_dict['_value_dict'] = value_dict
+ return super(MetaSimObject, mcls).__new__(mcls, name, bases, cls_dict)
+
+ # subclass initialization
+ def __init__(cls, name, bases, dict):
+ # calls type.__init__()... I think that's a no-op, but leave
+ # it here just in case it's not.
+ super(MetaSimObject, cls).__init__(name, bases, dict)
+
+ # initialize required attributes
+
+ # class-only attributes
+ cls._params = multidict() # param descriptions
+ cls._ports = multidict() # port descriptions
+
+ # class or instance attributes
+ cls._values = multidict() # param values
+ cls._port_refs = multidict() # port ref objects
+ cls._instantiated = False # really instantiated, cloned, or subclassed
+
+ # We don't support multiple inheritance. If you want to, you
+ # must fix multidict to deal with it properly.
+ if len(bases) > 1:
+ raise TypeError, "SimObjects do not support multiple inheritance"
+
+ base = bases[0]
+
+ # Set up general inheritance via multidicts. A subclass will
+ # inherit all its settings from the base class. The only time
+ # the following is not true is when we define the SimObject
+ # class itself (in which case the multidicts have no parent).
+ if isinstance(base, MetaSimObject):
+ cls._params.parent = base._params
+ cls._ports.parent = base._ports
+ cls._values.parent = base._values
+ cls._port_refs.parent = base._port_refs
+ # mark base as having been subclassed
+ base._instantiated = True
+
+ # Now process the _value_dict items. They could be defining
+ # new (or overriding existing) parameters or ports, setting
+ # class keywords (e.g., 'abstract'), or setting parameter
+ # values or port bindings. The first 3 can only be set when
+ # the class is defined, so we handle them here. The others
+ # can be set later too, so just emulate that by calling
+ # setattr().
+ for key,val in cls._value_dict.items():
+ # param descriptions
+ if isinstance(val, ParamDesc):
+ cls._new_param(key, val)
+
+ # port objects
+ elif isinstance(val, Port):
+ cls._new_port(key, val)
+
+ # init-time-only keywords
+ elif cls.init_keywords.has_key(key):
+ cls._set_keyword(key, val, cls.init_keywords[key])
+
+ # default: use normal path (ends up in __setattr__)
+ else:
+ setattr(cls, key, val)
+
+ cls.cxx_type = cls.type + '*'
+ # A forward class declaration is sufficient since we are just
+ # declaring a pointer.
+ cls.cxx_predecls = ['class %s;' % cls.type]
+ cls.swig_predecls = cls.cxx_predecls
+
+ def _set_keyword(cls, keyword, val, kwtype):
+ if not isinstance(val, kwtype):
+ raise TypeError, 'keyword %s has bad type %s (expecting %s)' % \
+ (keyword, type(val), kwtype)
+ if isinstance(val, types.FunctionType):
+ val = classmethod(val)
+ type.__setattr__(cls, keyword, val)
+
+ def _new_param(cls, name, pdesc):
+ # each param desc should be uniquely assigned to one variable
+ assert(not hasattr(pdesc, 'name'))
+ pdesc.name = name
+ cls._params[name] = pdesc
+ if hasattr(pdesc, 'default'):
+ cls._set_param(name, pdesc.default, pdesc)
+
+ def _set_param(cls, name, value, param):
+ assert(param.name == name)
+ try:
+ cls._values[name] = param.convert(value)
+ except Exception, e:
+ msg = "%s\nError setting param %s.%s to %s\n" % \
+ (e, cls.__name__, name, value)
+ e.args = (msg, )
+ raise
+
+ def _new_port(cls, name, port):
+ # each port should be uniquely assigned to one variable
+ assert(not hasattr(port, 'name'))
+ port.name = name
+ cls._ports[name] = port
+ if hasattr(port, 'default'):
+ cls._cls_get_port_ref(name).connect(port.default)
+
+ # same as _get_port_ref, effectively, but for classes
+ def _cls_get_port_ref(cls, attr):
+ # Return reference that can be assigned to another port
+ # via __setattr__. There is only ever one reference
+ # object per port, but we create them lazily here.
+ ref = cls._port_refs.get(attr)
+ if not ref:
+ ref = cls._ports[attr].makeRef(cls)
+ cls._port_refs[attr] = ref
+ return ref
+
+ # Set attribute (called on foo.attr = value when foo is an
+ # instance of class cls).
+ def __setattr__(cls, attr, value):
+ # normal processing for private attributes
+ if attr.startswith('_'):
+ type.__setattr__(cls, attr, value)
+ return
+
+ if cls.keywords.has_key(attr):
+ cls._set_keyword(attr, value, cls.keywords[attr])
+ return
+
+ if cls._ports.has_key(attr):
+ cls._cls_get_port_ref(attr).connect(value)
+ return
+
+ if isSimObjectOrSequence(value) and cls._instantiated:
+ raise RuntimeError, \
+ "cannot set SimObject parameter '%s' after\n" \
+ " class %s has been instantiated or subclassed" \
+ % (attr, cls.__name__)
+
+ # check for param
+ param = cls._params.get(attr)
+ if param:
+ cls._set_param(attr, value, param)
+ return
+
+ if isSimObjectOrSequence(value):
+ # If RHS is a SimObject, it's an implicit child assignment.
+ # Classes don't have children, so we just put this object
+ # in _values; later, each instance will do a 'setattr(self,
+ # attr, _values[attr])' in SimObject.__init__ which will
+ # add this object as a child.
+ cls._values[attr] = value
+ return
+
+ # no valid assignment... raise exception
+ raise AttributeError, \
+ "Class %s has no parameter \'%s\'" % (cls.__name__, attr)
+
+ def __getattr__(cls, attr):
+ if cls._values.has_key(attr):
+ return cls._values[attr]
+
+ raise AttributeError, \
+ "object '%s' has no attribute '%s'" % (cls.__name__, attr)
+
+ def __str__(cls):
+ return cls.__name__
+
+ def cxx_decl(cls):
+ code = "#ifndef __PARAMS__%s\n#define __PARAMS__%s\n\n" % (cls, cls)
+
+ if str(cls) != 'SimObject':
+ base = cls.__bases__[0].type
+ else:
+ base = None
+
+ # The 'dict' attribute restricts us to the params declared in
+ # the object itself, not including inherited params (which
+ # will also be inherited from the base class's param struct
+ # here).
+ params = cls._params.dict.values()
+ try:
+ ptypes = [p.ptype for p in params]
+ except:
+ print cls, p, p.ptype_str
+ print params
+ raise
+
+ # get a list of lists of predeclaration lines
+ predecls = [p.cxx_predecls() for p in params]
+ # flatten
+ predecls = reduce(lambda x,y:x+y, predecls, [])
+ # remove redundant lines
+ predecls2 = []
+ for pd in predecls:
+ if pd not in predecls2:
+ predecls2.append(pd)
+ predecls2.sort()
+ code += "\n".join(predecls2)
+ code += "\n\n";
+
+ if base:
+ code += '#include "params/%s.hh"\n\n' % base
+
+ # Generate declarations for locally defined enumerations.
+ enum_ptypes = [t for t in ptypes if issubclass(t, Enum)]
+ if enum_ptypes:
+ code += "\n".join([t.cxx_decl() for t in enum_ptypes])
+ code += "\n\n"
+
+ # now generate the actual param struct
+ code += "struct %sParams" % cls
+ if base:
+ code += " : public %sParams" % base
+ code += " {\n"
+ decls = [p.cxx_decl() for p in params]
+ decls.sort()
+ code += "".join([" %s\n" % d for d in decls])
+ code += "};\n"
+
+ # close #ifndef __PARAMS__* guard
+ code += "\n#endif\n"
+ return code
+
+ def swig_decl(cls):
+
+ code = '%%module %sParams\n' % cls
+
+ if str(cls) != 'SimObject':
+ base = cls.__bases__[0].type
+ else:
+ base = None
+
+ # The 'dict' attribute restricts us to the params declared in
+ # the object itself, not including inherited params (which
+ # will also be inherited from the base class's param struct
+ # here).
+ params = cls._params.dict.values()
+ ptypes = [p.ptype for p in params]
+
+ # get a list of lists of predeclaration lines
+ predecls = [p.swig_predecls() for p in params]
+ # flatten
+ predecls = reduce(lambda x,y:x+y, predecls, [])
+ # remove redundant lines
+ predecls2 = []
+ for pd in predecls:
+ if pd not in predecls2:
+ predecls2.append(pd)
+ predecls2.sort()
+ code += "\n".join(predecls2)
+ code += "\n\n";
+
+ if base:
+ code += '%%import "python/m5/swig/%sParams.i"\n\n' % base
+
+ code += '%{\n'
+ code += '#include "params/%s.hh"\n' % cls
+ code += '%}\n\n'
+ code += '%%include "params/%s.hh"\n\n' % cls
+
+ return code
+
+# The SimObject class is the root of the special hierarchy. Most of
+# the code in this class deals with the configuration hierarchy itself
+# (parent/child node relationships).
+class SimObject(object):
+ # Specify metaclass. Any class inheriting from SimObject will
+ # get this metaclass.
+ __metaclass__ = MetaSimObject
+ type = 'SimObject'
+
+ name = Param.String("Object name")
+
+ # Initialize new instance. For objects with SimObject-valued
+ # children, we need to recursively clone the classes represented
+ # by those param values as well in a consistent "deep copy"-style
+ # fashion. That is, we want to make sure that each instance is
+ # cloned only once, and that if there are multiple references to
+ # the same original object, we end up with the corresponding
+ # cloned references all pointing to the same cloned instance.
+ def __init__(self, **kwargs):
+ ancestor = kwargs.get('_ancestor')
+ memo_dict = kwargs.get('_memo')
+ if memo_dict is None:
+ # prepare to memoize any recursively instantiated objects
+ memo_dict = {}
+ elif ancestor:
+ # memoize me now to avoid problems with recursive calls
+ memo_dict[ancestor] = self
+
+ if not ancestor:
+ ancestor = self.__class__
+ ancestor._instantiated = True
+
+ # initialize required attributes
+ self._parent = None
+ self._children = {}
+ self._ccObject = None # pointer to C++ object
+ self._instantiated = False # really "cloned"
+
+ # Inherit parameter values from class using multidict so
+ # individual value settings can be overridden.
+ self._values = multidict(ancestor._values)
+ # clone SimObject-valued parameters
+ for key,val in ancestor._values.iteritems():
+ if isSimObject(val):
+ setattr(self, key, val(_memo=memo_dict))
+ elif isSimObjectSequence(val) and len(val):
+ setattr(self, key, [ v(_memo=memo_dict) for v in val ])
+ # clone port references. no need to use a multidict here
+ # since we will be creating new references for all ports.
+ self._port_refs = {}
+ for key,val in ancestor._port_refs.iteritems():
+ self._port_refs[key] = val.clone(self, memo_dict)
+ # apply attribute assignments from keyword args, if any
+ for key,val in kwargs.iteritems():
+ setattr(self, key, val)
+
+ # "Clone" the current instance by creating another instance of
+ # this instance's class, but that inherits its parameter values
+ # and port mappings from the current instance. If we're in a
+ # "deep copy" recursive clone, check the _memo dict to see if
+ # we've already cloned this instance.
+ def __call__(self, **kwargs):
+ memo_dict = kwargs.get('_memo')
+ if memo_dict is None:
+ # no memo_dict: must be top-level clone operation.
+ # this is only allowed at the root of a hierarchy
+ if self._parent:
+ raise RuntimeError, "attempt to clone object %s " \
+ "not at the root of a tree (parent = %s)" \
+ % (self, self._parent)
+ # create a new dict and use that.
+ memo_dict = {}
+ kwargs['_memo'] = memo_dict
+ elif memo_dict.has_key(self):
+ # clone already done & memoized
+ return memo_dict[self]
+ return self.__class__(_ancestor = self, **kwargs)
+
+ def _get_port_ref(self, attr):
+ # Return reference that can be assigned to another port
+ # via __setattr__. There is only ever one reference
+ # object per port, but we create them lazily here.
+ ref = self._port_refs.get(attr)
+ if not ref:
+ ref = self._ports[attr].makeRef(self)
+ self._port_refs[attr] = ref
+ return ref
+
+ def __getattr__(self, attr):
+ if self._ports.has_key(attr):
+ return self._get_port_ref(attr)
+
+ if self._values.has_key(attr):
+ return self._values[attr]
+
+ raise AttributeError, "object '%s' has no attribute '%s'" \
+ % (self.__class__.__name__, attr)
+
+ # Set attribute (called on foo.attr = value when foo is an
+ # instance of class cls).
+ def __setattr__(self, attr, value):
+ # normal processing for private attributes
+ if attr.startswith('_'):
+ object.__setattr__(self, attr, value)
+ return
+
+ if self._ports.has_key(attr):
+ # set up port connection
+ self._get_port_ref(attr).connect(value)
+ return
+
+ if isSimObjectOrSequence(value) and self._instantiated:
+ raise RuntimeError, \
+ "cannot set SimObject parameter '%s' after\n" \
+ " instance been cloned %s" % (attr, `self`)
+
+ # must be SimObject param
+ param = self._params.get(attr)
+ if param:
+ try:
+ value = param.convert(value)
+ except Exception, e:
+ msg = "%s\nError setting param %s.%s to %s\n" % \
+ (e, self.__class__.__name__, attr, value)
+ e.args = (msg, )
+ raise
+ self._set_child(attr, value)
+ return
+
+ if isSimObjectOrSequence(value):
+ self._set_child(attr, value)
+ return
+
+ # no valid assignment... raise exception
+ raise AttributeError, "Class %s has no parameter %s" \
+ % (self.__class__.__name__, attr)
+
+
+ # this hack allows tacking a '[0]' onto parameters that may or may
+ # not be vectors, and always getting the first element (e.g. cpus)
+ def __getitem__(self, key):
+ if key == 0:
+ return self
+ raise TypeError, "Non-zero index '%s' to SimObject" % key
+
+ # clear out children with given name, even if it's a vector
+ def clear_child(self, name):
+ if not self._children.has_key(name):
+ return
+ child = self._children[name]
+ if isinstance(child, SimObjVector):
+ for i in xrange(len(child)):
+ del self._children["s%d" % (name, i)]
+ del self._children[name]
+
+ def add_child(self, name, value):
+ self._children[name] = value
+
+ def _maybe_set_parent(self, parent, name):
+ if not self._parent:
+ self._parent = parent
+ self._name = name
+ parent.add_child(name, self)
+
+ def _set_child(self, attr, value):
+ # if RHS is a SimObject, it's an implicit child assignment
+ # clear out old child with this name, if any
+ self.clear_child(attr)
+
+ if isSimObject(value):
+ value._maybe_set_parent(self, attr)
+ elif isSimObjectSequence(value):
+ value = SimObjVector(value)
+ [v._maybe_set_parent(self, "%s%d" % (attr, i))
+ for i,v in enumerate(value)]
+
+ self._values[attr] = value
+
+ def path(self):
+ if not self._parent:
+ return 'root'
+ ppath = self._parent.path()
+ if ppath == 'root':
+ return self._name
+ return ppath + "." + self._name
+
+ def __str__(self):
+ return self.path()
+
+ def ini_str(self):
+ return self.path()
+
+ def find_any(self, ptype):
+ if isinstance(self, ptype):
+ return self, True
+
+ found_obj = None
+ for child in self._children.itervalues():
+ if isinstance(child, ptype):
+ if found_obj != None and child != found_obj:
+ raise AttributeError, \
+ 'parent.any matched more than one: %s %s' % \
+ (found_obj.path, child.path)
+ found_obj = child
+ # search param space
+ for pname,pdesc in self._params.iteritems():
+ if issubclass(pdesc.ptype, ptype):
+ match_obj = self._values[pname]
+ if found_obj != None and found_obj != match_obj:
+ raise AttributeError, \
+ 'parent.any matched more than one: %s' % obj.path
+ found_obj = match_obj
+ return found_obj, found_obj != None
+
+ def unproxy(self, base):
+ return self
+
+ def unproxy_all(self):
+ for param in self._params.iterkeys():
+ value = self._values.get(param)
+ if value != None and proxy.isproxy(value):
+ try:
+ value = value.unproxy(self)
+ except:
+ print "Error in unproxying param '%s' of %s" % \
+ (param, self.path())
+ raise
+ setattr(self, param, value)
+
+ # Unproxy ports in sorted order so that 'append' operations on
+ # vector ports are done in a deterministic fashion.
+ port_names = self._ports.keys()
+ port_names.sort()
+ for port_name in port_names:
+ port = self._port_refs.get(port_name)
+ if port != None:
+ port.unproxy(self)
+
+ # Unproxy children in sorted order for determinism also.
+ child_names = self._children.keys()
+ child_names.sort()
+ for child in child_names:
+ self._children[child].unproxy_all()
+
+ def print_ini(self):
+ print '[' + self.path() + ']' # .ini section header
+
+ instanceDict[self.path()] = self
+
+ if hasattr(self, 'type') and not isinstance(self, ParamContext):
+ print 'type=%s' % self.type
+
+ child_names = self._children.keys()
+ child_names.sort()
+ np_child_names = [c for c in child_names \
+ if not isinstance(self._children[c], ParamContext)]
+ if len(np_child_names):
+ print 'children=%s' % ' '.join(np_child_names)
+
+ param_names = self._params.keys()
+ param_names.sort()
+ for param in param_names:
+ value = self._values.get(param)
+ if value != None:
+ print '%s=%s' % (param, self._values[param].ini_str())
+
+ port_names = self._ports.keys()
+ port_names.sort()
+ for port_name in port_names:
+ port = self._port_refs.get(port_name, None)
+ if port != None:
+ print '%s=%s' % (port_name, port.ini_str())
+
+ print # blank line between objects
+
+ for child in child_names:
+ self._children[child].print_ini()
+
+ # Call C++ to create C++ object corresponding to this object and
+ # (recursively) all its children
+ def createCCObject(self):
+ self.getCCObject() # force creation
+ for child in self._children.itervalues():
+ child.createCCObject()
+
+ # Get C++ object corresponding to this object, calling C++ if
+ # necessary to construct it. Does *not* recursively create
+ # children.
+ def getCCObject(self):
+ if not self._ccObject:
+ self._ccObject = -1 # flag to catch cycles in recursion
+ self._ccObject = cc_main.createSimObject(self.path())
+ elif self._ccObject == -1:
+ raise RuntimeError, "%s: recursive call to getCCObject()" \
+ % self.path()
+ return self._ccObject
+
+ # Create C++ port connections corresponding to the connections in
+ # _port_refs (& recursively for all children)
+ def connectPorts(self):
+ for portRef in self._port_refs.itervalues():
+ portRef.ccConnect()
+ for child in self._children.itervalues():
+ child.connectPorts()
+
+ def startDrain(self, drain_event, recursive):
+ count = 0
+ # ParamContexts don't serialize
+ if isinstance(self, SimObject) and not isinstance(self, ParamContext):
+ count += self._ccObject.drain(drain_event)
+ if recursive:
+ for child in self._children.itervalues():
+ count += child.startDrain(drain_event, True)
+ return count
+
+ def resume(self):
+ if isinstance(self, SimObject) and not isinstance(self, ParamContext):
+ self._ccObject.resume()
+ for child in self._children.itervalues():
+ child.resume()
+
+ def changeTiming(self, mode):
+ if isinstance(self, System):
+ self._ccObject.setMemoryMode(mode)
+ for child in self._children.itervalues():
+ child.changeTiming(mode)
+
+ def takeOverFrom(self, old_cpu):
+ cpu_ptr = cc_main.convertToBaseCPUPtr(old_cpu._ccObject)
+ self._ccObject.takeOverFrom(cpu_ptr)
+
+ # generate output file for 'dot' to display as a pretty graph.
+ # this code is currently broken.
+ def outputDot(self, dot):
+ label = "{%s|" % self.path
+ if isSimObject(self.realtype):
+ label += '%s|' % self.type
+
+ if self.children:
+ # instantiate children in same order they were added for
+ # backward compatibility (else we can end up with cpu1
+ # before cpu0).
+ for c in self.children:
+ dot.add_edge(pydot.Edge(self.path,c.path, style="bold"))
+
+ simobjs = []
+ for param in self.params:
+ try:
+ if param.value is None:
+ raise AttributeError, 'Parameter with no value'
+
+ value = param.value
+ string = param.string(value)
+ except Exception, e:
+ msg = 'exception in %s:%s\n%s' % (self.name, param.name, e)
+ e.args = (msg, )
+ raise
+
+ if isSimObject(param.ptype) and string != "Null":
+ simobjs.append(string)
+ else:
+ label += '%s = %s\\n' % (param.name, string)
+
+ for so in simobjs:
+ label += "|<%s> %s" % (so, so)
+ dot.add_edge(pydot.Edge("%s:%s" % (self.path, so), so,
+ tailport="w"))
+ label += '}'
+ dot.add_node(pydot.Node(self.path,shape="Mrecord",label=label))
+
+ # recursively dump out children
+ for c in self.children:
+ c.outputDot(dot)
+
+class ParamContext(SimObject):
+ pass
+
+# Function to provide to C++ so it can look up instances based on paths
+def resolveSimObject(name):
+ obj = instanceDict[name]
+ return obj.getCCObject()
+
+# __all__ defines the list of symbols that get exported when
+# 'from config import *' is invoked. Try to keep this reasonably
+# short to avoid polluting other namespaces.
+__all__ = ['SimObject', 'ParamContext']
+
+
+# see comment on imports at end of __init__.py.
+import proxy
+import cc_main
+import m5
diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py
index 950d605..5717b49 100644
--- a/src/python/m5/__init__.py
+++ b/src/python/m5/__init__.py
@@ -44,6 +44,7 @@
print >>sys.stderr, 'panic:', string
sys.exit(1)
+# force scalars to one-element lists for uniformity
def makeList(objOrList):
if isinstance(objOrList, list):
return objOrList
@@ -71,17 +72,11 @@
env = smartdict.SmartDict()
env.update(os.environ)
-# Function to provide to C++ so it can look up instances based on paths
-def resolveSimObject(name):
- obj = config.instanceDict[name]
- return obj.getCCObject()
-
-from main import options, arguments, main
-
# The final hook to generate .ini files. Called from the user script
# once the config is built.
def instantiate(root):
- config.ticks_per_sec = float(root.clock.frequency)
+ params.ticks_per_sec = float(root.clock.frequency)
+ root.unproxy_all()
# ugly temporary hack to get output to config.ini
sys.stdout = file(os.path.join(options.outdir, 'config.ini'), 'w')
root.print_ini()
@@ -109,11 +104,6 @@
# register our C++ exit callback function with Python
atexit.register(cc_main.doExitCleanup)
-# This import allows user scripts to reference 'm5.objects.Foo' after
-# just doing an 'import m5' (without an 'import m5.objects'). May not
-# matter since most scripts will probably 'from m5.objects import *'.
-import objects
-
# This loops until all objects have been fully drained.
def doDrain(root):
all_drained = drain(root)
@@ -206,3 +196,17 @@
new_cpu.takeOverFrom(old_cpus[index])
new_cpu._ccObject.resume()
index += 1
+
+# Since we have so many mutual imports in this package, we should:
+# 1. Put all intra-package imports at the *bottom* of the file, unless
+# they're absolutely needed before that (for top-level statements
+# or class attributes). Imports of "trivial" packages that don't
+# import other packages (e.g., 'smartdict') can be at the top.
+# 2. Never use 'from foo import *' on an intra-package import since
+# you can get the wrong result if foo is only partially imported
+# at the point you do that (i.e., because foo is in the middle of
+# importing *you*).
+from main import options
+import objects
+import params
+from SimObject import resolveSimObject
diff --git a/src/python/m5/config.py b/src/python/m5/config.py
deleted file mode 100644
index df4b74c..0000000
--- a/src/python/m5/config.py
+++ /dev/null
@@ -1,1527 +0,0 @@
-# Copyright (c) 2004-2006 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Steve Reinhardt
-# Nathan Binkert
-
-import os, re, sys, types, inspect, copy
-
-import m5
-from m5 import panic, cc_main
-from convert import *
-from multidict import multidict
-
-noDot = False
-try:
- import pydot
-except:
- noDot = True
-
-class Singleton(type):
- def __call__(cls, *args, **kwargs):
- if hasattr(cls, '_instance'):
- return cls._instance
-
- cls._instance = super(Singleton, cls).__call__(*args, **kwargs)
- return cls._instance
-
-#####################################################################
-#
-# M5 Python Configuration Utility
-#
-# The basic idea is to write simple Python programs that build Python
-# objects corresponding to M5 SimObjects for the desired simulation
-# configuration. For now, the Python emits a .ini file that can be
-# parsed by M5. In the future, some tighter integration between M5
-# and the Python interpreter may allow bypassing the .ini file.
-#
-# Each SimObject class in M5 is represented by a Python class with the
-# same name. The Python inheritance tree mirrors the M5 C++ tree
-# (e.g., SimpleCPU derives from BaseCPU in both cases, and all
-# SimObjects inherit from a single SimObject base class). To specify
-# an instance of an M5 SimObject in a configuration, the user simply
-# instantiates the corresponding Python object. The parameters for
-# that SimObject are given by assigning to attributes of the Python
-# object, either using keyword assignment in the constructor or in
-# separate assignment statements. For example:
-#
-# cache = BaseCache(size='64KB')
-# cache.hit_latency = 3
-# cache.assoc = 8
-#
-# The magic lies in the mapping of the Python attributes for SimObject
-# classes to the actual SimObject parameter specifications. This
-# allows parameter validity checking in the Python code. Continuing
-# the example above, the statements "cache.blurfl=3" or
-# "cache.assoc='hello'" would both result in runtime errors in Python,
-# since the BaseCache object has no 'blurfl' parameter and the 'assoc'
-# parameter requires an integer, respectively. This magic is done
-# primarily by overriding the special __setattr__ method that controls
-# assignment to object attributes.
-#
-# Once a set of Python objects have been instantiated in a hierarchy,
-# calling 'instantiate(obj)' (where obj is the root of the hierarchy)
-# will generate a .ini file.
-#
-#####################################################################
-
-# dict to look up SimObjects based on path
-instanceDict = {}
-
-#############################
-#
-# Utility methods
-#
-#############################
-
-def isSimObject(value):
- return isinstance(value, SimObject)
-
-def isSimObjectSequence(value):
- if not isinstance(value, (list, tuple)) or len(value) == 0:
- return False
-
- for val in value:
- if not isNullPointer(val) and not isSimObject(val):
- return False
-
- return True
-
-def isSimObjectOrSequence(value):
- return isSimObject(value) or isSimObjectSequence(value)
-
-def isNullPointer(value):
- return isinstance(value, NullSimObject)
-
-# Apply method to object.
-# applyMethod(obj, 'meth', <args>) is equivalent to obj.meth(<args>)
-def applyMethod(obj, meth, *args, **kwargs):
- return getattr(obj, meth)(*args, **kwargs)
-
-# If the first argument is an (non-sequence) object, apply the named
-# method with the given arguments. If the first argument is a
-# sequence, apply the method to each element of the sequence (a la
-# 'map').
-def applyOrMap(objOrSeq, meth, *args, **kwargs):
- if not isinstance(objOrSeq, (list, tuple)):
- return applyMethod(objOrSeq, meth, *args, **kwargs)
- else:
- return [applyMethod(o, meth, *args, **kwargs) for o in objOrSeq]
-
-
-# The metaclass for SimObject. This class controls how new classes
-# that derive from SimObject are instantiated, and provides inherited
-# class behavior (just like a class controls how instances of that
-# class are instantiated, and provides inherited instance behavior).
-class MetaSimObject(type):
- # Attributes that can be set only at initialization time
- init_keywords = { 'abstract' : types.BooleanType,
- 'type' : types.StringType }
- # Attributes that can be set any time
- keywords = { 'check' : types.FunctionType }
-
- # __new__ is called before __init__, and is where the statements
- # in the body of the class definition get loaded into the class's
- # __dict__. We intercept this to filter out parameter & port assignments
- # and only allow "private" attributes to be passed to the base
- # __new__ (starting with underscore).
- def __new__(mcls, name, bases, dict):
- # Copy "private" attributes, functions, and classes to the
- # official dict. Everything else goes in _init_dict to be
- # filtered in __init__.
- cls_dict = {}
- value_dict = {}
- for key,val in dict.items():
- if key.startswith('_') or isinstance(val, (types.FunctionType,
- types.TypeType)):
- cls_dict[key] = val
- else:
- # must be a param/port setting
- value_dict[key] = val
- cls_dict['_value_dict'] = value_dict
- return super(MetaSimObject, mcls).__new__(mcls, name, bases, cls_dict)
-
- # subclass initialization
- def __init__(cls, name, bases, dict):
- # calls type.__init__()... I think that's a no-op, but leave
- # it here just in case it's not.
- super(MetaSimObject, cls).__init__(name, bases, dict)
-
- # initialize required attributes
-
- # class-only attributes
- cls._params = multidict() # param descriptions
- cls._ports = multidict() # port descriptions
-
- # class or instance attributes
- cls._values = multidict() # param values
- cls._port_map = multidict() # port bindings
- cls._instantiated = False # really instantiated, cloned, or subclassed
-
- # We don't support multiple inheritance. If you want to, you
- # must fix multidict to deal with it properly.
- if len(bases) > 1:
- raise TypeError, "SimObjects do not support multiple inheritance"
-
- base = bases[0]
-
- # Set up general inheritance via multidicts. A subclass will
- # inherit all its settings from the base class. The only time
- # the following is not true is when we define the SimObject
- # class itself (in which case the multidicts have no parent).
- if isinstance(base, MetaSimObject):
- cls._params.parent = base._params
- cls._ports.parent = base._ports
- cls._values.parent = base._values
- cls._port_map.parent = base._port_map
- # mark base as having been subclassed
- base._instantiated = True
-
- # Now process the _value_dict items. They could be defining
- # new (or overriding existing) parameters or ports, setting
- # class keywords (e.g., 'abstract'), or setting parameter
- # values or port bindings. The first 3 can only be set when
- # the class is defined, so we handle them here. The others
- # can be set later too, so just emulate that by calling
- # setattr().
- for key,val in cls._value_dict.items():
- # param descriptions
- if isinstance(val, ParamDesc):
- cls._new_param(key, val)
-
- # port objects
- elif isinstance(val, Port):
- cls._ports[key] = val
-
- # init-time-only keywords
- elif cls.init_keywords.has_key(key):
- cls._set_keyword(key, val, cls.init_keywords[key])
-
- # default: use normal path (ends up in __setattr__)
- else:
- setattr(cls, key, val)
-
- def _set_keyword(cls, keyword, val, kwtype):
- if not isinstance(val, kwtype):
- raise TypeError, 'keyword %s has bad type %s (expecting %s)' % \
- (keyword, type(val), kwtype)
- if isinstance(val, types.FunctionType):
- val = classmethod(val)
- type.__setattr__(cls, keyword, val)
-
- def _new_param(cls, name, value):
- cls._params[name] = value
- if hasattr(value, 'default'):
- setattr(cls, name, value.default)
-
- # Set attribute (called on foo.attr = value when foo is an
- # instance of class cls).
- def __setattr__(cls, attr, value):
- # normal processing for private attributes
- if attr.startswith('_'):
- type.__setattr__(cls, attr, value)
- return
-
- if cls.keywords.has_key(attr):
- cls._set_keyword(attr, value, cls.keywords[attr])
- return
-
- if cls._ports.has_key(attr):
- self._ports[attr].connect(self, attr, value)
- return
-
- if isSimObjectOrSequence(value) and cls._instantiated:
- raise RuntimeError, \
- "cannot set SimObject parameter '%s' after\n" \
- " class %s has been instantiated or subclassed" \
- % (attr, cls.__name__)
-
- # check for param
- param = cls._params.get(attr, None)
- if param:
- try:
- cls._values[attr] = param.convert(value)
- except Exception, e:
- msg = "%s\nError setting param %s.%s to %s\n" % \
- (e, cls.__name__, attr, value)
- e.args = (msg, )
- raise
- elif isSimObjectOrSequence(value):
- # if RHS is a SimObject, it's an implicit child assignment
- cls._values[attr] = value
- else:
- raise AttributeError, \
- "Class %s has no parameter \'%s\'" % (cls.__name__, attr)
-
- def __getattr__(cls, attr):
- if cls._values.has_key(attr):
- return cls._values[attr]
-
- raise AttributeError, \
- "object '%s' has no attribute '%s'" % (cls.__name__, attr)
-
-# The SimObject class is the root of the special hierarchy. Most of
-# the code in this class deals with the configuration hierarchy itself
-# (parent/child node relationships).
-class SimObject(object):
- # Specify metaclass. Any class inheriting from SimObject will
- # get this metaclass.
- __metaclass__ = MetaSimObject
-
- # Initialize new instance. For objects with SimObject-valued
- # children, we need to recursively clone the classes represented
- # by those param values as well in a consistent "deep copy"-style
- # fashion. That is, we want to make sure that each instance is
- # cloned only once, and that if there are multiple references to
- # the same original object, we end up with the corresponding
- # cloned references all pointing to the same cloned instance.
- def __init__(self, **kwargs):
- ancestor = kwargs.get('_ancestor')
- memo_dict = kwargs.get('_memo')
- if memo_dict is None:
- # prepare to memoize any recursively instantiated objects
- memo_dict = {}
- elif ancestor:
- # memoize me now to avoid problems with recursive calls
- memo_dict[ancestor] = self
-
- if not ancestor:
- ancestor = self.__class__
- ancestor._instantiated = True
-
- # initialize required attributes
- self._parent = None
- self._children = {}
- self._ccObject = None # pointer to C++ object
- self._instantiated = False # really "cloned"
-
- # Inherit parameter values from class using multidict so
- # individual value settings can be overridden.
- self._values = multidict(ancestor._values)
- # clone SimObject-valued parameters
- for key,val in ancestor._values.iteritems():
- if isSimObject(val):
- setattr(self, key, val(_memo=memo_dict))
- elif isSimObjectSequence(val) and len(val):
- setattr(self, key, [ v(_memo=memo_dict) for v in val ])
- # clone port references. no need to use a multidict here
- # since we will be creating new references for all ports.
- self._port_map = {}
- for key,val in ancestor._port_map.iteritems():
- self._port_map[key] = applyOrMap(val, 'clone', memo_dict)
- # apply attribute assignments from keyword args, if any
- for key,val in kwargs.iteritems():
- setattr(self, key, val)
-
- # "Clone" the current instance by creating another instance of
- # this instance's class, but that inherits its parameter values
- # and port mappings from the current instance. If we're in a
- # "deep copy" recursive clone, check the _memo dict to see if
- # we've already cloned this instance.
- def __call__(self, **kwargs):
- memo_dict = kwargs.get('_memo')
- if memo_dict is None:
- # no memo_dict: must be top-level clone operation.
- # this is only allowed at the root of a hierarchy
- if self._parent:
- raise RuntimeError, "attempt to clone object %s " \
- "not at the root of a tree (parent = %s)" \
- % (self, self._parent)
- # create a new dict and use that.
- memo_dict = {}
- kwargs['_memo'] = memo_dict
- elif memo_dict.has_key(self):
- # clone already done & memoized
- return memo_dict[self]
- return self.__class__(_ancestor = self, **kwargs)
-
- def __getattr__(self, attr):
- if self._ports.has_key(attr):
- # return reference that can be assigned to another port
- # via __setattr__
- return self._ports[attr].makeRef(self, attr)
-
- if self._values.has_key(attr):
- return self._values[attr]
-
- raise AttributeError, "object '%s' has no attribute '%s'" \
- % (self.__class__.__name__, attr)
-
- # Set attribute (called on foo.attr = value when foo is an
- # instance of class cls).
- def __setattr__(self, attr, value):
- # normal processing for private attributes
- if attr.startswith('_'):
- object.__setattr__(self, attr, value)
- return
-
- if self._ports.has_key(attr):
- # set up port connection
- self._ports[attr].connect(self, attr, value)
- return
-
- if isSimObjectOrSequence(value) and self._instantiated:
- raise RuntimeError, \
- "cannot set SimObject parameter '%s' after\n" \
- " instance been cloned %s" % (attr, `self`)
-
- # must be SimObject param
- param = self._params.get(attr, None)
- if param:
- try:
- value = param.convert(value)
- except Exception, e:
- msg = "%s\nError setting param %s.%s to %s\n" % \
- (e, self.__class__.__name__, attr, value)
- e.args = (msg, )
- raise
- elif isSimObjectOrSequence(value):
- pass
- else:
- raise AttributeError, "Class %s has no parameter %s" \
- % (self.__class__.__name__, attr)
-
- # clear out old child with this name, if any
- self.clear_child(attr)
-
- if isSimObject(value):
- value.set_path(self, attr)
- elif isSimObjectSequence(value):
- value = SimObjVector(value)
- [v.set_path(self, "%s%d" % (attr, i)) for i,v in enumerate(value)]
-
- self._values[attr] = value
-
- # this hack allows tacking a '[0]' onto parameters that may or may
- # not be vectors, and always getting the first element (e.g. cpus)
- def __getitem__(self, key):
- if key == 0:
- return self
- raise TypeError, "Non-zero index '%s' to SimObject" % key
-
- # clear out children with given name, even if it's a vector
- def clear_child(self, name):
- if not self._children.has_key(name):
- return
- child = self._children[name]
- if isinstance(child, SimObjVector):
- for i in xrange(len(child)):
- del self._children["s%d" % (name, i)]
- del self._children[name]
-
- def add_child(self, name, value):
- self._children[name] = value
-
- def set_path(self, parent, name):
- if not self._parent:
- self._parent = parent
- self._name = name
- parent.add_child(name, self)
-
- def path(self):
- if not self._parent:
- return 'root'
- ppath = self._parent.path()
- if ppath == 'root':
- return self._name
- return ppath + "." + self._name
-
- def __str__(self):
- return self.path()
-
- def ini_str(self):
- return self.path()
-
- def find_any(self, ptype):
- if isinstance(self, ptype):
- return self, True
-
- found_obj = None
- for child in self._children.itervalues():
- if isinstance(child, ptype):
- if found_obj != None and child != found_obj:
- raise AttributeError, \
- 'parent.any matched more than one: %s %s' % \
- (found_obj.path, child.path)
- found_obj = child
- # search param space
- for pname,pdesc in self._params.iteritems():
- if issubclass(pdesc.ptype, ptype):
- match_obj = self._values[pname]
- if found_obj != None and found_obj != match_obj:
- raise AttributeError, \
- 'parent.any matched more than one: %s' % obj.path
- found_obj = match_obj
- return found_obj, found_obj != None
-
- def unproxy(self, base):
- return self
-
- def print_ini(self):
- print '[' + self.path() + ']' # .ini section header
-
- instanceDict[self.path()] = self
-
- if hasattr(self, 'type') and not isinstance(self, ParamContext):
- print 'type=%s' % self.type
-
- child_names = self._children.keys()
- child_names.sort()
- np_child_names = [c for c in child_names \
- if not isinstance(self._children[c], ParamContext)]
- if len(np_child_names):
- print 'children=%s' % ' '.join(np_child_names)
-
- param_names = self._params.keys()
- param_names.sort()
- for param in param_names:
- value = self._values.get(param, None)
- if value != None:
- if isproxy(value):
- try:
- value = value.unproxy(self)
- except:
- print >> sys.stderr, \
- "Error in unproxying param '%s' of %s" % \
- (param, self.path())
- raise
- setattr(self, param, value)
- print '%s=%s' % (param, self._values[param].ini_str())
-
- print # blank line between objects
-
- for child in child_names:
- self._children[child].print_ini()
-
- # Call C++ to create C++ object corresponding to this object and
- # (recursively) all its children
- def createCCObject(self):
- self.getCCObject() # force creation
- for child in self._children.itervalues():
- child.createCCObject()
-
- # Get C++ object corresponding to this object, calling C++ if
- # necessary to construct it. Does *not* recursively create
- # children.
- def getCCObject(self):
- if not self._ccObject:
- self._ccObject = -1 # flag to catch cycles in recursion
- self._ccObject = cc_main.createSimObject(self.path())
- elif self._ccObject == -1:
- raise RuntimeError, "%s: recursive call to getCCObject()" \
- % self.path()
- return self._ccObject
-
- # Create C++ port connections corresponding to the connections in
- # _port_map (& recursively for all children)
- def connectPorts(self):
- for portRef in self._port_map.itervalues():
- applyOrMap(portRef, 'ccConnect')
- for child in self._children.itervalues():
- child.connectPorts()
-
- def startDrain(self, drain_event, recursive):
- count = 0
- # ParamContexts don't serialize
- if isinstance(self, SimObject) and not isinstance(self, ParamContext):
- count += self._ccObject.drain(drain_event)
- if recursive:
- for child in self._children.itervalues():
- count += child.startDrain(drain_event, True)
- return count
-
- def resume(self):
- if isinstance(self, SimObject) and not isinstance(self, ParamContext):
- self._ccObject.resume()
- for child in self._children.itervalues():
- child.resume()
-
- def changeTiming(self, mode):
- if isinstance(self, System):
- self._ccObject.setMemoryMode(mode)
- for child in self._children.itervalues():
- child.changeTiming(mode)
-
- def takeOverFrom(self, old_cpu):
- cpu_ptr = cc_main.convertToBaseCPUPtr(old_cpu._ccObject)
- self._ccObject.takeOverFrom(cpu_ptr)
-
- # generate output file for 'dot' to display as a pretty graph.
- # this code is currently broken.
- def outputDot(self, dot):
- label = "{%s|" % self.path
- if isSimObject(self.realtype):
- label += '%s|' % self.type
-
- if self.children:
- # instantiate children in same order they were added for
- # backward compatibility (else we can end up with cpu1
- # before cpu0).
- for c in self.children:
- dot.add_edge(pydot.Edge(self.path,c.path, style="bold"))
-
- simobjs = []
- for param in self.params:
- try:
- if param.value is None:
- raise AttributeError, 'Parameter with no value'
-
- value = param.value
- string = param.string(value)
- except Exception, e:
- msg = 'exception in %s:%s\n%s' % (self.name, param.name, e)
- e.args = (msg, )
- raise
-
- if isSimObject(param.ptype) and string != "Null":
- simobjs.append(string)
- else:
- label += '%s = %s\\n' % (param.name, string)
-
- for so in simobjs:
- label += "|<%s> %s" % (so, so)
- dot.add_edge(pydot.Edge("%s:%s" % (self.path, so), so,
- tailport="w"))
- label += '}'
- dot.add_node(pydot.Node(self.path,shape="Mrecord",label=label))
-
- # recursively dump out children
- for c in self.children:
- c.outputDot(dot)
-
-class ParamContext(SimObject):
- pass
-
-#####################################################################
-#
-# Proxy object support.
-#
-#####################################################################
-
-class BaseProxy(object):
- def __init__(self, search_self, search_up):
- self._search_self = search_self
- self._search_up = search_up
- self._multiplier = None
-
- def __setattr__(self, attr, value):
- if not attr.startswith('_'):
- raise AttributeError, 'cannot set attribute on proxy object'
- super(BaseProxy, self).__setattr__(attr, value)
-
- # support multiplying proxies by constants
- def __mul__(self, other):
- if not isinstance(other, (int, long, float)):
- raise TypeError, "Proxy multiplier must be integer"
- if self._multiplier == None:
- self._multiplier = other
- else:
- # support chained multipliers
- self._multiplier *= other
- return self
-
- __rmul__ = __mul__
-
- def _mulcheck(self, result):
- if self._multiplier == None:
- return result
- return result * self._multiplier
-
- def unproxy(self, base):
- obj = base
- done = False
-
- if self._search_self:
- result, done = self.find(obj)
-
- if self._search_up:
- while not done:
- obj = obj._parent
- if not obj:
- break
- result, done = self.find(obj)
-
- if not done:
- raise AttributeError, \
- "Can't resolve proxy '%s' from '%s'" % \
- (self.path(), base.path())
-
- if isinstance(result, BaseProxy):
- if result == self:
- raise RuntimeError, "Cycle in unproxy"
- result = result.unproxy(obj)
-
- return self._mulcheck(result)
-
- def getindex(obj, index):
- if index == None:
- return obj
- try:
- obj = obj[index]
- except TypeError:
- if index != 0:
- raise
- # if index is 0 and item is not subscriptable, just
- # use item itself (so cpu[0] works on uniprocessors)
- return obj
- getindex = staticmethod(getindex)
-
- def set_param_desc(self, pdesc):
- self._pdesc = pdesc
-
-class AttrProxy(BaseProxy):
- def __init__(self, search_self, search_up, attr):
- super(AttrProxy, self).__init__(search_self, search_up)
- self._attr = attr
- self._modifiers = []
-
- def __getattr__(self, attr):
- # python uses __bases__ internally for inheritance
- if attr.startswith('_'):
- return super(AttrProxy, self).__getattr__(self, attr)
- if hasattr(self, '_pdesc'):
- raise AttributeError, "Attribute reference on bound proxy"
- self._modifiers.append(attr)
- return self
-
- # support indexing on proxies (e.g., Self.cpu[0])
- def __getitem__(self, key):
- if not isinstance(key, int):
- raise TypeError, "Proxy object requires integer index"
- self._modifiers.append(key)
- return self
-
- def find(self, obj):
- try:
- val = getattr(obj, self._attr)
- except:
- return None, False
- while isproxy(val):
- val = val.unproxy(obj)
- for m in self._modifiers:
- if isinstance(m, str):
- val = getattr(val, m)
- elif isinstance(m, int):
- val = val[m]
- else:
- assert("Item must be string or integer")
- while isproxy(val):
- val = val.unproxy(obj)
- return val, True
-
- def path(self):
- p = self._attr
- for m in self._modifiers:
- if isinstance(m, str):
- p += '.%s' % m
- elif isinstance(m, int):
- p += '[%d]' % m
- else:
- assert("Item must be string or integer")
- return p
-
-class AnyProxy(BaseProxy):
- def find(self, obj):
- return obj.find_any(self._pdesc.ptype)
-
- def path(self):
- return 'any'
-
-def isproxy(obj):
- if isinstance(obj, (BaseProxy, EthernetAddr)):
- return True
- elif isinstance(obj, (list, tuple)):
- for v in obj:
- if isproxy(v):
- return True
- return False
-
-class ProxyFactory(object):
- def __init__(self, search_self, search_up):
- self.search_self = search_self
- self.search_up = search_up
-
- def __getattr__(self, attr):
- if attr == 'any':
- return AnyProxy(self.search_self, self.search_up)
- else:
- return AttrProxy(self.search_self, self.search_up, attr)
-
-# global objects for handling proxies
-Parent = ProxyFactory(search_self = False, search_up = True)
-Self = ProxyFactory(search_self = True, search_up = False)
-
-#####################################################################
-#
-# Parameter description classes
-#
-# The _params dictionary in each class maps parameter names to either
-# a Param or a VectorParam object. These objects contain the
-# parameter description string, the parameter type, and the default
-# value (if any). The convert() method on these objects is used to
-# force whatever value is assigned to the parameter to the appropriate
-# type.
-#
-# Note that the default values are loaded into the class's attribute
-# space when the parameter dictionary is initialized (in
-# MetaSimObject._new_param()); after that point they aren't used.
-#
-#####################################################################
-
-# Dummy base class to identify types that are legitimate for SimObject
-# parameters.
-class ParamValue(object):
-
- # default for printing to .ini file is regular string conversion.
- # will be overridden in some cases
- def ini_str(self):
- return str(self)
-
- # allows us to blithely call unproxy() on things without checking
- # if they're really proxies or not
- def unproxy(self, base):
- return self
-
-# Regular parameter description.
-class ParamDesc(object):
- def __init__(self, ptype_str, ptype, *args, **kwargs):
- self.ptype_str = ptype_str
- # remember ptype only if it is provided
- if ptype != None:
- self.ptype = ptype
-
- if args:
- if len(args) == 1:
- self.desc = args[0]
- elif len(args) == 2:
- self.default = args[0]
- self.desc = args[1]
- else:
- raise TypeError, 'too many arguments'
-
- if kwargs.has_key('desc'):
- assert(not hasattr(self, 'desc'))
- self.desc = kwargs['desc']
- del kwargs['desc']
-
- if kwargs.has_key('default'):
- assert(not hasattr(self, 'default'))
- self.default = kwargs['default']
- del kwargs['default']
-
- if kwargs:
- raise TypeError, 'extra unknown kwargs %s' % kwargs
-
- if not hasattr(self, 'desc'):
- raise TypeError, 'desc attribute missing'
-
- def __getattr__(self, attr):
- if attr == 'ptype':
- try:
- ptype = eval(self.ptype_str, m5.objects.__dict__)
- if not isinstance(ptype, type):
- panic("Param qualifier is not a type: %s" % self.ptype)
- self.ptype = ptype
- return ptype
- except NameError:
- pass
- raise AttributeError, "'%s' object has no attribute '%s'" % \
- (type(self).__name__, attr)
-
- def convert(self, value):
- if isinstance(value, BaseProxy):
- value.set_param_desc(self)
- return value
- if not hasattr(self, 'ptype') and isNullPointer(value):
- # deferred evaluation of SimObject; continue to defer if
- # we're just assigning a null pointer
- return value
- if isinstance(value, self.ptype):
- return value
- if isNullPointer(value) and issubclass(self.ptype, SimObject):
- return value
- return self.ptype(value)
-
-# Vector-valued parameter description. Just like ParamDesc, except
-# that the value is a vector (list) of the specified type instead of a
-# single value.
-
-class VectorParamValue(list):
- def ini_str(self):
- return ' '.join([v.ini_str() for v in self])
-
- def unproxy(self, base):
- return [v.unproxy(base) for v in self]
-
-class SimObjVector(VectorParamValue):
- def print_ini(self):
- for v in self:
- v.print_ini()
-
-class VectorParamDesc(ParamDesc):
- # Convert assigned value to appropriate type. If the RHS is not a
- # list or tuple, it generates a single-element list.
- def convert(self, value):
- if isinstance(value, (list, tuple)):
- # list: coerce each element into new list
- tmp_list = [ ParamDesc.convert(self, v) for v in value ]
- if isSimObjectSequence(tmp_list):
- return SimObjVector(tmp_list)
- else:
- return VectorParamValue(tmp_list)
- else:
- # singleton: leave it be (could coerce to a single-element
- # list here, but for some historical reason we don't...
- return ParamDesc.convert(self, value)
-
-
-class ParamFactory(object):
- def __init__(self, param_desc_class, ptype_str = None):
- self.param_desc_class = param_desc_class
- self.ptype_str = ptype_str
-
- def __getattr__(self, attr):
- if self.ptype_str:
- attr = self.ptype_str + '.' + attr
- return ParamFactory(self.param_desc_class, attr)
-
- # E.g., Param.Int(5, "number of widgets")
- def __call__(self, *args, **kwargs):
- caller_frame = inspect.currentframe().f_back
- ptype = None
- try:
- ptype = eval(self.ptype_str,
- caller_frame.f_globals, caller_frame.f_locals)
- if not isinstance(ptype, type):
- raise TypeError, \
- "Param qualifier is not a type: %s" % ptype
- except NameError:
- # if name isn't defined yet, assume it's a SimObject, and
- # try to resolve it later
- pass
- return self.param_desc_class(self.ptype_str, ptype, *args, **kwargs)
-
-Param = ParamFactory(ParamDesc)
-VectorParam = ParamFactory(VectorParamDesc)
-
-#####################################################################
-#
-# Parameter Types
-#
-# Though native Python types could be used to specify parameter types
-# (the 'ptype' field of the Param and VectorParam classes), it's more
-# flexible to define our own set of types. This gives us more control
-# over how Python expressions are converted to values (via the
-# __init__() constructor) and how these values are printed out (via
-# the __str__() conversion method). Eventually we'll need these types
-# to correspond to distinct C++ types as well.
-#
-#####################################################################
-
-# superclass for "numeric" parameter values, to emulate math
-# operations in a type-safe way. e.g., a Latency times an int returns
-# a new Latency object.
-class NumericParamValue(ParamValue):
- def __str__(self):
- return str(self.value)
-
- def __float__(self):
- return float(self.value)
-
- # hook for bounds checking
- def _check(self):
- return
-
- def __mul__(self, other):
- newobj = self.__class__(self)
- newobj.value *= other
- newobj._check()
- return newobj
-
- __rmul__ = __mul__
-
- def __div__(self, other):
- newobj = self.__class__(self)
- newobj.value /= other
- newobj._check()
- return newobj
-
- def __sub__(self, other):
- newobj = self.__class__(self)
- newobj.value -= other
- newobj._check()
- return newobj
-
-class Range(ParamValue):
- type = int # default; can be overridden in subclasses
- def __init__(self, *args, **kwargs):
-
- def handle_kwargs(self, kwargs):
- if 'end' in kwargs:
- self.second = self.type(kwargs.pop('end'))
- elif 'size' in kwargs:
- self.second = self.first + self.type(kwargs.pop('size')) - 1
- else:
- raise TypeError, "Either end or size must be specified"
-
- if len(args) == 0:
- self.first = self.type(kwargs.pop('start'))
- handle_kwargs(self, kwargs)
-
- elif len(args) == 1:
- if kwargs:
- self.first = self.type(args[0])
- handle_kwargs(self, kwargs)
- elif isinstance(args[0], Range):
- self.first = self.type(args[0].first)
- self.second = self.type(args[0].second)
- else:
- self.first = self.type(0)
- self.second = self.type(args[0]) - 1
-
- elif len(args) == 2:
- self.first = self.type(args[0])
- self.second = self.type(args[1])
- else:
- raise TypeError, "Too many arguments specified"
-
- if kwargs:
- raise TypeError, "too many keywords: %s" % kwargs.keys()
-
- def __str__(self):
- return '%s:%s' % (self.first, self.second)
-
-# Metaclass for bounds-checked integer parameters. See CheckedInt.
-class CheckedIntType(type):
- def __init__(cls, name, bases, dict):
- super(CheckedIntType, cls).__init__(name, bases, dict)
-
- # CheckedInt is an abstract base class, so we actually don't
- # want to do any processing on it... the rest of this code is
- # just for classes that derive from CheckedInt.
- if name == 'CheckedInt':
- return
-
- if not (hasattr(cls, 'min') and hasattr(cls, 'max')):
- if not (hasattr(cls, 'size') and hasattr(cls, 'unsigned')):
- panic("CheckedInt subclass %s must define either\n" \
- " 'min' and 'max' or 'size' and 'unsigned'\n" \
- % name);
- if cls.unsigned:
- cls.min = 0
- cls.max = 2 ** cls.size - 1
- else:
- cls.min = -(2 ** (cls.size - 1))
- cls.max = (2 ** (cls.size - 1)) - 1
-
-# Abstract superclass for bounds-checked integer parameters. This
-# class is subclassed to generate parameter classes with specific
-# bounds. Initialization of the min and max bounds is done in the
-# metaclass CheckedIntType.__init__.
-class CheckedInt(NumericParamValue):
- __metaclass__ = CheckedIntType
-
- def _check(self):
- if not self.min <= self.value <= self.max:
- raise TypeError, 'Integer param out of bounds %d < %d < %d' % \
- (self.min, self.value, self.max)
-
- def __init__(self, value):
- if isinstance(value, str):
- self.value = toInteger(value)
- elif isinstance(value, (int, long, float)):
- self.value = long(value)
- self._check()
-
-class Int(CheckedInt): size = 32; unsigned = False
-class Unsigned(CheckedInt): size = 32; unsigned = True
-
-class Int8(CheckedInt): size = 8; unsigned = False
-class UInt8(CheckedInt): size = 8; unsigned = True
-class Int16(CheckedInt): size = 16; unsigned = False
-class UInt16(CheckedInt): size = 16; unsigned = True
-class Int32(CheckedInt): size = 32; unsigned = False
-class UInt32(CheckedInt): size = 32; unsigned = True
-class Int64(CheckedInt): size = 64; unsigned = False
-class UInt64(CheckedInt): size = 64; unsigned = True
-
-class Counter(CheckedInt): size = 64; unsigned = True
-class Tick(CheckedInt): size = 64; unsigned = True
-class TcpPort(CheckedInt): size = 16; unsigned = True
-class UdpPort(CheckedInt): size = 16; unsigned = True
-
-class Percent(CheckedInt): min = 0; max = 100
-
-class Float(ParamValue, float):
- pass
-
-class MemorySize(CheckedInt):
- size = 64
- unsigned = True
- def __init__(self, value):
- if isinstance(value, MemorySize):
- self.value = value.value
- else:
- self.value = toMemorySize(value)
- self._check()
-
-class MemorySize32(CheckedInt):
- size = 32
- unsigned = True
- def __init__(self, value):
- if isinstance(value, MemorySize):
- self.value = value.value
- else:
- self.value = toMemorySize(value)
- self._check()
-
-class Addr(CheckedInt):
- size = 64
- unsigned = True
- def __init__(self, value):
- if isinstance(value, Addr):
- self.value = value.value
- else:
- try:
- self.value = toMemorySize(value)
- except TypeError:
- self.value = long(value)
- self._check()
-
-class AddrRange(Range):
- type = Addr
-
-# String-valued parameter. Just mixin the ParamValue class
-# with the built-in str class.
-class String(ParamValue,str):
- pass
-
-# Boolean parameter type. Python doesn't let you subclass bool, since
-# it doesn't want to let you create multiple instances of True and
-# False. Thus this is a little more complicated than String.
-class Bool(ParamValue):
- def __init__(self, value):
- try:
- self.value = toBool(value)
- except TypeError:
- self.value = bool(value)
-
- def __str__(self):
- return str(self.value)
-
- def ini_str(self):
- if self.value:
- return 'true'
- return 'false'
-
-def IncEthernetAddr(addr, val = 1):
- bytes = map(lambda x: int(x, 16), addr.split(':'))
- bytes[5] += val
- for i in (5, 4, 3, 2, 1):
- val,rem = divmod(bytes[i], 256)
- bytes[i] = rem
- if val == 0:
- break
- bytes[i - 1] += val
- assert(bytes[0] <= 255)
- return ':'.join(map(lambda x: '%02x' % x, bytes))
-
-class NextEthernetAddr(object):
- addr = "00:90:00:00:00:01"
-
- def __init__(self, inc = 1):
- self.value = NextEthernetAddr.addr
- NextEthernetAddr.addr = IncEthernetAddr(NextEthernetAddr.addr, inc)
-
-class EthernetAddr(ParamValue):
- def __init__(self, value):
- if value == NextEthernetAddr:
- self.value = value
- return
-
- if not isinstance(value, str):
- raise TypeError, "expected an ethernet address and didn't get one"
-
- bytes = value.split(':')
- if len(bytes) != 6:
- raise TypeError, 'invalid ethernet address %s' % value
-
- for byte in bytes:
- if not 0 <= int(byte) <= 256:
- raise TypeError, 'invalid ethernet address %s' % value
-
- self.value = value
-
- def unproxy(self, base):
- if self.value == NextEthernetAddr:
- self.addr = self.value().value
- return self
-
- def __str__(self):
- if self.value == NextEthernetAddr:
- if hasattr(self, 'addr'):
- return self.addr
- else:
- return "NextEthernetAddr (unresolved)"
- else:
- return self.value
-
-# Special class for NULL pointers. Note the special check in
-# make_param_value() above that lets these be assigned where a
-# SimObject is required.
-# only one copy of a particular node
-class NullSimObject(object):
- __metaclass__ = Singleton
-
- def __call__(cls):
- return cls
-
- def _instantiate(self, parent = None, path = ''):
- pass
-
- def ini_str(self):
- return 'Null'
-
- def unproxy(self, base):
- return self
-
- def set_path(self, parent, name):
- pass
- def __str__(self):
- return 'Null'
-
-# The only instance you'll ever need...
-Null = NULL = NullSimObject()
-
-# Enumerated types are a little more complex. The user specifies the
-# type as Enum(foo) where foo is either a list or dictionary of
-# alternatives (typically strings, but not necessarily so). (In the
-# long run, the integer value of the parameter will be the list index
-# or the corresponding dictionary value. For now, since we only check
-# that the alternative is valid and then spit it into a .ini file,
-# there's not much point in using the dictionary.)
-
-# What Enum() must do is generate a new type encapsulating the
-# provided list/dictionary so that specific values of the parameter
-# can be instances of that type. We define two hidden internal
-# classes (_ListEnum and _DictEnum) to serve as base classes, then
-# derive the new type from the appropriate base class on the fly.
-
-
-# Metaclass for Enum types
-class MetaEnum(type):
- def __init__(cls, name, bases, init_dict):
- if init_dict.has_key('map'):
- if not isinstance(cls.map, dict):
- raise TypeError, "Enum-derived class attribute 'map' " \
- "must be of type dict"
- # build list of value strings from map
- cls.vals = cls.map.keys()
- cls.vals.sort()
- elif init_dict.has_key('vals'):
- if not isinstance(cls.vals, list):
- raise TypeError, "Enum-derived class attribute 'vals' " \
- "must be of type list"
- # build string->value map from vals sequence
- cls.map = {}
- for idx,val in enumerate(cls.vals):
- cls.map[val] = idx
- else:
- raise TypeError, "Enum-derived class must define "\
- "attribute 'map' or 'vals'"
-
- super(MetaEnum, cls).__init__(name, bases, init_dict)
-
- def cpp_declare(cls):
- s = 'enum %s {\n ' % cls.__name__
- s += ',\n '.join(['%s = %d' % (v,cls.map[v]) for v in cls.vals])
- s += '\n};\n'
- return s
-
-# Base class for enum types.
-class Enum(ParamValue):
- __metaclass__ = MetaEnum
- vals = []
-
- def __init__(self, value):
- if value not in self.map:
- raise TypeError, "Enum param got bad value '%s' (not in %s)" \
- % (value, self.vals)
- self.value = value
-
- def __str__(self):
- return self.value
-
-ticks_per_sec = None
-
-# how big does a rounding error need to be before we warn about it?
-frequency_tolerance = 0.001 # 0.1%
-
-# convert a floting-point # of ticks to integer, and warn if rounding
-# discards too much precision
-def tick_check(float_ticks):
- if float_ticks == 0:
- return 0
- int_ticks = int(round(float_ticks))
- err = (float_ticks - int_ticks) / float_ticks
- if err > frequency_tolerance:
- print >> sys.stderr, "Warning: rounding error > tolerance"
- print >> sys.stderr, " %f rounded to %d" % (float_ticks, int_ticks)
- #raise ValueError
- return int_ticks
-
-def getLatency(value):
- if isinstance(value, Latency) or isinstance(value, Clock):
- return value.value
- elif isinstance(value, Frequency) or isinstance(value, RootClock):
- return 1 / value.value
- elif isinstance(value, str):
- try:
- return toLatency(value)
- except ValueError:
- try:
- return 1 / toFrequency(value)
- except ValueError:
- pass # fall through
- raise ValueError, "Invalid Frequency/Latency value '%s'" % value
-
-
-class Latency(NumericParamValue):
- def __init__(self, value):
- self.value = getLatency(value)
-
- def __getattr__(self, attr):
- if attr in ('latency', 'period'):
- return self
- if attr == 'frequency':
- return Frequency(self)
- raise AttributeError, "Latency object has no attribute '%s'" % attr
-
- # convert latency to ticks
- def ini_str(self):
- return str(tick_check(self.value * ticks_per_sec))
-
-class Frequency(NumericParamValue):
- def __init__(self, value):
- self.value = 1 / getLatency(value)
-
- def __getattr__(self, attr):
- if attr == 'frequency':
- return self
- if attr in ('latency', 'period'):
- return Latency(self)
- raise AttributeError, "Frequency object has no attribute '%s'" % attr
-
- # convert frequency to ticks per period
- def ini_str(self):
- return self.period.ini_str()
-
-# Just like Frequency, except ini_str() is absolute # of ticks per sec (Hz).
-# We can't inherit from Frequency because we don't want it to be directly
-# assignable to a regular Frequency parameter.
-class RootClock(ParamValue):
- def __init__(self, value):
- self.value = 1 / getLatency(value)
-
- def __getattr__(self, attr):
- if attr == 'frequency':
- return Frequency(self)
- if attr in ('latency', 'period'):
- return Latency(self)
- raise AttributeError, "Frequency object has no attribute '%s'" % attr
-
- def ini_str(self):
- return str(tick_check(self.value))
-
-# A generic frequency and/or Latency value. Value is stored as a latency,
-# but to avoid ambiguity this object does not support numeric ops (* or /).
-# An explicit conversion to a Latency or Frequency must be made first.
-class Clock(ParamValue):
- def __init__(self, value):
- self.value = getLatency(value)
-
- def __getattr__(self, attr):
- if attr == 'frequency':
- return Frequency(self)
- if attr in ('latency', 'period'):
- return Latency(self)
- raise AttributeError, "Frequency object has no attribute '%s'" % attr
-
- def ini_str(self):
- return self.period.ini_str()
-
-class NetworkBandwidth(float,ParamValue):
- def __new__(cls, value):
- val = toNetworkBandwidth(value) / 8.0
- return super(cls, NetworkBandwidth).__new__(cls, val)
-
- def __str__(self):
- return str(self.val)
-
- def ini_str(self):
- return '%f' % (ticks_per_sec / float(self))
-
-class MemoryBandwidth(float,ParamValue):
- def __new__(self, value):
- val = toMemoryBandwidth(value)
- return super(cls, MemoryBandwidth).__new__(cls, val)
-
- def __str__(self):
- return str(self.val)
-
- def ini_str(self):
- return '%f' % (ticks_per_sec / float(self))
-
-#
-# "Constants"... handy aliases for various values.
-#
-
-# Some memory range specifications use this as a default upper bound.
-MaxAddr = Addr.max
-MaxTick = Tick.max
-AllMemory = AddrRange(0, MaxAddr)
-
-
-#####################################################################
-#
-# Port objects
-#
-# Ports are used to interconnect objects in the memory system.
-#
-#####################################################################
-
-# Port reference: encapsulates a reference to a particular port on a
-# particular SimObject.
-class PortRef(object):
- def __init__(self, simobj, name, isVec):
- assert(isSimObject(simobj))
- self.simobj = simobj
- self.name = name
- self.index = -1
- self.isVec = isVec # is this a vector port?
- self.peer = None # not associated with another port yet
- self.ccConnected = False # C++ port connection done?
-
- # Set peer port reference. Called via __setattr__ as a result of
- # a port assignment, e.g., "obj1.port1 = obj2.port2".
- def setPeer(self, other):
- if self.isVec:
- curMap = self.simobj._port_map.get(self.name, [])
- self.index = len(curMap)
- curMap.append(other)
- else:
- curMap = self.simobj._port_map.get(self.name)
- if curMap and not self.isVec:
- print "warning: overwriting port", self.simobj, self.name
- curMap = other
- self.simobj._port_map[self.name] = curMap
- self.peer = other
-
- def clone(self, memo):
- newRef = copy.copy(self)
- assert(isSimObject(newRef.simobj))
- newRef.simobj = newRef.simobj(_memo=memo)
- # Tricky: if I'm the *second* PortRef in the pair to be
- # cloned, then my peer is still in the middle of its clone
- # method, and thus hasn't returned to its owner's
- # SimObject.__init__ to get installed in _port_map. As a
- # result I have no way of finding the *new* peer object. So I
- # mark myself as "waiting" for my peer, and I let the *first*
- # PortRef clone call set up both peer pointers after I return.
- newPeer = newRef.simobj._port_map.get(self.name)
- if newPeer:
- if self.isVec:
- assert(self.index != -1)
- newPeer = newPeer[self.index]
- # other guy is all set up except for his peer pointer
- assert(newPeer.peer == -1) # peer must be waiting for handshake
- newPeer.peer = newRef
- newRef.peer = newPeer
- else:
- # other guy is in clone; just wait for him to do the work
- newRef.peer = -1 # mark as waiting for handshake
- return newRef
-
- # Call C++ to create corresponding port connection between C++ objects
- def ccConnect(self):
- if self.ccConnected: # already done this
- return
- peer = self.peer
- cc_main.connectPorts(self.simobj.getCCObject(), self.name, self.index,
- peer.simobj.getCCObject(), peer.name, peer.index)
- self.ccConnected = True
- peer.ccConnected = True
-
-# Port description object. Like a ParamDesc object, this represents a
-# logical port in the SimObject class, not a particular port on a
-# SimObject instance. The latter are represented by PortRef objects.
-class Port(object):
- def __init__(self, desc):
- self.desc = desc
- self.isVec = False
-
- # Generate a PortRef for this port on the given SimObject with the
- # given name
- def makeRef(self, simobj, name):
- return PortRef(simobj, name, self.isVec)
-
- # Connect an instance of this port (on the given SimObject with
- # the given name) with the port described by the supplied PortRef
- def connect(self, simobj, name, ref):
- if not isinstance(ref, PortRef):
- raise TypeError, \
- "assigning non-port reference port '%s'" % name
- myRef = self.makeRef(simobj, name)
- myRef.setPeer(ref)
- ref.setPeer(myRef)
-
-# VectorPort description object. Like Port, but represents a vector
-# of connections (e.g., as on a Bus).
-class VectorPort(Port):
- def __init__(self, desc):
- Port.__init__(self, desc)
- self.isVec = True
-
-#####################################################################
-
-# __all__ defines the list of symbols that get exported when
-# 'from config import *' is invoked. Try to keep this reasonably
-# short to avoid polluting other namespaces.
-__all__ = ['SimObject', 'ParamContext', 'Param', 'VectorParam',
- 'Parent', 'Self',
- 'Enum', 'Bool', 'String', 'Float',
- 'Int', 'Unsigned', 'Int8', 'UInt8', 'Int16', 'UInt16',
- 'Int32', 'UInt32', 'Int64', 'UInt64',
- 'Counter', 'Addr', 'Tick', 'Percent',
- 'TcpPort', 'UdpPort', 'EthernetAddr',
- 'MemorySize', 'MemorySize32',
- 'Latency', 'Frequency', 'RootClock', 'Clock',
- 'NetworkBandwidth', 'MemoryBandwidth',
- 'Range', 'AddrRange', 'MaxAddr', 'MaxTick', 'AllMemory',
- 'Null', 'NULL',
- 'NextEthernetAddr',
- 'Port', 'VectorPort']
-
diff --git a/src/python/m5/multidict.py b/src/python/m5/multidict.py
index 34fc313..b5cd700 100644
--- a/src/python/m5/multidict.py
+++ b/src/python/m5/multidict.py
@@ -29,7 +29,6 @@
__all__ = [ 'multidict' ]
class multidict(object):
- __nodefault = object()
def __init__(self, parent = {}, **kwargs):
self.local = dict(**kwargs)
self.parent = parent
@@ -102,14 +101,11 @@
def values(self):
return [ value for key,value in self.next() ]
- def get(self, key, default=__nodefault):
+ def get(self, key, default=None):
try:
return self[key]
except KeyError, e:
- if default != self.__nodefault:
- return default
- else:
- raise KeyError, e
+ return default
def setdefault(self, key, default):
try:
diff --git a/src/python/m5/objects/AlphaConsole.py b/src/python/m5/objects/AlphaConsole.py
index 329b8c5..1c71493 100644
--- a/src/python/m5/objects/AlphaConsole.py
+++ b/src/python/m5/objects/AlphaConsole.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.params import *
+from m5.proxy import *
from Device import BasicPioDevice
class AlphaConsole(BasicPioDevice):
diff --git a/src/python/m5/objects/AlphaTLB.py b/src/python/m5/objects/AlphaTLB.py
index 11c1792..af7c04a 100644
--- a/src/python/m5/objects/AlphaTLB.py
+++ b/src/python/m5/objects/AlphaTLB.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
class AlphaTLB(SimObject):
type = 'AlphaTLB'
abstract = True
diff --git a/src/python/m5/objects/BadDevice.py b/src/python/m5/objects/BadDevice.py
index 186b733..9196238 100644
--- a/src/python/m5/objects/BadDevice.py
+++ b/src/python/m5/objects/BadDevice.py
@@ -1,4 +1,4 @@
-from m5.config import *
+from m5.params import *
from Device import BasicPioDevice
class BadDevice(BasicPioDevice):
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 41e90b1..3dd0bda 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -1,5 +1,7 @@
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
from m5 import build_env
-from m5.config import *
from AlphaTLB import AlphaDTB, AlphaITB
from Bus import Bus
diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py
index 497b2b0..db58a17 100644
--- a/src/python/m5/objects/BaseCache.py
+++ b/src/python/m5/objects/BaseCache.py
@@ -1,4 +1,4 @@
-from m5.config import *
+from m5.params import *
from MemObject import MemObject
class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py
index c9e673a..ee8e76b 100644
--- a/src/python/m5/objects/Bridge.py
+++ b/src/python/m5/objects/Bridge.py
@@ -1,4 +1,4 @@
-from m5.config import *
+from m5.params import *
from MemObject import MemObject
class Bridge(MemObject):
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py
index e0278e6..f6828a0 100644
--- a/src/python/m5/objects/Bus.py
+++ b/src/python/m5/objects/Bus.py
@@ -1,4 +1,4 @@
-from m5.config import *
+from m5.params import *
from MemObject import MemObject
class Bus(MemObject):
diff --git a/src/python/m5/objects/CoherenceProtocol.py b/src/python/m5/objects/CoherenceProtocol.py
index 64b6cba..82adb68 100644
--- a/src/python/m5/objects/CoherenceProtocol.py
+++ b/src/python/m5/objects/CoherenceProtocol.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi']
class CoherenceProtocol(SimObject):
diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py
index f72c8e7..4672d10 100644
--- a/src/python/m5/objects/Device.py
+++ b/src/python/m5/objects/Device.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.params import *
+from m5.proxy import *
from MemObject import MemObject
class PioDevice(MemObject):
@@ -17,4 +18,4 @@
class DmaDevice(PioDevice):
type = 'DmaDevice'
abstract = True
- dma = Port("DMA port")
+ dma = Port(Self.pio.peerObj.port, "DMA port")
diff --git a/src/python/m5/objects/DiskImage.py b/src/python/m5/objects/DiskImage.py
index a98b35a..d0ada7e 100644
--- a/src/python/m5/objects/DiskImage.py
+++ b/src/python/m5/objects/DiskImage.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
class DiskImage(SimObject):
type = 'DiskImage'
abstract = True
diff --git a/src/python/m5/objects/Ethernet.py b/src/python/m5/objects/Ethernet.py
index fb641bf..609a3dd 100644
--- a/src/python/m5/objects/Ethernet.py
+++ b/src/python/m5/objects/Ethernet.py
@@ -1,5 +1,7 @@
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
from m5 import build_env
-from m5.config import *
from Device import DmaDevice
from Pci import PciDevice, PciConfigData
diff --git a/src/python/m5/objects/FUPool.py b/src/python/m5/objects/FUPool.py
index cbf1089..4b4be79 100644
--- a/src/python/m5/objects/FUPool.py
+++ b/src/python/m5/objects/FUPool.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
class FUPool(SimObject):
type = 'FUPool'
diff --git a/src/python/m5/objects/FuncUnit.py b/src/python/m5/objects/FuncUnit.py
index f61590a..f0ad55f 100644
--- a/src/python/m5/objects/FuncUnit.py
+++ b/src/python/m5/objects/FuncUnit.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
class OpType(Enum):
vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
diff --git a/src/python/m5/objects/Ide.py b/src/python/m5/objects/Ide.py
index a8bd4ac..69681bd 100644
--- a/src/python/m5/objects/Ide.py
+++ b/src/python/m5/objects/Ide.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
from Pci import PciDevice, PciConfigData
class IdeID(Enum): vals = ['master', 'slave']
diff --git a/src/python/m5/objects/IntrControl.py b/src/python/m5/objects/IntrControl.py
index 514c3fc..95be0f4 100644
--- a/src/python/m5/objects/IntrControl.py
+++ b/src/python/m5/objects/IntrControl.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
class IntrControl(SimObject):
type = 'IntrControl'
cpu = Param.BaseCPU(Parent.any, "the cpu")
diff --git a/src/python/m5/objects/MemObject.py b/src/python/m5/objects/MemObject.py
index d957dae..8982d55 100644
--- a/src/python/m5/objects/MemObject.py
+++ b/src/python/m5/objects/MemObject.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.SimObject import SimObject
class MemObject(SimObject):
type = 'MemObject'
diff --git a/src/python/m5/objects/MemTest.py b/src/python/m5/objects/MemTest.py
index 9916d7c..9760076 100644
--- a/src/python/m5/objects/MemTest.py
+++ b/src/python/m5/objects/MemTest.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
class MemTest(SimObject):
type = 'MemTest'
cache = Param.BaseCache("L1 cache")
diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py
index 900bbf2..5100c7c 100644
--- a/src/python/m5/objects/O3CPU.py
+++ b/src/python/m5/objects/O3CPU.py
@@ -1,5 +1,6 @@
+from m5.params import *
+from m5.proxy import *
from m5 import build_env
-from m5.config import *
from BaseCPU import BaseCPU
from Checker import O3Checker
diff --git a/src/python/m5/objects/OzoneCPU.py b/src/python/m5/objects/OzoneCPU.py
index 88fb63c..8f25d77 100644
--- a/src/python/m5/objects/OzoneCPU.py
+++ b/src/python/m5/objects/OzoneCPU.py
@@ -1,5 +1,5 @@
+from m5.params import *
from m5 import build_env
-from m5.config import *
from BaseCPU import BaseCPU
class DerivOzoneCPU(BaseCPU):
diff --git a/src/python/m5/objects/Pci.py b/src/python/m5/objects/Pci.py
index cc0d1cf..9872532 100644
--- a/src/python/m5/objects/Pci.py
+++ b/src/python/m5/objects/Pci.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
from Device import BasicPioDevice, DmaDevice, PioDevice
class PciConfigData(SimObject):
@@ -48,7 +50,7 @@
class PciDevice(DmaDevice):
type = 'PciDevice'
abstract = True
- config = Port("PCI configuration space port")
+ config = Port(Self.pio.peerObj.port, "PCI configuration space port")
pci_bus = Param.Int("PCI bus")
pci_dev = Param.Int("PCI device number")
pci_func = Param.Int("PCI function code")
diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py
index bc427aa..dd3ffd6 100644
--- a/src/python/m5/objects/PhysicalMemory.py
+++ b/src/python/m5/objects/PhysicalMemory.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.params import *
+from m5.proxy import *
from MemObject import *
class PhysicalMemory(MemObject):
diff --git a/src/python/m5/objects/Platform.py b/src/python/m5/objects/Platform.py
index 89fee99..ab2083e 100644
--- a/src/python/m5/objects/Platform.py
+++ b/src/python/m5/objects/Platform.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
class Platform(SimObject):
type = 'Platform'
abstract = True
diff --git a/src/python/m5/objects/Process.py b/src/python/m5/objects/Process.py
index 0091d86..08f8b6b 100644
--- a/src/python/m5/objects/Process.py
+++ b/src/python/m5/objects/Process.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
class Process(SimObject):
type = 'Process'
abstract = True
diff --git a/src/python/m5/objects/Repl.py b/src/python/m5/objects/Repl.py
index 8e9f109..10892cf 100644
--- a/src/python/m5/objects/Repl.py
+++ b/src/python/m5/objects/Repl.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
class Repl(SimObject):
type = 'Repl'
abstract = True
diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py
index 33dd226..f01fc06 100644
--- a/src/python/m5/objects/Root.py
+++ b/src/python/m5/objects/Root.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
from Serialize import Serialize
from Statistics import Statistics
from Trace import Trace
diff --git a/src/python/m5/objects/SimConsole.py b/src/python/m5/objects/SimConsole.py
index 9e1452c..bdd7f24 100644
--- a/src/python/m5/objects/SimConsole.py
+++ b/src/python/m5/objects/SimConsole.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
class ConsoleListener(SimObject):
type = 'ConsoleListener'
port = Param.TcpPort(3456, "listen port")
diff --git a/src/python/m5/objects/SimpleDisk.py b/src/python/m5/objects/SimpleDisk.py
index 44ef709..099a77d 100644
--- a/src/python/m5/objects/SimpleDisk.py
+++ b/src/python/m5/objects/SimpleDisk.py
@@ -1,4 +1,6 @@
-from m5.config import *
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
class SimpleDisk(SimObject):
type = 'SimpleDisk'
disk = Param.DiskImage("Disk Image")
diff --git a/src/python/m5/objects/SimpleOzoneCPU.py b/src/python/m5/objects/SimpleOzoneCPU.py
index 5d968ca..193f31b 100644
--- a/src/python/m5/objects/SimpleOzoneCPU.py
+++ b/src/python/m5/objects/SimpleOzoneCPU.py
@@ -1,5 +1,5 @@
+from m5.params import *
from m5 import build_env
-from m5.config import *
from BaseCPU import BaseCPU
class SimpleOzoneCPU(BaseCPU):
diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py
index 386f392..bc2a002 100644
--- a/src/python/m5/objects/System.py
+++ b/src/python/m5/objects/System.py
@@ -1,5 +1,7 @@
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
from m5 import build_env
-from m5.config import *
class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py
index 0b5ff9e..0b53153 100644
--- a/src/python/m5/objects/Tsunami.py
+++ b/src/python/m5/objects/Tsunami.py
@@ -1,4 +1,5 @@
-from m5.config import *
+from m5.params import *
+from m5.proxy import *
from Device import BasicPioDevice
from Platform import Platform
from AlphaConsole import AlphaConsole
diff --git a/src/python/m5/objects/Uart.py b/src/python/m5/objects/Uart.py
index 8e1fd1a..62062c6 100644
--- a/src/python/m5/objects/Uart.py
+++ b/src/python/m5/objects/Uart.py
@@ -1,5 +1,6 @@
+from m5.params import *
+from m5.proxy import *
from m5 import build_env
-from m5.config import *
from Device import BasicPioDevice
class Uart(BasicPioDevice):
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
new file mode 100644
index 0000000..cbbd230
--- /dev/null
+++ b/src/python/m5/params.py
@@ -0,0 +1,968 @@
+# Copyright (c) 2004-2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+# Nathan Binkert
+
+#####################################################################
+#
+# Parameter description classes
+#
+# The _params dictionary in each class maps parameter names to either
+# a Param or a VectorParam object. These objects contain the
+# parameter description string, the parameter type, and the default
+# value (if any). The convert() method on these objects is used to
+# force whatever value is assigned to the parameter to the appropriate
+# type.
+#
+# Note that the default values are loaded into the class's attribute
+# space when the parameter dictionary is initialized (in
+# MetaSimObject._new_param()); after that point they aren't used.
+#
+#####################################################################
+
+import sys, inspect, copy
+import convert
+from util import *
+
+# Dummy base class to identify types that are legitimate for SimObject
+# parameters.
+class ParamValue(object):
+
+ cxx_predecls = []
+ swig_predecls = []
+
+ # default for printing to .ini file is regular string conversion.
+ # will be overridden in some cases
+ def ini_str(self):
+ return str(self)
+
+ # allows us to blithely call unproxy() on things without checking
+ # if they're really proxies or not
+ def unproxy(self, base):
+ return self
+
+# Regular parameter description.
+class ParamDesc(object):
+ def __init__(self, ptype_str, ptype, *args, **kwargs):
+ self.ptype_str = ptype_str
+ # remember ptype only if it is provided
+ if ptype != None:
+ self.ptype = ptype
+
+ if args:
+ if len(args) == 1:
+ self.desc = args[0]
+ elif len(args) == 2:
+ self.default = args[0]
+ self.desc = args[1]
+ else:
+ raise TypeError, 'too many arguments'
+
+ if kwargs.has_key('desc'):
+ assert(not hasattr(self, 'desc'))
+ self.desc = kwargs['desc']
+ del kwargs['desc']
+
+ if kwargs.has_key('default'):
+ assert(not hasattr(self, 'default'))
+ self.default = kwargs['default']
+ del kwargs['default']
+
+ if kwargs:
+ raise TypeError, 'extra unknown kwargs %s' % kwargs
+
+ if not hasattr(self, 'desc'):
+ raise TypeError, 'desc attribute missing'
+
+ def __getattr__(self, attr):
+ if attr == 'ptype':
+ try:
+ ptype = eval(self.ptype_str, objects.__dict__)
+ if not isinstance(ptype, type):
+ raise NameError
+ self.ptype = ptype
+ return ptype
+ except NameError:
+ raise TypeError, \
+ "Param qualifier '%s' is not a type" % self.ptype_str
+ raise AttributeError, "'%s' object has no attribute '%s'" % \
+ (type(self).__name__, attr)
+
+ def convert(self, value):
+ if isinstance(value, proxy.BaseProxy):
+ value.set_param_desc(self)
+ return value
+ if not hasattr(self, 'ptype') and isNullPointer(value):
+ # deferred evaluation of SimObject; continue to defer if
+ # we're just assigning a null pointer
+ return value
+ if isinstance(value, self.ptype):
+ return value
+ if isNullPointer(value) and isSimObjectClass(self.ptype):
+ return value
+ return self.ptype(value)
+
+ def cxx_predecls(self):
+ return self.ptype.cxx_predecls
+
+ def swig_predecls(self):
+ return self.ptype.swig_predecls
+
+ def cxx_decl(self):
+ return '%s %s;' % (self.ptype.cxx_type, self.name)
+
+# Vector-valued parameter description. Just like ParamDesc, except
+# that the value is a vector (list) of the specified type instead of a
+# single value.
+
+class VectorParamValue(list):
+ def ini_str(self):
+ return ' '.join([v.ini_str() for v in self])
+
+ def unproxy(self, base):
+ return [v.unproxy(base) for v in self]
+
+class SimObjVector(VectorParamValue):
+ def print_ini(self):
+ for v in self:
+ v.print_ini()
+
+class VectorParamDesc(ParamDesc):
+ # Convert assigned value to appropriate type. If the RHS is not a
+ # list or tuple, it generates a single-element list.
+ def convert(self, value):
+ if isinstance(value, (list, tuple)):
+ # list: coerce each element into new list
+ tmp_list = [ ParamDesc.convert(self, v) for v in value ]
+ if isSimObjectSequence(tmp_list):
+ return SimObjVector(tmp_list)
+ else:
+ return VectorParamValue(tmp_list)
+ else:
+ # singleton: leave it be (could coerce to a single-element
+ # list here, but for some historical reason we don't...
+ return ParamDesc.convert(self, value)
+
+ def cxx_predecls(self):
+ return ['#include <vector>'] + self.ptype.cxx_predecls
+
+ def swig_predecls(self):
+ return ['%include "std_vector.i"'] + self.ptype.swig_predecls
+
+ def cxx_decl(self):
+ return 'std::vector< %s > %s;' % (self.ptype.cxx_type, self.name)
+
+class ParamFactory(object):
+ def __init__(self, param_desc_class, ptype_str = None):
+ self.param_desc_class = param_desc_class
+ self.ptype_str = ptype_str
+
+ def __getattr__(self, attr):
+ if self.ptype_str:
+ attr = self.ptype_str + '.' + attr
+ return ParamFactory(self.param_desc_class, attr)
+
+ # E.g., Param.Int(5, "number of widgets")
+ def __call__(self, *args, **kwargs):
+ caller_frame = inspect.currentframe().f_back
+ ptype = None
+ try:
+ ptype = eval(self.ptype_str,
+ caller_frame.f_globals, caller_frame.f_locals)
+ if not isinstance(ptype, type):
+ raise TypeError, \
+ "Param qualifier is not a type: %s" % ptype
+ except NameError:
+ # if name isn't defined yet, assume it's a SimObject, and
+ # try to resolve it later
+ pass
+ return self.param_desc_class(self.ptype_str, ptype, *args, **kwargs)
+
+Param = ParamFactory(ParamDesc)
+VectorParam = ParamFactory(VectorParamDesc)
+
+#####################################################################
+#
+# Parameter Types
+#
+# Though native Python types could be used to specify parameter types
+# (the 'ptype' field of the Param and VectorParam classes), it's more
+# flexible to define our own set of types. This gives us more control
+# over how Python expressions are converted to values (via the
+# __init__() constructor) and how these values are printed out (via
+# the __str__() conversion method).
+#
+#####################################################################
+
+# String-valued parameter. Just mixin the ParamValue class with the
+# built-in str class.
+class String(ParamValue,str):
+ cxx_type = 'std::string'
+ cxx_predecls = ['#include <string>']
+ swig_predecls = ['%include "std_string.i"\n' +
+ '%apply const std::string& {std::string *};']
+ pass
+
+# superclass for "numeric" parameter values, to emulate math
+# operations in a type-safe way. e.g., a Latency times an int returns
+# a new Latency object.
+class NumericParamValue(ParamValue):
+ def __str__(self):
+ return str(self.value)
+
+ def __float__(self):
+ return float(self.value)
+
+ # hook for bounds checking
+ def _check(self):
+ return
+
+ def __mul__(self, other):
+ newobj = self.__class__(self)
+ newobj.value *= other
+ newobj._check()
+ return newobj
+
+ __rmul__ = __mul__
+
+ def __div__(self, other):
+ newobj = self.__class__(self)
+ newobj.value /= other
+ newobj._check()
+ return newobj
+
+ def __sub__(self, other):
+ newobj = self.__class__(self)
+ newobj.value -= other
+ newobj._check()
+ return newobj
+
+# Metaclass for bounds-checked integer parameters. See CheckedInt.
+class CheckedIntType(type):
+ def __init__(cls, name, bases, dict):
+ super(CheckedIntType, cls).__init__(name, bases, dict)
+
+ # CheckedInt is an abstract base class, so we actually don't
+ # want to do any processing on it... the rest of this code is
+ # just for classes that derive from CheckedInt.
+ if name == 'CheckedInt':
+ return
+
+ if not cls.cxx_predecls:
+ # most derived types require this, so we just do it here once
+ cls.cxx_predecls = ['#include "sim/host.hh"']
+
+ if not cls.swig_predecls:
+ # most derived types require this, so we just do it here once
+ cls.swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
+ '%import "sim/host.hh"']
+
+ if not (hasattr(cls, 'min') and hasattr(cls, 'max')):
+ if not (hasattr(cls, 'size') and hasattr(cls, 'unsigned')):
+ panic("CheckedInt subclass %s must define either\n" \
+ " 'min' and 'max' or 'size' and 'unsigned'\n" \
+ % name);
+ if cls.unsigned:
+ cls.min = 0
+ cls.max = 2 ** cls.size - 1
+ else:
+ cls.min = -(2 ** (cls.size - 1))
+ cls.max = (2 ** (cls.size - 1)) - 1
+
+# Abstract superclass for bounds-checked integer parameters. This
+# class is subclassed to generate parameter classes with specific
+# bounds. Initialization of the min and max bounds is done in the
+# metaclass CheckedIntType.__init__.
+class CheckedInt(NumericParamValue):
+ __metaclass__ = CheckedIntType
+
+ def _check(self):
+ if not self.min <= self.value <= self.max:
+ raise TypeError, 'Integer param out of bounds %d < %d < %d' % \
+ (self.min, self.value, self.max)
+
+ def __init__(self, value):
+ if isinstance(value, str):
+ self.value = convert.toInteger(value)
+ elif isinstance(value, (int, long, float)):
+ self.value = long(value)
+ self._check()
+
+class Int(CheckedInt): cxx_type = 'int'; size = 32; unsigned = False
+class Unsigned(CheckedInt): cxx_type = 'unsigned'; size = 32; unsigned = True
+
+class Int8(CheckedInt): cxx_type = 'int8_t'; size = 8; unsigned = False
+class UInt8(CheckedInt): cxx_type = 'uint8_t'; size = 8; unsigned = True
+class Int16(CheckedInt): cxx_type = 'int16_t'; size = 16; unsigned = False
+class UInt16(CheckedInt): cxx_type = 'uint16_t'; size = 16; unsigned = True
+class Int32(CheckedInt): cxx_type = 'int32_t'; size = 32; unsigned = False
+class UInt32(CheckedInt): cxx_type = 'uint32_t'; size = 32; unsigned = True
+class Int64(CheckedInt): cxx_type = 'int64_t'; size = 64; unsigned = False
+class UInt64(CheckedInt): cxx_type = 'uint64_t'; size = 64; unsigned = True
+
+class Counter(CheckedInt): cxx_type = 'Counter'; size = 64; unsigned = True
+class Tick(CheckedInt): cxx_type = 'Tick'; size = 64; unsigned = True
+class TcpPort(CheckedInt): cxx_type = 'uint16_t'; size = 16; unsigned = True
+class UdpPort(CheckedInt): cxx_type = 'uint16_t'; size = 16; unsigned = True
+
+class Percent(CheckedInt): cxx_type = 'int'; min = 0; max = 100
+
+class Float(ParamValue, float):
+ pass
+
+class MemorySize(CheckedInt):
+ cxx_type = 'uint64_t'
+ size = 64
+ unsigned = True
+ def __init__(self, value):
+ if isinstance(value, MemorySize):
+ self.value = value.value
+ else:
+ self.value = convert.toMemorySize(value)
+ self._check()
+
+class MemorySize32(CheckedInt):
+ size = 32
+ unsigned = True
+ def __init__(self, value):
+ if isinstance(value, MemorySize):
+ self.value = value.value
+ else:
+ self.value = convert.toMemorySize(value)
+ self._check()
+
+class Addr(CheckedInt):
+ cxx_type = 'Addr'
+ cxx_predecls = ['#include "targetarch/isa_traits.hh"']
+ size = 64
+ unsigned = True
+ def __init__(self, value):
+ if isinstance(value, Addr):
+ self.value = value.value
+ else:
+ try:
+ self.value = convert.toMemorySize(value)
+ except TypeError:
+ self.value = long(value)
+ self._check()
+
+
+class MetaRange(type):
+ def __init__(cls, name, bases, dict):
+ super(MetaRange, cls).__init__(name, bases, dict)
+ if name == 'Range':
+ return
+ cls.cxx_type = 'Range< %s >' % cls.type.cxx_type
+ cls.cxx_predecls = \
+ ['#include "base/range.hh"'] + cls.type.cxx_predecls
+
+class Range(ParamValue):
+ __metaclass__ = MetaRange
+ type = Int # default; can be overridden in subclasses
+ def __init__(self, *args, **kwargs):
+ def handle_kwargs(self, kwargs):
+ if 'end' in kwargs:
+ self.second = self.type(kwargs.pop('end'))
+ elif 'size' in kwargs:
+ self.second = self.first + self.type(kwargs.pop('size')) - 1
+ else:
+ raise TypeError, "Either end or size must be specified"
+
+ if len(args) == 0:
+ self.first = self.type(kwargs.pop('start'))
+ handle_kwargs(self, kwargs)
+
+ elif len(args) == 1:
+ if kwargs:
+ self.first = self.type(args[0])
+ handle_kwargs(self, kwargs)
+ elif isinstance(args[0], Range):
+ self.first = self.type(args[0].first)
+ self.second = self.type(args[0].second)
+ else:
+ self.first = self.type(0)
+ self.second = self.type(args[0]) - 1
+
+ elif len(args) == 2:
+ self.first = self.type(args[0])
+ self.second = self.type(args[1])
+ else:
+ raise TypeError, "Too many arguments specified"
+
+ if kwargs:
+ raise TypeError, "too many keywords: %s" % kwargs.keys()
+
+ def __str__(self):
+ return '%s:%s' % (self.first, self.second)
+
+class AddrRange(Range):
+ type = Addr
+
+class TickRange(Range):
+ type = Tick
+
+# Boolean parameter type. Python doesn't let you subclass bool, since
+# it doesn't want to let you create multiple instances of True and
+# False. Thus this is a little more complicated than String.
+class Bool(ParamValue):
+ cxx_type = 'bool'
+ def __init__(self, value):
+ try:
+ self.value = convert.toBool(value)
+ except TypeError:
+ self.value = bool(value)
+
+ def __str__(self):
+ return str(self.value)
+
+ def ini_str(self):
+ if self.value:
+ return 'true'
+ return 'false'
+
+def IncEthernetAddr(addr, val = 1):
+ bytes = map(lambda x: int(x, 16), addr.split(':'))
+ bytes[5] += val
+ for i in (5, 4, 3, 2, 1):
+ val,rem = divmod(bytes[i], 256)
+ bytes[i] = rem
+ if val == 0:
+ break
+ bytes[i - 1] += val
+ assert(bytes[0] <= 255)
+ return ':'.join(map(lambda x: '%02x' % x, bytes))
+
+class NextEthernetAddr(object):
+ addr = "00:90:00:00:00:01"
+
+ def __init__(self, inc = 1):
+ self.value = NextEthernetAddr.addr
+ NextEthernetAddr.addr = IncEthernetAddr(NextEthernetAddr.addr, inc)
+
+class EthernetAddr(ParamValue):
+ cxx_type = 'Net::EthAddr'
+ cxx_predecls = ['#include "base/inet.hh"']
+ swig_predecls = ['class Net::EthAddr;']
+ def __init__(self, value):
+ if value == NextEthernetAddr:
+ self.value = value
+ return
+
+ if not isinstance(value, str):
+ raise TypeError, "expected an ethernet address and didn't get one"
+
+ bytes = value.split(':')
+ if len(bytes) != 6:
+ raise TypeError, 'invalid ethernet address %s' % value
+
+ for byte in bytes:
+ if not 0 <= int(byte) <= 256:
+ raise TypeError, 'invalid ethernet address %s' % value
+
+ self.value = value
+
+ def unproxy(self, base):
+ if self.value == NextEthernetAddr:
+ self.addr = self.value().value
+ return self
+
+ def __str__(self):
+ if self.value == NextEthernetAddr:
+ if hasattr(self, 'addr'):
+ return self.addr
+ else:
+ return "NextEthernetAddr (unresolved)"
+ else:
+ return self.value
+
+# Enumerated types are a little more complex. The user specifies the
+# type as Enum(foo) where foo is either a list or dictionary of
+# alternatives (typically strings, but not necessarily so). (In the
+# long run, the integer value of the parameter will be the list index
+# or the corresponding dictionary value. For now, since we only check
+# that the alternative is valid and then spit it into a .ini file,
+# there's not much point in using the dictionary.)
+
+# What Enum() must do is generate a new type encapsulating the
+# provided list/dictionary so that specific values of the parameter
+# can be instances of that type. We define two hidden internal
+# classes (_ListEnum and _DictEnum) to serve as base classes, then
+# derive the new type from the appropriate base class on the fly.
+
+
+# Metaclass for Enum types
+class MetaEnum(type):
+ def __init__(cls, name, bases, init_dict):
+ if init_dict.has_key('map'):
+ if not isinstance(cls.map, dict):
+ raise TypeError, "Enum-derived class attribute 'map' " \
+ "must be of type dict"
+ # build list of value strings from map
+ cls.vals = cls.map.keys()
+ cls.vals.sort()
+ elif init_dict.has_key('vals'):
+ if not isinstance(cls.vals, list):
+ raise TypeError, "Enum-derived class attribute 'vals' " \
+ "must be of type list"
+ # build string->value map from vals sequence
+ cls.map = {}
+ for idx,val in enumerate(cls.vals):
+ cls.map[val] = idx
+ else:
+ raise TypeError, "Enum-derived class must define "\
+ "attribute 'map' or 'vals'"
+
+ cls.cxx_type = name + '::Enum'
+
+ super(MetaEnum, cls).__init__(name, bases, init_dict)
+
+ # Generate C++ class declaration for this enum type.
+ # Note that we wrap the enum in a class/struct to act as a namespace,
+ # so that the enum strings can be brief w/o worrying about collisions.
+ def cxx_decl(cls):
+ s = 'struct %s {\n enum Enum {\n ' % cls.__name__
+ s += ',\n '.join(['%s = %d' % (v,cls.map[v]) for v in cls.vals])
+ s += '\n };\n};\n'
+ return s
+
+# Base class for enum types.
+class Enum(ParamValue):
+ __metaclass__ = MetaEnum
+ vals = []
+
+ def __init__(self, value):
+ if value not in self.map:
+ raise TypeError, "Enum param got bad value '%s' (not in %s)" \
+ % (value, self.vals)
+ self.value = value
+
+ def __str__(self):
+ return self.value
+
+ticks_per_sec = None
+
+# how big does a rounding error need to be before we warn about it?
+frequency_tolerance = 0.001 # 0.1%
+
+# convert a floting-point # of ticks to integer, and warn if rounding
+# discards too much precision
+def tick_check(float_ticks):
+ if float_ticks == 0:
+ return 0
+ int_ticks = int(round(float_ticks))
+ err = (float_ticks - int_ticks) / float_ticks
+ if err > frequency_tolerance:
+ print >> sys.stderr, "Warning: rounding error > tolerance"
+ print >> sys.stderr, " %f rounded to %d" % (float_ticks, int_ticks)
+ #raise ValueError
+ return int_ticks
+
+def getLatency(value):
+ if isinstance(value, Latency) or isinstance(value, Clock):
+ return value.value
+ elif isinstance(value, Frequency) or isinstance(value, RootClock):
+ return 1 / value.value
+ elif isinstance(value, str):
+ try:
+ return convert.toLatency(value)
+ except ValueError:
+ try:
+ return 1 / convert.toFrequency(value)
+ except ValueError:
+ pass # fall through
+ raise ValueError, "Invalid Frequency/Latency value '%s'" % value
+
+
+class Latency(NumericParamValue):
+ cxx_type = 'Tick'
+ cxx_predecls = ['#include "sim/host.hh"']
+ swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
+ '%import "sim/host.hh"']
+ def __init__(self, value):
+ self.value = getLatency(value)
+
+ def __getattr__(self, attr):
+ if attr in ('latency', 'period'):
+ return self
+ if attr == 'frequency':
+ return Frequency(self)
+ raise AttributeError, "Latency object has no attribute '%s'" % attr
+
+ # convert latency to ticks
+ def ini_str(self):
+ return str(tick_check(self.value * ticks_per_sec))
+
+class Frequency(NumericParamValue):
+ cxx_type = 'Tick'
+ cxx_predecls = ['#include "sim/host.hh"']
+ swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
+ '%import "sim/host.hh"']
+ def __init__(self, value):
+ self.value = 1 / getLatency(value)
+
+ def __getattr__(self, attr):
+ if attr == 'frequency':
+ return self
+ if attr in ('latency', 'period'):
+ return Latency(self)
+ raise AttributeError, "Frequency object has no attribute '%s'" % attr
+
+ # convert frequency to ticks per period
+ def ini_str(self):
+ return self.period.ini_str()
+
+# Just like Frequency, except ini_str() is absolute # of ticks per sec (Hz).
+# We can't inherit from Frequency because we don't want it to be directly
+# assignable to a regular Frequency parameter.
+class RootClock(ParamValue):
+ cxx_type = 'Tick'
+ cxx_predecls = ['#include "sim/host.hh"']
+ swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
+ '%import "sim/host.hh"']
+ def __init__(self, value):
+ self.value = 1 / getLatency(value)
+
+ def __getattr__(self, attr):
+ if attr == 'frequency':
+ return Frequency(self)
+ if attr in ('latency', 'period'):
+ return Latency(self)
+ raise AttributeError, "Frequency object has no attribute '%s'" % attr
+
+ def ini_str(self):
+ return str(tick_check(self.value))
+
+# A generic frequency and/or Latency value. Value is stored as a latency,
+# but to avoid ambiguity this object does not support numeric ops (* or /).
+# An explicit conversion to a Latency or Frequency must be made first.
+class Clock(ParamValue):
+ cxx_type = 'Tick'
+ cxx_predecls = ['#include "sim/host.hh"']
+ swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
+ '%import "sim/host.hh"']
+ def __init__(self, value):
+ self.value = getLatency(value)
+
+ def __getattr__(self, attr):
+ if attr == 'frequency':
+ return Frequency(self)
+ if attr in ('latency', 'period'):
+ return Latency(self)
+ raise AttributeError, "Frequency object has no attribute '%s'" % attr
+
+ def ini_str(self):
+ return self.period.ini_str()
+
+class NetworkBandwidth(float,ParamValue):
+ cxx_type = 'float'
+ def __new__(cls, value):
+ val = convert.toNetworkBandwidth(value) / 8.0
+ return super(cls, NetworkBandwidth).__new__(cls, val)
+
+ def __str__(self):
+ return str(self.val)
+
+ def ini_str(self):
+ return '%f' % (ticks_per_sec / float(self))
+
+class MemoryBandwidth(float,ParamValue):
+ cxx_type = 'float'
+ def __new__(self, value):
+ val = convert.toMemoryBandwidth(value)
+ return super(cls, MemoryBandwidth).__new__(cls, val)
+
+ def __str__(self):
+ return str(self.val)
+
+ def ini_str(self):
+ return '%f' % (ticks_per_sec / float(self))
+
+#
+# "Constants"... handy aliases for various values.
+#
+
+# Special class for NULL pointers. Note the special check in
+# make_param_value() above that lets these be assigned where a
+# SimObject is required.
+# only one copy of a particular node
+class NullSimObject(object):
+ __metaclass__ = Singleton
+
+ def __call__(cls):
+ return cls
+
+ def _instantiate(self, parent = None, path = ''):
+ pass
+
+ def ini_str(self):
+ return 'Null'
+
+ def unproxy(self, base):
+ return self
+
+ def set_path(self, parent, name):
+ pass
+ def __str__(self):
+ return 'Null'
+
+# The only instance you'll ever need...
+NULL = NullSimObject()
+
+def isNullPointer(value):
+ return isinstance(value, NullSimObject)
+
+# Some memory range specifications use this as a default upper bound.
+MaxAddr = Addr.max
+MaxTick = Tick.max
+AllMemory = AddrRange(0, MaxAddr)
+
+
+#####################################################################
+#
+# Port objects
+#
+# Ports are used to interconnect objects in the memory system.
+#
+#####################################################################
+
+# Port reference: encapsulates a reference to a particular port on a
+# particular SimObject.
+class PortRef(object):
+ def __init__(self, simobj, name):
+ assert(isSimObject(simobj) or isSimObjectClass(simobj))
+ self.simobj = simobj
+ self.name = name
+ self.peer = None # not associated with another port yet
+ self.ccConnected = False # C++ port connection done?
+ self.index = -1 # always -1 for non-vector ports
+
+ def __str__(self):
+ return '%s.%s' % (self.simobj, self.name)
+
+ # for config.ini, print peer's name (not ours)
+ def ini_str(self):
+ return str(self.peer)
+
+ def __getattr__(self, attr):
+ if attr == 'peerObj':
+ # shorthand for proxies
+ return self.peer.simobj
+ raise AttributeError, "'%s' object has no attribute '%s'" % \
+ (self.__class__.__name__, attr)
+
+ # Full connection is symmetric (both ways). Called via
+ # SimObject.__setattr__ as a result of a port assignment, e.g.,
+ # "obj1.portA = obj2.portB", or via VectorPortElementRef.__setitem__,
+ # e.g., "obj1.portA[3] = obj2.portB".
+ def connect(self, other):
+ if isinstance(other, VectorPortRef):
+ # reference to plain VectorPort is implicit append
+ other = other._get_next()
+ if self.peer and not proxy.isproxy(self.peer):
+ print "warning: overwriting port", self, \
+ "value", self.peer, "with", other
+ self.peer = other
+ if proxy.isproxy(other):
+ other.set_param_desc(PortParamDesc())
+ elif isinstance(other, PortRef):
+ if other.peer is not self:
+ other.connect(self)
+ else:
+ raise TypeError, \
+ "assigning non-port reference '%s' to port '%s'" \
+ % (other, self)
+
+ def clone(self, simobj, memo):
+ if memo.has_key(self):
+ return memo[self]
+ newRef = copy.copy(self)
+ memo[self] = newRef
+ newRef.simobj = simobj
+ assert(isSimObject(newRef.simobj))
+ if self.peer and not proxy.isproxy(self.peer):
+ peerObj = memo[self.peer.simobj]
+ newRef.peer = self.peer.clone(peerObj, memo)
+ assert(not isinstance(newRef.peer, VectorPortRef))
+ return newRef
+
+ def unproxy(self, simobj):
+ assert(simobj is self.simobj)
+ if proxy.isproxy(self.peer):
+ try:
+ realPeer = self.peer.unproxy(self.simobj)
+ except:
+ print "Error in unproxying port '%s' of %s" % \
+ (self.name, self.simobj.path())
+ raise
+ self.connect(realPeer)
+
+ # Call C++ to create corresponding port connection between C++ objects
+ def ccConnect(self):
+ if self.ccConnected: # already done this
+ return
+ peer = self.peer
+ cc_main.connectPorts(self.simobj.getCCObject(), self.name, self.index,
+ peer.simobj.getCCObject(), peer.name, peer.index)
+ self.ccConnected = True
+ peer.ccConnected = True
+
+# A reference to an individual element of a VectorPort... much like a
+# PortRef, but has an index.
+class VectorPortElementRef(PortRef):
+ def __init__(self, simobj, name, index):
+ PortRef.__init__(self, simobj, name)
+ self.index = index
+
+ def __str__(self):
+ return '%s.%s[%d]' % (self.simobj, self.name, self.index)
+
+# A reference to a complete vector-valued port (not just a single element).
+# Can be indexed to retrieve individual VectorPortElementRef instances.
+class VectorPortRef(object):
+ def __init__(self, simobj, name):
+ assert(isSimObject(simobj) or isSimObjectClass(simobj))
+ self.simobj = simobj
+ self.name = name
+ self.elements = []
+
+ def __str__(self):
+ return '%s.%s[:]' % (self.simobj, self.name)
+
+ # for config.ini, print peer's name (not ours)
+ def ini_str(self):
+ return ' '.join([el.ini_str() for el in self.elements])
+
+ def __getitem__(self, key):
+ if not isinstance(key, int):
+ raise TypeError, "VectorPort index must be integer"
+ if key >= len(self.elements):
+ # need to extend list
+ ext = [VectorPortElementRef(self.simobj, self.name, i)
+ for i in range(len(self.elements), key+1)]
+ self.elements.extend(ext)
+ return self.elements[key]
+
+ def _get_next(self):
+ return self[len(self.elements)]
+
+ def __setitem__(self, key, value):
+ if not isinstance(key, int):
+ raise TypeError, "VectorPort index must be integer"
+ self[key].connect(value)
+
+ def connect(self, other):
+ if isinstance(other, (list, tuple)):
+ # Assign list of port refs to vector port.
+ # For now, append them... not sure if that's the right semantics
+ # or if it should replace the current vector.
+ for ref in other:
+ self._get_next().connect(ref)
+ else:
+ # scalar assignment to plain VectorPort is implicit append
+ self._get_next().connect(other)
+
+ def clone(self, simobj, memo):
+ if memo.has_key(self):
+ return memo[self]
+ newRef = copy.copy(self)
+ memo[self] = newRef
+ newRef.simobj = simobj
+ assert(isSimObject(newRef.simobj))
+ newRef.elements = [el.clone(simobj, memo) for el in self.elements]
+ return newRef
+
+ def unproxy(self, simobj):
+ [el.unproxy(simobj) for el in self.elements]
+
+ def ccConnect(self):
+ [el.ccConnect() for el in self.elements]
+
+# Port description object. Like a ParamDesc object, this represents a
+# logical port in the SimObject class, not a particular port on a
+# SimObject instance. The latter are represented by PortRef objects.
+class Port(object):
+ # Port("description") or Port(default, "description")
+ def __init__(self, *args):
+ if len(args) == 1:
+ self.desc = args[0]
+ elif len(args) == 2:
+ self.default = args[0]
+ self.desc = args[1]
+ else:
+ raise TypeError, 'wrong number of arguments'
+ # self.name is set by SimObject class on assignment
+ # e.g., pio_port = Port("blah") sets self.name to 'pio_port'
+
+ # Generate a PortRef for this port on the given SimObject with the
+ # given name
+ def makeRef(self, simobj):
+ return PortRef(simobj, self.name)
+
+ # Connect an instance of this port (on the given SimObject with
+ # the given name) with the port described by the supplied PortRef
+ def connect(self, simobj, ref):
+ self.makeRef(simobj).connect(ref)
+
+# VectorPort description object. Like Port, but represents a vector
+# of connections (e.g., as on a Bus).
+class VectorPort(Port):
+ def __init__(self, *args):
+ Port.__init__(self, *args)
+ self.isVec = True
+
+ def makeRef(self, simobj):
+ return VectorPortRef(simobj, self.name)
+
+# 'Fake' ParamDesc for Port references to assign to the _pdesc slot of
+# proxy objects (via set_param_desc()) so that proxy error messages
+# make sense.
+class PortParamDesc(object):
+ __metaclass__ = Singleton
+
+ ptype_str = 'Port'
+ ptype = Port
+
+
+__all__ = ['Param', 'VectorParam',
+ 'Enum', 'Bool', 'String', 'Float',
+ 'Int', 'Unsigned', 'Int8', 'UInt8', 'Int16', 'UInt16',
+ 'Int32', 'UInt32', 'Int64', 'UInt64',
+ 'Counter', 'Addr', 'Tick', 'Percent',
+ 'TcpPort', 'UdpPort', 'EthernetAddr',
+ 'MemorySize', 'MemorySize32',
+ 'Latency', 'Frequency', 'RootClock', 'Clock',
+ 'NetworkBandwidth', 'MemoryBandwidth',
+ 'Range', 'AddrRange', 'TickRange',
+ 'MaxAddr', 'MaxTick', 'AllMemory',
+ 'NextEthernetAddr', 'NULL',
+ 'Port', 'VectorPort']
+
+# see comment on imports at end of __init__.py.
+from SimObject import isSimObject, isSimObjectSequence, isSimObjectClass
+import proxy
+import objects
+import cc_main
diff --git a/src/python/m5/proxy.py b/src/python/m5/proxy.py
new file mode 100644
index 0000000..7ebc0ae
--- /dev/null
+++ b/src/python/m5/proxy.py
@@ -0,0 +1,206 @@
+# Copyright (c) 2004-2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+# Nathan Binkert
+
+#####################################################################
+#
+# Proxy object support.
+#
+#####################################################################
+
+class BaseProxy(object):
+ def __init__(self, search_self, search_up):
+ self._search_self = search_self
+ self._search_up = search_up
+ self._multiplier = None
+
+ def __str__(self):
+ if self._search_self and not self._search_up:
+ s = 'Self'
+ elif not self._search_self and self._search_up:
+ s = 'Parent'
+ else:
+ s = 'ConfusedProxy'
+ return s + '.' + self.path()
+
+ def __setattr__(self, attr, value):
+ if not attr.startswith('_'):
+ raise AttributeError, \
+ "cannot set attribute '%s' on proxy object" % attr
+ super(BaseProxy, self).__setattr__(attr, value)
+
+ # support multiplying proxies by constants
+ def __mul__(self, other):
+ if not isinstance(other, (int, long, float)):
+ raise TypeError, "Proxy multiplier must be integer"
+ if self._multiplier == None:
+ self._multiplier = other
+ else:
+ # support chained multipliers
+ self._multiplier *= other
+ return self
+
+ __rmul__ = __mul__
+
+ def _mulcheck(self, result):
+ if self._multiplier == None:
+ return result
+ return result * self._multiplier
+
+ def unproxy(self, base):
+ obj = base
+ done = False
+
+ if self._search_self:
+ result, done = self.find(obj)
+
+ if self._search_up:
+ while not done:
+ obj = obj._parent
+ if not obj:
+ break
+ result, done = self.find(obj)
+
+ if not done:
+ raise AttributeError, \
+ "Can't resolve proxy '%s' of type '%s' from '%s'" % \
+ (self.path(), self._pdesc.ptype_str, base.path())
+
+ if isinstance(result, BaseProxy):
+ if result == self:
+ raise RuntimeError, "Cycle in unproxy"
+ result = result.unproxy(obj)
+
+ return self._mulcheck(result)
+
+ def getindex(obj, index):
+ if index == None:
+ return obj
+ try:
+ obj = obj[index]
+ except TypeError:
+ if index != 0:
+ raise
+ # if index is 0 and item is not subscriptable, just
+ # use item itself (so cpu[0] works on uniprocessors)
+ return obj
+ getindex = staticmethod(getindex)
+
+ # This method should be called once the proxy is assigned to a
+ # particular parameter or port to set the expected type of the
+ # resolved proxy
+ def set_param_desc(self, pdesc):
+ self._pdesc = pdesc
+
+class AttrProxy(BaseProxy):
+ def __init__(self, search_self, search_up, attr):
+ super(AttrProxy, self).__init__(search_self, search_up)
+ self._attr = attr
+ self._modifiers = []
+
+ def __getattr__(self, attr):
+ # python uses __bases__ internally for inheritance
+ if attr.startswith('_'):
+ return super(AttrProxy, self).__getattr__(self, attr)
+ if hasattr(self, '_pdesc'):
+ raise AttributeError, "Attribute reference on bound proxy"
+ self._modifiers.append(attr)
+ return self
+
+ # support indexing on proxies (e.g., Self.cpu[0])
+ def __getitem__(self, key):
+ if not isinstance(key, int):
+ raise TypeError, "Proxy object requires integer index"
+ self._modifiers.append(key)
+ return self
+
+ def find(self, obj):
+ try:
+ val = getattr(obj, self._attr)
+ except:
+ return None, False
+ while isproxy(val):
+ val = val.unproxy(obj)
+ for m in self._modifiers:
+ if isinstance(m, str):
+ val = getattr(val, m)
+ elif isinstance(m, int):
+ val = val[m]
+ else:
+ assert("Item must be string or integer")
+ while isproxy(val):
+ val = val.unproxy(obj)
+ return val, True
+
+ def path(self):
+ p = self._attr
+ for m in self._modifiers:
+ if isinstance(m, str):
+ p += '.%s' % m
+ elif isinstance(m, int):
+ p += '[%d]' % m
+ else:
+ assert("Item must be string or integer")
+ return p
+
+class AnyProxy(BaseProxy):
+ def find(self, obj):
+ return obj.find_any(self._pdesc.ptype)
+
+ def path(self):
+ return 'any'
+
+def isproxy(obj):
+ if isinstance(obj, (BaseProxy, params.EthernetAddr)):
+ return True
+ elif isinstance(obj, (list, tuple)):
+ for v in obj:
+ if isproxy(v):
+ return True
+ return False
+
+class ProxyFactory(object):
+ def __init__(self, search_self, search_up):
+ self.search_self = search_self
+ self.search_up = search_up
+
+ def __getattr__(self, attr):
+ if attr == 'any':
+ return AnyProxy(self.search_self, self.search_up)
+ else:
+ return AttrProxy(self.search_self, self.search_up, attr)
+
+# global objects for handling proxies
+Parent = ProxyFactory(search_self = False, search_up = True)
+Self = ProxyFactory(search_self = True, search_up = False)
+
+# limit exports on 'from proxy import *'
+__all__ = ['Parent', 'Self']
+
+# see comment on imports at end of __init__.py.
+import params # for EthernetAddr
diff --git a/src/python/m5/util.py b/src/python/m5/util.py
new file mode 100644
index 0000000..28b8b1b
--- /dev/null
+++ b/src/python/m5/util.py
@@ -0,0 +1,59 @@
+# Copyright (c) 2004-2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+# Nathan Binkert
+
+#############################
+#
+# Utility classes & methods
+#
+#############################
+
+class Singleton(type):
+ def __call__(cls, *args, **kwargs):
+ if hasattr(cls, '_instance'):
+ return cls._instance
+
+ cls._instance = super(Singleton, cls).__call__(*args, **kwargs)
+ return cls._instance
+
+# Apply method to object.
+# applyMethod(obj, 'meth', <args>) is equivalent to obj.meth(<args>)
+def applyMethod(obj, meth, *args, **kwargs):
+ return getattr(obj, meth)(*args, **kwargs)
+
+# If the first argument is an (non-sequence) object, apply the named
+# method with the given arguments. If the first argument is a
+# sequence, apply the method to each element of the sequence (a la
+# 'map').
+def applyOrMap(objOrSeq, meth, *args, **kwargs):
+ if not isinstance(objOrSeq, (list, tuple)):
+ return applyMethod(objOrSeq, meth, *args, **kwargs)
+ else:
+ return [applyMethod(o, meth, *args, **kwargs) for o in objOrSeq]
+
+
diff --git a/src/sim/main.cc b/src/sim/main.cc
index 4ea8c41..5725897 100644
--- a/src/sim/main.cc
+++ b/src/sim/main.cc
@@ -151,8 +151,8 @@
// initialize SWIG 'cc_main' module
init_cc_main();
- PyRun_SimpleString("import m5");
- PyRun_SimpleString("m5.main()");
+ PyRun_SimpleString("import m5.main");
+ PyRun_SimpleString("m5.main.main()");
// clean up Python intepreter.
Py_Finalize();
diff --git a/tests/SConscript b/tests/SConscript
index b538ec5..1228e78 100644
--- a/tests/SConscript
+++ b/tests/SConscript
@@ -207,7 +207,7 @@
'tsunami-simple-atomic-dual',
'tsunami-simple-timing-dual']
else:
- configs += ['simple-atomic', 'simple-timing']
+ configs += ['simple-atomic', 'simple-timing', 'o3-timing']
cwd = os.getcwd()
os.chdir(str(Dir('.').srcdir))
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
new file mode 100644
index 0000000..227e1ba
--- /dev/null
+++ b/tests/configs/o3-timing.py
@@ -0,0 +1,52 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+import m5
+from m5.objects import *
+m5.AddToPath('../configs/common')
+from FullO3Config import *
+
+class MyCache(BaseCache):
+ assoc = 2
+ block_size = 64
+ latency = 1
+ mshrs = 10
+ tgts_per_mshr = 5
+
+cpu = DetailedO3CPU()
+cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+ MyCache(size = '2MB'))
+cpu.mem = cpu.dcache
+
+system = System(cpu = cpu,
+ physmem = PhysicalMemory(),
+ membus = Bus())
+system.physmem.port = system.membus.port
+cpu.connectMemPorts(system.membus)
+
+root = Root(system = system)
diff --git a/tests/diff-out b/tests/diff-out
index 5ebe97d..1308ecc 100755
--- a/tests/diff-out
+++ b/tests/diff-out
@@ -398,8 +398,8 @@
}
cleanup();
-# Exit code is 0 if no stats error, 1 otherwise
-$status = ($max_err_mag == 0.0) ? 0 : 1;
+# Exit code is 0 if some stats found & no stats error, 1 otherwise
+$status = ($#key_stats >= 0 && $max_err_mag == 0.0) ? 0 : 1;
exit $status;
sub cleanup
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
new file mode 100644
index 0000000..c3a59fb
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -0,0 +1,417 @@
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache fuPool icache l2cache toL2Bus workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=1
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.cpu.dcache
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+predType=tournament
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+squashWidth=8
+system=system
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList0
+count=6
+opList=system.cpu.fuPool.FUList0.opList0
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList4.opList0
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList5.opList0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0
+count=1
+opList=system.cpu.fuPool.FUList7.opList0
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+env=
+executable=tests/test-progs/hello/bin/alpha/linux/hello
+input=cin
+output=cout
+system=system
+
+[system.membus]
+type=Bus
+bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+port=system.membus.port[0]
+
+[trace]
+bufsize=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out
new file mode 100644
index 0000000..f491a30
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out
@@ -0,0 +1,403 @@
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
+input=cin
+output=cout
+env=
+system=system
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+opClass=IntAlu
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+opList=system.cpu.fuPool.FUList0.opList0
+count=6
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+opClass=IntMult
+opLat=3
+issueLat=1
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+opClass=IntDiv
+opLat=20
+issueLat=19
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+count=2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+opClass=FloatAdd
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+opClass=FloatCmp
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+opClass=FloatCvt
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+count=4
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+opClass=FloatMult
+opLat=4
+issueLat=1
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+opClass=FloatDiv
+opLat=12
+issueLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+opClass=FloatSqrt
+opLat=24
+issueLat=24
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+count=2
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+opList=system.cpu.fuPool.FUList4.opList0
+count=0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+opList=system.cpu.fuPool.FUList5.opList0
+count=0
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+count=4
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+opClass=IprAccess
+opLat=3
+issueLat=3
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+opList=system.cpu.fuPool.FUList7.opList0
+count=1
+
+[system.cpu.fuPool]
+type=FUPool
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu]
+type=DerivO3CPU
+clock=1
+numThreads=1
+activity=0
+workload=system.cpu.workload
+mem=system.cpu.dcache
+checker=null
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+cachePorts=200
+decodeToFetchDelay=1
+renameToFetchDelay=1
+iewToFetchDelay=1
+commitToFetchDelay=1
+fetchWidth=8
+renameToDecodeDelay=1
+iewToDecodeDelay=1
+commitToDecodeDelay=1
+fetchToDecodeDelay=1
+decodeWidth=8
+iewToRenameDelay=1
+commitToRenameDelay=1
+decodeToRenameDelay=1
+renameWidth=8
+commitToIEWDelay=1
+renameToIEWDelay=2
+issueToExecuteDelay=1
+dispatchWidth=8
+issueWidth=8
+wbWidth=8
+wbDepth=1
+fuPool=system.cpu.fuPool
+iewToCommitDelay=1
+renameToROBDelay=1
+commitWidth=8
+squashWidth=8
+trapLatency=13
+backComSize=5
+forwardComSize=5
+predType=tournament
+localPredictorSize=2048
+localCtrBits=2
+localHistoryTableSize=2048
+localHistoryBits=11
+globalPredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+choicePredictorSize=8192
+choiceCtrBits=2
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+LQEntries=32
+SQEntries=32
+LFSTSize=1024
+SSITSize=1024
+numPhysIntRegs=256
+numPhysFloatRegs=256
+numIQEntries=64
+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+
+[trace]
+flags=
+start=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
new file mode 100644
index 0000000..5d4f923
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt
@@ -0,0 +1,1974 @@
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 542 # Number of BTB hits
+global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
+global.BPredUnit.lookups 2256 # Number of BP lookups
+global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
+host_inst_rate 41797 # Simulator instruction rate (inst/s)
+host_mem_usage 160344 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
+host_tick_rate 50948 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 5623 # Number of instructions simulated
+sim_seconds 0.000000 # Number of seconds simulated
+sim_ticks 6870 # Number of ticks simulated
+system.cpu.commit.COM:branches 862 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 6116
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 3908 6389.80%
+ 1 1064 1739.70%
+ 2 389 636.04%
+ 3 210 343.36%
+ 4 153 250.16%
+ 5 93 152.06%
+ 6 76 124.26%
+ 7 149 243.62%
+ 8 74 120.99%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 5640 # Number of instructions committed
+system.cpu.commit.COM:loads 979 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 1791 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 5623 # Number of Instructions Simulated
+system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
+system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 2048 # number of overall hits
+system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 311 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
+system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 6871
+system.cpu.fetch.rateDist.min_value 0
+ 0 4549 6620.58%
+ 1 174 253.24%
+ 2 186 270.70%
+ 3 157 228.50%
+ 4 211 307.09%
+ 5 153 222.68%
+ 6 171 248.87%
+ 7 105 152.82%
+ 8 1165 1695.53%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
+system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 1255 # number of overall hits
+system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
+system.cpu.icache.overall_misses 327 # number of overall misses
+system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
+system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.iew.EXEC:branches 1206 # Number of branches executed
+system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
+system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
+system.cpu.iew.EXEC:nop 37 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
+system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
+system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
+system.cpu.iew.EXEC:stores 989 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
+system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 4049 # num instructions producing a value
+system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
+system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
+system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:(null).samples 0
+system.cpu.iq.IQ:residence:(null).min_value 0
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+system.cpu.iq.IQ:residence:(null).max_value 0
+system.cpu.iq.IQ:residence:(null).end_dist
+
+system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IntAlu.samples 0
+system.cpu.iq.IQ:residence:IntAlu.min_value 0
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+
+system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:IntMult.min_value 0
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+
+system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:IntDiv.samples 0
+system.cpu.iq.IQ:residence:IntDiv.min_value 0
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+
+system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:FloatAdd.min_value 0
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+system.cpu.iq.IQ:residence:FloatAdd.max_value 0
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+
+system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:FloatCmp.min_value 0
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+
+system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:FloatCvt.min_value 0
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+
+system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:FloatMult.min_value 0
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+
+system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:FloatDiv.min_value 0
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+
+system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:FloatSqrt.end_dist
+
+system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:MemRead.min_value 0
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+
+system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:MemWrite.end_dist
+
+system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:IprAccess.min_value 0
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+system.cpu.iq.IQ:residence:IprAccess.end_dist
+
+system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:InstPrefetch.samples 0
+system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
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+system.cpu.iq.IQ:residence:InstPrefetch.end_dist
+
+system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:(null)_delay.samples 0
+system.cpu.iq.ISSUE:(null)_delay.min_value 0
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+
+system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntAlu_delay.samples 0
+system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
+ 0 0
+ 2 0
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+system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
+system.cpu.iq.ISSUE:IntAlu_delay.end_dist
+
+system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntMult_delay.samples 0
+system.cpu.iq.ISSUE:IntMult_delay.min_value 0
+ 0 0
+ 2 0
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+system.cpu.iq.ISSUE:IntMult_delay.max_value 0
+system.cpu.iq.ISSUE:IntMult_delay.end_dist
+
+system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntDiv_delay.samples 0
+system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
+ 0 0
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+system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
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+
+system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
+system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
+ 0 0
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+system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
+system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
+system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
+ 0 0
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+system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
+system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
+system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
+ 0 0
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+system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
+system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatMult_delay.samples 0
+system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
+ 0 0
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+system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
+system.cpu.iq.ISSUE:FloatMult_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
+system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
+ 0 0
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+system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
+system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
+ 0 0
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+system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
+
+system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:MemRead_delay.samples 0
+system.cpu.iq.ISSUE:MemRead_delay.min_value 0
+ 0 0
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+system.cpu.iq.ISSUE:MemRead_delay.max_value 0
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+
+system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
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+system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
+ 0 0
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+system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
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+
+system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IprAccess_delay.samples 0
+system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
+ 0 0
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+system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
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+
+system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
+ 0 0
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+system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
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+
+system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ (null) 2 0.02% # Type of FU issued
+ IntAlu 5594 66.69% # Type of FU issued
+ IntMult 1 0.01% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 2 0.02% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 1757 20.95% # Type of FU issued
+ MemWrite 1032 12.30% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ (null) 0 0.00% # attempts to use FU when none available
+ IntAlu 1 0.87% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 76 66.09% # attempts to use FU when none available
+ MemWrite 38 33.04% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 3753 5462.09%
+ 1 894 1301.12%
+ 2 723 1052.25%
+ 3 614 893.61%
+ 4 451 656.38%
+ 5 279 406.05%
+ 6 104 151.36%
+ 7 41 59.67%
+ 8 12 17.46%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
+system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 2 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 497 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.numCycles 6871 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
+system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
new file mode 100644
index 0000000..8893caa
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr
@@ -0,0 +1,3 @@
+warn: Entering event queue @ 0. Starting simulation...
+warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
+warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
new file mode 100644
index 0000000..fbb329a
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout
@@ -0,0 +1,13 @@
+Hello world!
+M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:12 2006
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
+Exiting @ tick 6870 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
index a530874..f843721 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -68,6 +68,8 @@
system=system
width=1
workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
@@ -81,12 +83,14 @@
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
index 72cf4f4..e3cd05f 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 108728 # Simulator instruction rate (inst/s)
-host_mem_usage 147156 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
-host_tick_rate 107873 # Simulator tick rate (ticks/s)
+host_inst_rate 74000 # Simulator instruction rate (inst/s)
+host_mem_usage 148088 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
+host_tick_rate 73591 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
index 8850985..17eea9a 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout
@@ -6,8 +6,8 @@
All Rights Reserved
-M5 compiled Aug 24 2006 13:09:55
-M5 started Thu Aug 24 14:29:33 2006
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:14 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
Exiting @ tick 5641 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index fe81831..80d2a27 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -66,6 +66,8 @@
mem=system.cpu.dcache
system=system
workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
@@ -104,6 +106,8 @@
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
@@ -142,6 +146,8 @@
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
@@ -180,10 +186,13 @@
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
@@ -197,12 +206,14 @@
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
index 2397e59..fe2cd43 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 73848 # Simulator instruction rate (inst/s)
-host_mem_usage 159612 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
-host_tick_rate 107959 # Simulator tick rate (ticks/s)
+host_inst_rate 113478 # Simulator instruction rate (inst/s)
+host_mem_usage 159608 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
+host_tick_rate 165749 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5642 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
@@ -53,7 +53,7 @@
system.cpu.dcache.overall_accesses 1802 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 2.876471 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 1632 # number of overall hits
system.cpu.dcache.overall_miss_latency 489 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.094340 # miss rate for overall accesses
@@ -178,7 +178,7 @@
system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 1.968610 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1 # number of overall hits
system.cpu.l2cache.overall_miss_latency 878 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
index be2f328..7104aa0 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout
@@ -6,8 +6,8 @@
All Rights Reserved
-M5 compiled Aug 21 2006 14:18:48
-M5 started Mon Aug 21 14:19:14 2006
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:15 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
Exiting @ tick 8312 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
new file mode 100644
index 0000000..790ae6a
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -0,0 +1,417 @@
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=dcache fuPool icache l2cache toL2Bus workload
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=1
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.cpu.dcache
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+predType=tournament
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+squashWidth=8
+system=system
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList0
+count=6
+opList=system.cpu.fuPool.FUList0.opList0
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList4.opList0
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList5.opList0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0
+count=1
+opList=system.cpu.fuPool.FUList7.opList0
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+env=
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
+input=cin
+output=cout
+system=system
+
+[system.membus]
+type=Bus
+bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+port=system.membus.port[0]
+
+[trace]
+bufsize=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out
new file mode 100644
index 0000000..474ea35
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out
@@ -0,0 +1,403 @@
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
+input=cin
+output=cout
+env=
+system=system
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+opClass=IntAlu
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+opList=system.cpu.fuPool.FUList0.opList0
+count=6
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+opClass=IntMult
+opLat=3
+issueLat=1
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+opClass=IntDiv
+opLat=20
+issueLat=19
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+count=2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+opClass=FloatAdd
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+opClass=FloatCmp
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+opClass=FloatCvt
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+count=4
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+opClass=FloatMult
+opLat=4
+issueLat=1
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+opClass=FloatDiv
+opLat=12
+issueLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+opClass=FloatSqrt
+opLat=24
+issueLat=24
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+count=2
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+opList=system.cpu.fuPool.FUList4.opList0
+count=0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+opList=system.cpu.fuPool.FUList5.opList0
+count=0
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+count=4
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+opClass=IprAccess
+opLat=3
+issueLat=3
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+opList=system.cpu.fuPool.FUList7.opList0
+count=1
+
+[system.cpu.fuPool]
+type=FUPool
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu]
+type=DerivO3CPU
+clock=1
+numThreads=1
+activity=0
+workload=system.cpu.workload
+mem=system.cpu.dcache
+checker=null
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+cachePorts=200
+decodeToFetchDelay=1
+renameToFetchDelay=1
+iewToFetchDelay=1
+commitToFetchDelay=1
+fetchWidth=8
+renameToDecodeDelay=1
+iewToDecodeDelay=1
+commitToDecodeDelay=1
+fetchToDecodeDelay=1
+decodeWidth=8
+iewToRenameDelay=1
+commitToRenameDelay=1
+decodeToRenameDelay=1
+renameWidth=8
+commitToIEWDelay=1
+renameToIEWDelay=2
+issueToExecuteDelay=1
+dispatchWidth=8
+issueWidth=8
+wbWidth=8
+wbDepth=1
+fuPool=system.cpu.fuPool
+iewToCommitDelay=1
+renameToROBDelay=1
+commitWidth=8
+squashWidth=8
+trapLatency=13
+backComSize=5
+forwardComSize=5
+predType=tournament
+localPredictorSize=2048
+localCtrBits=2
+localHistoryTableSize=2048
+localHistoryBits=11
+globalPredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+choicePredictorSize=8192
+choiceCtrBits=2
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+LQEntries=32
+SQEntries=32
+LFSTSize=1024
+SSITSize=1024
+numPhysIntRegs=256
+numPhysFloatRegs=256
+numIQEntries=64
+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+
+[trace]
+flags=
+start=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
new file mode 100644
index 0000000..db582e7
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt
@@ -0,0 +1,1972 @@
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 155 # Number of BTB hits
+global.BPredUnit.BTBLookups 711 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 222 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 441 # Number of conditional branches predicted
+global.BPredUnit.lookups 888 # Number of BP lookups
+global.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target.
+host_inst_rate 26468 # Simulator instruction rate (inst/s)
+host_mem_usage 159864 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
+host_tick_rate 31894 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 675 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 369 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 2387 # Number of instructions simulated
+sim_seconds 0.000000 # Number of seconds simulated
+sim_ticks 2886 # Number of ticks simulated
+system.cpu.commit.COM:branches 396 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 40 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 2646
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 1713 6473.92%
+ 1 239 903.25%
+ 2 322 1216.93%
+ 3 139 525.32%
+ 4 78 294.78%
+ 5 67 253.21%
+ 6 27 102.04%
+ 7 21 79.37%
+ 8 40 151.17%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 2576 # Number of instructions committed
+system.cpu.commit.COM:loads 415 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 709 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 138 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 1258 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 2387 # Number of Instructions Simulated
+system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
+system.cpu.cpi 1.209049 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.209049 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 535 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 195 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.121495 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 65 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 122 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.114019 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 3.017241 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.208333 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 236 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 175 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.197279 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 58 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 34 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 53 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 1.500000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 8.305882 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 3 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 829 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3.008130 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 706 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 370 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.148372 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 123 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 38 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 175 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.102533 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 829 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3.008130 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 706 # number of overall hits
+system.cpu.dcache.overall_miss_latency 370 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.148372 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 123 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 38 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 175 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.102533 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 54.161413 # Cycle average of tags in use
+system.cpu.dcache.total_refs 706 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 82 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 90 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 156 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 4646 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 1691 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 873 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 240 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 315 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 888 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 740 # Number of cache lines fetched
+system.cpu.fetch.Cycles 1663 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 77 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 5518 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 235 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.307586 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 740 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 315 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.911327 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 2887
+system.cpu.fetch.rateDist.min_value 0
+ 0 1965 6806.37%
+ 1 36 124.70%
+ 2 79 273.64%
+ 3 66 228.61%
+ 4 125 432.98%
+ 5 60 207.83%
+ 6 40 138.55%
+ 7 42 145.48%
+ 8 474 1641.84%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.icache.ReadReq_accesses 740 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 2.989474 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 550 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 568 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.256757 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 190 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 378 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.255405 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 189 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 2.910053 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 740 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 2.989474 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
+system.cpu.icache.demand_hits 550 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 568 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.256757 # miss rate for demand accesses
+system.cpu.icache.demand_misses 190 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 378 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.255405 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 189 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 740 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 2.989474 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 550 # number of overall hits
+system.cpu.icache.overall_miss_latency 568 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.256757 # miss rate for overall accesses
+system.cpu.icache.overall_misses 190 # number of overall misses
+system.cpu.icache.overall_mshr_hits 1 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 378 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.255405 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 189 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.sampled_refs 189 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 115.538968 # Cycle average of tags in use
+system.cpu.icache.total_refs 550 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.iew.EXEC:branches 533 # Number of branches executed
+system.cpu.iew.EXEC:insts 3123 # Number of executed instructions
+system.cpu.iew.EXEC:loads 578 # Number of load instructions executed
+system.cpu.iew.EXEC:nop 247 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.081746 # Inst execution rate
+system.cpu.iew.EXEC:refs 914 # number of memory reference insts executed
+system.cpu.iew.EXEC:squashedInsts 148 # Number of squashed instructions skipped in execute
+system.cpu.iew.EXEC:stores 336 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 1801 # num instructions consuming a value
+system.cpu.iew.WB:count 3070 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.791227 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 1425 # num instructions producing a value
+system.cpu.iew.WB:rate 1.063388 # insts written-back per cycle
+system.cpu.iew.WB:sent 3076 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 159 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 675 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 369 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 3835 # Number of instructions dispatched to IQ
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 240 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 260 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 75 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 106 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.827096 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.827096 # IPC: Total IPC of All Threads
+system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
+system.cpu.iq.IQ:residence:(null).samples 0
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+
+system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
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+
+system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
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+
+system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:IntDiv.min_value 0
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+
+system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:FloatAdd.min_value 0
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+
+system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:FloatCmp.min_value 0
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+
+system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:FloatCvt.min_value 0
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+
+system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:FloatMult.min_value 0
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+
+system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:FloatDiv.min_value 0
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+
+system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
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+system.cpu.iq.IQ:residence:FloatSqrt.end_dist
+
+system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:MemRead.min_value 0
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+
+system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:MemWrite.min_value 0
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+
+system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:IprAccess.min_value 0
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+
+system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
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+system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
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+
+system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
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+system.cpu.iq.ISSUE:(null)_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
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+system.cpu.iq.ISSUE:(null)_delay.max_value 0
+system.cpu.iq.ISSUE:(null)_delay.end_dist
+
+system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntAlu_delay.samples 0
+system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
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+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
+system.cpu.iq.ISSUE:IntAlu_delay.end_dist
+
+system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntMult_delay.samples 0
+system.cpu.iq.ISSUE:IntMult_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
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+ 86 0
+ 88 0
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+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IntMult_delay.max_value 0
+system.cpu.iq.ISSUE:IntMult_delay.end_dist
+
+system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IntDiv_delay.samples 0
+system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
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+ 88 0
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+ 92 0
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+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
+system.cpu.iq.ISSUE:IntDiv_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
+system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
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+ 12 0
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+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
+system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
+system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
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+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
+system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
+system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
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+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
+system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatMult_delay.samples 0
+system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
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+ 82 0
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+ 86 0
+ 88 0
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+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
+system.cpu.iq.ISSUE:FloatMult_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
+system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
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+ 86 0
+ 88 0
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+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
+system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
+
+system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
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+ 30 0
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+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
+system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
+
+system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:MemRead_delay.samples 0
+system.cpu.iq.ISSUE:MemRead_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
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+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:MemRead_delay.max_value 0
+system.cpu.iq.ISSUE:MemRead_delay.end_dist
+
+system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:MemWrite_delay.samples 0
+system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
+ 24 0
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+ 36 0
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+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
+system.cpu.iq.ISSUE:MemWrite_delay.end_dist
+
+system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:IprAccess_delay.samples 0
+system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
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+ 36 0
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+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
+system.cpu.iq.ISSUE:IprAccess_delay.end_dist
+
+system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
+system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
+ 0 0
+ 2 0
+ 4 0
+ 6 0
+ 8 0
+ 10 0
+ 12 0
+ 14 0
+ 16 0
+ 18 0
+ 20 0
+ 22 0
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+ 78 0
+ 80 0
+ 82 0
+ 84 0
+ 86 0
+ 88 0
+ 90 0
+ 92 0
+ 94 0
+ 96 0
+ 98 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
+system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
+
+system.cpu.iq.ISSUE:FU_type_0 3271 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ (null) 0 0.00% # Type of FU issued
+ IntAlu 2317 70.83% # Type of FU issued
+ IntMult 1 0.03% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 0 0.00% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 609 18.62% # Type of FU issued
+ MemWrite 344 10.52% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 40 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.012229 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ (null) 0 0.00% # attempts to use FU when none available
+ IntAlu 5 12.50% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 12 30.00% # attempts to use FU when none available
+ MemWrite 23 57.50% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 2887
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 1603 5552.48%
+ 1 434 1503.29%
+ 2 301 1042.60%
+ 3 220 762.04%
+ 4 167 578.46%
+ 5 94 325.60%
+ 6 46 159.33%
+ 7 15 51.96%
+ 8 7 24.25%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 1.133010 # Inst issue rate
+system.cpu.iq.iqInstsAdded 3581 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 3271 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 1067 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 477 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 274 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 2.018248 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 553 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 274 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 274 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 274 # number of ReadReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 274 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 2.018248 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 553 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 274 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 274 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 274 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 274 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 2.018248 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 0 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 553 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 274 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 274 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 274 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 274 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 169.795289 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.numCycles 2887 # number of cpu cycles simulated
+system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IdleCycles 1780 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 4975 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 4400 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 3144 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 785 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 240 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 8 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 1376 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 74 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 10 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 62 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 8 # count of temporary serializing insts renamed
+system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr
new file mode 100644
index 0000000..688d898
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr
@@ -0,0 +1,4 @@
+warn: Entering event queue @ 0. Starting simulation...
+warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
+warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff8
+warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
new file mode 100644
index 0000000..708b958
--- /dev/null
+++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout
@@ -0,0 +1,13 @@
+Hello world!
+M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:16 2006
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
+Exiting @ tick 2886 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index d845c0e..1ec052a 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,6 +68,8 @@
system=system
width=1
workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
@@ -81,12 +83,14 @@
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
index 2317e88..b4747f1 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 58510 # Simulator instruction rate (inst/s)
-host_mem_usage 146720 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
-host_tick_rate 57971 # Simulator tick rate (ticks/s)
+host_inst_rate 46556 # Simulator instruction rate (inst/s)
+host_mem_usage 147672 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 46204 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
index d7cbe76..438e330 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
@@ -6,8 +6,8 @@
All Rights Reserved
-M5 compiled Aug 18 2006 00:06:43
-M5 started Fri Aug 18 00:12:48 2006
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:18 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic
Exiting @ tick 2577 because target called exit()
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
index 5f05f07..e833d84 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -66,6 +66,8 @@
mem=system.cpu.dcache
system=system
workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
@@ -104,6 +106,8 @@
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
@@ -142,6 +146,8 @@
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
@@ -180,10 +186,13 @@
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
@@ -197,12 +206,14 @@
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
index ee76bf8..47bcc1b 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 5953 # Simulator instruction rate (inst/s)
-host_mem_usage 159132 # Number of bytes of host memory used
-host_seconds 0.43 # Real time elapsed on the host
-host_tick_rate 8713 # Simulator tick rate (ticks/s)
+host_inst_rate 73626 # Simulator instruction rate (inst/s)
+host_mem_usage 159128 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
+host_tick_rate 106590 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
index f4d7a39..4a02e57 100644
--- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
@@ -6,8 +6,8 @@
All Rights Reserved
-M5 compiled Aug 21 2006 14:18:48
-M5 started Mon Aug 21 14:19:22 2006
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:18 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
Exiting @ tick 3777 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
index f0eb69e..2c82b8c 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -68,6 +68,8 @@
system=system
width=1
workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
@@ -81,12 +83,14 @@
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
index a45e5a8..b70a6ee 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 124620 # Simulator instruction rate (inst/s)
-host_mem_usage 147356 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
-host_tick_rate 122794 # Simulator tick rate (ticks/s)
+host_inst_rate 90956 # Simulator instruction rate (inst/s)
+host_mem_usage 147380 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 90353 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5657 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
index 12a95ee..f5b9c8f 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout
@@ -6,8 +6,8 @@
All Rights Reserved
-M5 compiled Aug 18 2006 00:09:15
-M5 started Fri Aug 18 00:12:56 2006
+M5 compiled Sep 5 2006 15:37:09
+M5 started Tue Sep 5 15:46:32 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
Exiting @ tick 5656 because target called exit()
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
index ab77b14..040735f 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -66,6 +66,8 @@
mem=system.cpu.dcache
system=system
workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
@@ -104,6 +106,8 @@
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
@@ -142,6 +146,8 @@
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
@@ -180,10 +186,13 @@
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=LiveProcess
@@ -197,12 +206,14 @@
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
index 5477183..5d054b9 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 289509 # Simulator instruction rate (inst/s)
+host_inst_rate 129834 # Simulator instruction rate (inst/s)
host_mem_usage 158964 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
-host_tick_rate 429531 # Simulator tick rate (ticks/s)
+host_seconds 0.04 # Real time elapsed on the host
+host_tick_rate 194881 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5657 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
@@ -90,8 +90,8 @@
system.cpu.icache.ReadReq_mshr_miss_latency 604 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
index fd27ee6..1100993 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout
@@ -6,8 +6,8 @@
All Rights Reserved
-M5 compiled Aug 21 2006 14:43:46
-M5 started Mon Aug 21 14:44:00 2006
+M5 compiled Sep 5 2006 15:37:09
+M5 started Tue Sep 5 15:46:32 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
Exiting @ tick 8573 because target called exit()
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
index c223735..082415a 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -68,6 +68,8 @@
system=system
width=1
workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
[system.cpu.workload]
type=LiveProcess
@@ -81,12 +83,14 @@
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
index 52a75de..9bfb2fe 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 79435 # Simulator instruction rate (inst/s)
-host_mem_usage 147292 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-host_tick_rate 78854 # Simulator tick rate (ticks/s)
+host_inst_rate 61348 # Simulator instruction rate (inst/s)
+host_mem_usage 147288 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
+host_tick_rate 60991 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4483 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
index 0730d4b..38eb82c 100644
--- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
+++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout
@@ -5,8 +5,8 @@
All Rights Reserved
-M5 compiled Aug 24 2006 13:31:50
-M5 started Thu Aug 24 14:29:35 2006
+M5 compiled Sep 5 2006 15:39:50
+M5 started Tue Sep 5 15:49:24 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic
Exiting @ tick 4482 because target called exit()
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index fdd1f3d..c2bcb99 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -67,6 +67,8 @@
queue_size_a=16
queue_size_b=16
write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[0]
[system.cpu0]
type=AtomicSimpleCPU
@@ -87,6 +89,8 @@
simulate_stalls=false
system=system
width=1
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu0.dtb]
type=AlphaDTB
@@ -115,6 +119,8 @@
simulate_stalls=false
system=system
width=1
+dcache_port=system.membus.port[5]
+icache_port=system.membus.port[4]
[system.cpu1.dtb]
type=AlphaDTB
@@ -169,16 +175,20 @@
[system.iobus]
type=Bus
bus_id=0
+default=system.tsunami.pciconfig.pio
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
[system.membus]
type=Bus
bus_id=1
+port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[1]
[system.sim_console]
type=SimConsole
@@ -217,6 +227,7 @@
platform=system.tsunami
system=system
tsunami=system.tsunami
+pio=system.iobus.port[1]
[system.tsunami.console]
type=AlphaConsole
@@ -227,6 +238,7 @@
platform=system.tsunami
sim_console=system.sim_console
system=system
+pio=system.iobus.port[25]
[system.tsunami.etherint]
type=NSGigEInt
@@ -262,6 +274,9 @@
tx_delay=2000
tx_fifo_size=524288
tx_thread=false
+config=system.iobus.port[28]
+dma=system.iobus.port[29]
+pio=system.iobus.port[27]
[system.tsunami.ethernet.configdata]
type=PciConfigData
@@ -305,6 +320,7 @@
pio_size=393216
platform=system.tsunami
system=system
+pio=system.iobus.port[9]
[system.tsunami.fake_ata0]
type=IsaFake
@@ -313,6 +329,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[20]
[system.tsunami.fake_ata1]
type=IsaFake
@@ -321,6 +338,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[21]
[system.tsunami.fake_pnp_addr]
type=IsaFake
@@ -329,6 +347,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[10]
[system.tsunami.fake_pnp_read0]
type=IsaFake
@@ -337,6 +356,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[12]
[system.tsunami.fake_pnp_read1]
type=IsaFake
@@ -345,6 +365,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[13]
[system.tsunami.fake_pnp_read2]
type=IsaFake
@@ -353,6 +374,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[14]
[system.tsunami.fake_pnp_read3]
type=IsaFake
@@ -361,6 +383,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[15]
[system.tsunami.fake_pnp_read4]
type=IsaFake
@@ -369,6 +392,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[16]
[system.tsunami.fake_pnp_read5]
type=IsaFake
@@ -377,6 +401,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[17]
[system.tsunami.fake_pnp_read6]
type=IsaFake
@@ -385,6 +410,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[18]
[system.tsunami.fake_pnp_read7]
type=IsaFake
@@ -393,6 +419,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[19]
[system.tsunami.fake_pnp_write]
type=IsaFake
@@ -401,6 +428,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[11]
[system.tsunami.fake_ppc]
type=IsaFake
@@ -409,6 +437,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[8]
[system.tsunami.fake_sm_chip]
type=IsaFake
@@ -417,6 +446,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[3]
[system.tsunami.fake_uart1]
type=IsaFake
@@ -425,6 +455,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[4]
[system.tsunami.fake_uart2]
type=IsaFake
@@ -433,6 +464,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[5]
[system.tsunami.fake_uart3]
type=IsaFake
@@ -441,6 +473,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[6]
[system.tsunami.fake_uart4]
type=IsaFake
@@ -449,6 +482,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[7]
[system.tsunami.fb]
type=BadDevice
@@ -457,6 +491,7 @@
pio_latency=2
platform=system.tsunami
system=system
+pio=system.iobus.port[22]
[system.tsunami.ide]
type=IdeController
@@ -470,6 +505,9 @@
pio_latency=2
platform=system.tsunami
system=system
+config=system.iobus.port[30]
+dma=system.iobus.port[31]
+pio=system.iobus.port[26]
[system.tsunami.ide.configdata]
type=PciConfigData
@@ -515,6 +553,7 @@
system=system
time=1136073600
tsunami=system.tsunami
+pio=system.iobus.port[23]
[system.tsunami.pchip]
type=TsunamiPChip
@@ -523,6 +562,7 @@
platform=system.tsunami
system=system
tsunami=system.tsunami
+pio=system.iobus.port[2]
[system.tsunami.pciconfig]
type=PciConfigAll
@@ -531,6 +571,7 @@
platform=system.tsunami
size=16777216
system=system
+pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
@@ -539,6 +580,7 @@
platform=system.tsunami
sim_console=system.sim_console
system=system
+pio=system.iobus.port[24]
[trace]
bufsize=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
index 8b48b8a..c7715ae 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1433278 # Simulator instruction rate (inst/s)
-host_mem_usage 194568 # Number of bytes of host memory used
-host_seconds 44.14 # Real time elapsed on the host
-host_tick_rate 80562367 # Simulator tick rate (ticks/s)
+host_inst_rate 1382023 # Simulator instruction rate (inst/s)
+host_mem_usage 194588 # Number of bytes of host memory used
+host_seconds 45.78 # Real time elapsed on the host
+host_tick_rate 77681401 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks
sim_insts 63264995 # Number of instructions simulated
sim_seconds 1.778030 # Number of seconds simulated
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
index d503ac3..c8330ee 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
@@ -5,8 +5,8 @@
All Rights Reserved
-M5 compiled Aug 17 2006 23:41:21
-M5 started Thu Aug 17 23:50:27 2006
+M5 compiled Sep 5 2006 15:32:34
+M5 started Tue Sep 5 15:43:12 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Exiting @ tick 3556060806 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 2ee207b..c017495 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -67,6 +67,8 @@
queue_size_a=16
queue_size_b=16
write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
@@ -87,6 +89,8 @@
simulate_stalls=false
system=system
width=1
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=AlphaDTB
@@ -141,16 +145,20 @@
[system.iobus]
type=Bus
bus_id=0
+default=system.tsunami.pciconfig.pio
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
[system.membus]
type=Bus
bus_id=1
+port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[1]
[system.sim_console]
type=SimConsole
@@ -189,6 +197,7 @@
platform=system.tsunami
system=system
tsunami=system.tsunami
+pio=system.iobus.port[1]
[system.tsunami.console]
type=AlphaConsole
@@ -199,6 +208,7 @@
platform=system.tsunami
sim_console=system.sim_console
system=system
+pio=system.iobus.port[25]
[system.tsunami.etherint]
type=NSGigEInt
@@ -234,6 +244,9 @@
tx_delay=2000
tx_fifo_size=524288
tx_thread=false
+config=system.iobus.port[28]
+dma=system.iobus.port[29]
+pio=system.iobus.port[27]
[system.tsunami.ethernet.configdata]
type=PciConfigData
@@ -277,6 +290,7 @@
pio_size=393216
platform=system.tsunami
system=system
+pio=system.iobus.port[9]
[system.tsunami.fake_ata0]
type=IsaFake
@@ -285,6 +299,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[20]
[system.tsunami.fake_ata1]
type=IsaFake
@@ -293,6 +308,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[21]
[system.tsunami.fake_pnp_addr]
type=IsaFake
@@ -301,6 +317,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[10]
[system.tsunami.fake_pnp_read0]
type=IsaFake
@@ -309,6 +326,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[12]
[system.tsunami.fake_pnp_read1]
type=IsaFake
@@ -317,6 +335,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[13]
[system.tsunami.fake_pnp_read2]
type=IsaFake
@@ -325,6 +344,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[14]
[system.tsunami.fake_pnp_read3]
type=IsaFake
@@ -333,6 +353,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[15]
[system.tsunami.fake_pnp_read4]
type=IsaFake
@@ -341,6 +362,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[16]
[system.tsunami.fake_pnp_read5]
type=IsaFake
@@ -349,6 +371,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[17]
[system.tsunami.fake_pnp_read6]
type=IsaFake
@@ -357,6 +380,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[18]
[system.tsunami.fake_pnp_read7]
type=IsaFake
@@ -365,6 +389,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[19]
[system.tsunami.fake_pnp_write]
type=IsaFake
@@ -373,6 +398,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[11]
[system.tsunami.fake_ppc]
type=IsaFake
@@ -381,6 +407,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[8]
[system.tsunami.fake_sm_chip]
type=IsaFake
@@ -389,6 +416,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[3]
[system.tsunami.fake_uart1]
type=IsaFake
@@ -397,6 +425,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[4]
[system.tsunami.fake_uart2]
type=IsaFake
@@ -405,6 +434,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[5]
[system.tsunami.fake_uart3]
type=IsaFake
@@ -413,6 +443,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[6]
[system.tsunami.fake_uart4]
type=IsaFake
@@ -421,6 +452,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[7]
[system.tsunami.fb]
type=BadDevice
@@ -429,6 +461,7 @@
pio_latency=2
platform=system.tsunami
system=system
+pio=system.iobus.port[22]
[system.tsunami.ide]
type=IdeController
@@ -442,6 +475,9 @@
pio_latency=2
platform=system.tsunami
system=system
+config=system.iobus.port[30]
+dma=system.iobus.port[31]
+pio=system.iobus.port[26]
[system.tsunami.ide.configdata]
type=PciConfigData
@@ -487,6 +523,7 @@
system=system
time=1136073600
tsunami=system.tsunami
+pio=system.iobus.port[23]
[system.tsunami.pchip]
type=TsunamiPChip
@@ -495,6 +532,7 @@
platform=system.tsunami
system=system
tsunami=system.tsunami
+pio=system.iobus.port[2]
[system.tsunami.pciconfig]
type=PciConfigAll
@@ -503,6 +541,7 @@
platform=system.tsunami
size=16777216
system=system
+pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
@@ -511,6 +550,7 @@
platform=system.tsunami
sim_console=system.sim_console
system=system
+pio=system.iobus.port[24]
[trace]
bufsize=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
index a4b2a85..3a7dc1c 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1371456 # Simulator instruction rate (inst/s)
-host_mem_usage 194364 # Number of bytes of host memory used
-host_seconds 43.70 # Real time elapsed on the host
-host_tick_rate 79947218 # Simulator tick rate (ticks/s)
+host_inst_rate 1346129 # Simulator instruction rate (inst/s)
+host_mem_usage 194392 # Number of bytes of host memory used
+host_seconds 44.52 # Real time elapsed on the host
+host_tick_rate 78470813 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks
sim_insts 59929520 # Number of instructions simulated
sim_seconds 1.746773 # Number of seconds simulated
@@ -138,7 +138,7 @@
system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle no value # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
index 372fa29..c04cd50 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
@@ -5,8 +5,8 @@
All Rights Reserved
-M5 compiled Aug 17 2006 23:41:21
-M5 started Thu Aug 17 23:41:25 2006
+M5 compiled Sep 5 2006 15:32:34
+M5 started Tue Sep 5 15:42:26 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
Exiting @ tick 3493545624 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 430daba..97e9007 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -67,6 +67,8 @@
queue_size_a=16
queue_size_b=16
write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[0]
[system.cpu0]
type=TimingSimpleCPU
@@ -85,6 +87,8 @@
mem=system.physmem
profile=0
system=system
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu0.dtb]
type=AlphaDTB
@@ -111,6 +115,8 @@
mem=system.physmem
profile=0
system=system
+dcache_port=system.membus.port[5]
+icache_port=system.membus.port[4]
[system.cpu1.dtb]
type=AlphaDTB
@@ -165,16 +171,20 @@
[system.iobus]
type=Bus
bus_id=0
+default=system.tsunami.pciconfig.pio
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
[system.membus]
type=Bus
bus_id=1
+port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[1]
[system.sim_console]
type=SimConsole
@@ -213,6 +223,7 @@
platform=system.tsunami
system=system
tsunami=system.tsunami
+pio=system.iobus.port[1]
[system.tsunami.console]
type=AlphaConsole
@@ -223,6 +234,7 @@
platform=system.tsunami
sim_console=system.sim_console
system=system
+pio=system.iobus.port[25]
[system.tsunami.etherint]
type=NSGigEInt
@@ -258,6 +270,9 @@
tx_delay=2000
tx_fifo_size=524288
tx_thread=false
+config=system.iobus.port[28]
+dma=system.iobus.port[29]
+pio=system.iobus.port[27]
[system.tsunami.ethernet.configdata]
type=PciConfigData
@@ -301,6 +316,7 @@
pio_size=393216
platform=system.tsunami
system=system
+pio=system.iobus.port[9]
[system.tsunami.fake_ata0]
type=IsaFake
@@ -309,6 +325,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[20]
[system.tsunami.fake_ata1]
type=IsaFake
@@ -317,6 +334,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[21]
[system.tsunami.fake_pnp_addr]
type=IsaFake
@@ -325,6 +343,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[10]
[system.tsunami.fake_pnp_read0]
type=IsaFake
@@ -333,6 +352,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[12]
[system.tsunami.fake_pnp_read1]
type=IsaFake
@@ -341,6 +361,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[13]
[system.tsunami.fake_pnp_read2]
type=IsaFake
@@ -349,6 +370,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[14]
[system.tsunami.fake_pnp_read3]
type=IsaFake
@@ -357,6 +379,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[15]
[system.tsunami.fake_pnp_read4]
type=IsaFake
@@ -365,6 +388,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[16]
[system.tsunami.fake_pnp_read5]
type=IsaFake
@@ -373,6 +397,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[17]
[system.tsunami.fake_pnp_read6]
type=IsaFake
@@ -381,6 +406,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[18]
[system.tsunami.fake_pnp_read7]
type=IsaFake
@@ -389,6 +415,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[19]
[system.tsunami.fake_pnp_write]
type=IsaFake
@@ -397,6 +424,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[11]
[system.tsunami.fake_ppc]
type=IsaFake
@@ -405,6 +433,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[8]
[system.tsunami.fake_sm_chip]
type=IsaFake
@@ -413,6 +442,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[3]
[system.tsunami.fake_uart1]
type=IsaFake
@@ -421,6 +451,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[4]
[system.tsunami.fake_uart2]
type=IsaFake
@@ -429,6 +460,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[5]
[system.tsunami.fake_uart3]
type=IsaFake
@@ -437,6 +469,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[6]
[system.tsunami.fake_uart4]
type=IsaFake
@@ -445,6 +478,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[7]
[system.tsunami.fb]
type=BadDevice
@@ -453,6 +487,7 @@
pio_latency=2
platform=system.tsunami
system=system
+pio=system.iobus.port[22]
[system.tsunami.ide]
type=IdeController
@@ -466,6 +501,9 @@
pio_latency=2
platform=system.tsunami
system=system
+config=system.iobus.port[30]
+dma=system.iobus.port[31]
+pio=system.iobus.port[26]
[system.tsunami.ide.configdata]
type=PciConfigData
@@ -511,6 +549,7 @@
system=system
time=1136073600
tsunami=system.tsunami
+pio=system.iobus.port[23]
[system.tsunami.pchip]
type=TsunamiPChip
@@ -519,6 +558,7 @@
platform=system.tsunami
system=system
tsunami=system.tsunami
+pio=system.iobus.port[2]
[system.tsunami.pciconfig]
type=PciConfigAll
@@ -527,6 +567,7 @@
platform=system.tsunami
size=16777216
system=system
+pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
@@ -535,6 +576,7 @@
platform=system.tsunami
sim_console=system.sim_console
system=system
+pio=system.iobus.port[24]
[trace]
bufsize=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
index 1dc6745..666766e 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 845052 # Simulator instruction rate (inst/s)
-host_mem_usage 194484 # Number of bytes of host memory used
-host_seconds 74.66 # Real time elapsed on the host
-host_tick_rate 47409778 # Simulator tick rate (ticks/s)
+host_inst_rate 804715 # Simulator instruction rate (inst/s)
+host_mem_usage 194628 # Number of bytes of host memory used
+host_seconds 78.40 # Real time elapsed on the host
+host_tick_rate 45146741 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks
sim_insts 63088076 # Number of instructions simulated
sim_seconds 1.769718 # Number of seconds simulated
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
index 47e826d..33c1946 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
@@ -5,8 +5,8 @@
All Rights Reserved
-M5 compiled Aug 17 2006 23:41:21
-M5 started Thu Aug 17 23:51:44 2006
+M5 compiled Sep 5 2006 15:32:34
+M5 started Tue Sep 5 15:45:11 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Exiting @ tick 3539435029 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 3718990..2a354de 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -67,6 +67,8 @@
queue_size_a=16
queue_size_b=16
write_ack=false
+side_a=system.iobus.port[0]
+side_b=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
@@ -85,6 +87,8 @@
mem=system.physmem
profile=0
system=system
+dcache_port=system.membus.port[3]
+icache_port=system.membus.port[2]
[system.cpu.dtb]
type=AlphaDTB
@@ -139,16 +143,20 @@
[system.iobus]
type=Bus
bus_id=0
+default=system.tsunami.pciconfig.pio
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
[system.membus]
type=Bus
bus_id=1
+port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[1]
[system.sim_console]
type=SimConsole
@@ -187,6 +195,7 @@
platform=system.tsunami
system=system
tsunami=system.tsunami
+pio=system.iobus.port[1]
[system.tsunami.console]
type=AlphaConsole
@@ -197,6 +206,7 @@
platform=system.tsunami
sim_console=system.sim_console
system=system
+pio=system.iobus.port[25]
[system.tsunami.etherint]
type=NSGigEInt
@@ -232,6 +242,9 @@
tx_delay=2000
tx_fifo_size=524288
tx_thread=false
+config=system.iobus.port[28]
+dma=system.iobus.port[29]
+pio=system.iobus.port[27]
[system.tsunami.ethernet.configdata]
type=PciConfigData
@@ -275,6 +288,7 @@
pio_size=393216
platform=system.tsunami
system=system
+pio=system.iobus.port[9]
[system.tsunami.fake_ata0]
type=IsaFake
@@ -283,6 +297,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[20]
[system.tsunami.fake_ata1]
type=IsaFake
@@ -291,6 +306,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[21]
[system.tsunami.fake_pnp_addr]
type=IsaFake
@@ -299,6 +315,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[10]
[system.tsunami.fake_pnp_read0]
type=IsaFake
@@ -307,6 +324,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[12]
[system.tsunami.fake_pnp_read1]
type=IsaFake
@@ -315,6 +333,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[13]
[system.tsunami.fake_pnp_read2]
type=IsaFake
@@ -323,6 +342,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[14]
[system.tsunami.fake_pnp_read3]
type=IsaFake
@@ -331,6 +351,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[15]
[system.tsunami.fake_pnp_read4]
type=IsaFake
@@ -339,6 +360,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[16]
[system.tsunami.fake_pnp_read5]
type=IsaFake
@@ -347,6 +369,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[17]
[system.tsunami.fake_pnp_read6]
type=IsaFake
@@ -355,6 +378,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[18]
[system.tsunami.fake_pnp_read7]
type=IsaFake
@@ -363,6 +387,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[19]
[system.tsunami.fake_pnp_write]
type=IsaFake
@@ -371,6 +396,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[11]
[system.tsunami.fake_ppc]
type=IsaFake
@@ -379,6 +405,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[8]
[system.tsunami.fake_sm_chip]
type=IsaFake
@@ -387,6 +414,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[3]
[system.tsunami.fake_uart1]
type=IsaFake
@@ -395,6 +423,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[4]
[system.tsunami.fake_uart2]
type=IsaFake
@@ -403,6 +432,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[5]
[system.tsunami.fake_uart3]
type=IsaFake
@@ -411,6 +441,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[6]
[system.tsunami.fake_uart4]
type=IsaFake
@@ -419,6 +450,7 @@
pio_size=8
platform=system.tsunami
system=system
+pio=system.iobus.port[7]
[system.tsunami.fb]
type=BadDevice
@@ -427,6 +459,7 @@
pio_latency=2
platform=system.tsunami
system=system
+pio=system.iobus.port[22]
[system.tsunami.ide]
type=IdeController
@@ -440,6 +473,9 @@
pio_latency=2
platform=system.tsunami
system=system
+config=system.iobus.port[30]
+dma=system.iobus.port[31]
+pio=system.iobus.port[26]
[system.tsunami.ide.configdata]
type=PciConfigData
@@ -485,6 +521,7 @@
system=system
time=1136073600
tsunami=system.tsunami
+pio=system.iobus.port[23]
[system.tsunami.pchip]
type=TsunamiPChip
@@ -493,6 +530,7 @@
platform=system.tsunami
system=system
tsunami=system.tsunami
+pio=system.iobus.port[2]
[system.tsunami.pciconfig]
type=PciConfigAll
@@ -501,6 +539,7 @@
platform=system.tsunami
size=16777216
system=system
+pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
@@ -509,6 +548,7 @@
platform=system.tsunami
sim_console=system.sim_console
system=system
+pio=system.iobus.port[24]
[trace]
bufsize=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
index 5e5ce79..0adb4cc 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 859270 # Simulator instruction rate (inst/s)
-host_mem_usage 194168 # Number of bytes of host memory used
-host_seconds 69.73 # Real time elapsed on the host
-host_tick_rate 50283954 # Simulator tick rate (ticks/s)
+host_inst_rate 835908 # Simulator instruction rate (inst/s)
+host_mem_usage 194192 # Number of bytes of host memory used
+host_seconds 71.68 # Real time elapsed on the host
+host_tick_rate 48916813 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks
sim_insts 59915182 # Number of instructions simulated
sim_seconds 1.753109 # Number of seconds simulated
@@ -138,7 +138,7 @@
system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle no value # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
index 4741dd7..6204251 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
@@ -1,4 +1,4 @@
0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006
-Listening for console connection on port 3457
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
+Listening for console connection on port 3456
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
warn: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
index 3ad24fa..2739943 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
@@ -5,8 +5,8 @@
All Rights Reserved
-M5 compiled Aug 17 2006 23:41:21
-M5 started Thu Aug 17 23:41:25 2006
+M5 compiled Sep 5 2006 15:32:34
+M5 started Tue Sep 5 15:43:59 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
Exiting @ tick 3506218170 because m5_exit instruction encountered
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index 4f9d886..a4b1037 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -68,6 +68,8 @@
system=system
width=1
workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
[system.cpu.workload]
type=EioProcess
@@ -79,12 +81,14 @@
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
index 508b7b1..0132ecf 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1431500 # Simulator instruction rate (inst/s)
-host_mem_usage 146556 # Number of bytes of host memory used
-host_seconds 0.35 # Real time elapsed on the host
-host_tick_rate 1429839 # Simulator tick rate (ticks/s)
+host_inst_rate 1397534 # Simulator instruction rate (inst/s)
+host_mem_usage 147632 # Number of bytes of host memory used
+host_seconds 0.36 # Real time elapsed on the host
+host_tick_rate 1395943 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500000 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
index 20413a2..d3edcdc 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
@@ -7,8 +7,8 @@
All Rights Reserved
-M5 compiled Aug 18 2006 00:06:43
-M5 started Fri Aug 18 00:12:49 2006
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:20 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
Exiting @ tick 499999 because a thread reached the max instruction count
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index 0352c1b..27568ad 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -66,6 +66,8 @@
mem=system.cpu.dcache
system=system
workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
@@ -104,6 +106,8 @@
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
[system.cpu.icache]
type=BaseCache
@@ -142,6 +146,8 @@
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
[system.cpu.l2cache]
type=BaseCache
@@ -180,10 +186,13 @@
trace_addr=0
two_queue=false
write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
type=EioProcess
@@ -195,12 +204,14 @@
[system.membus]
type=Bus
bus_id=0
+port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
+port=system.membus.port[0]
[trace]
bufsize=0
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
index 17e8cb6..6339e48 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 310464 # Simulator instruction rate (inst/s)
-host_mem_usage 159200 # Number of bytes of host memory used
-host_seconds 1.61 # Real time elapsed on the host
-host_tick_rate 423570 # Simulator tick rate (ticks/s)
+host_inst_rate 620120 # Simulator instruction rate (inst/s)
+host_mem_usage 159196 # Number of bytes of host memory used
+host_seconds 0.81 # Real time elapsed on the host
+host_tick_rate 845850 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500000 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
index bb4db9d..158dcfe 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
@@ -7,8 +7,8 @@
All Rights Reserved
-M5 compiled Aug 21 2006 14:18:48
-M5 started Mon Aug 21 14:19:29 2006
+M5 compiled Sep 5 2006 15:28:48
+M5 started Tue Sep 5 15:42:20 2006
M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
Exiting @ tick 682354 because a thread reached the max instruction count
diff --git a/util/cscope-find.py b/util/cscope-find.py
new file mode 100755
index 0000000..1775f18
--- /dev/null
+++ b/util/cscope-find.py
@@ -0,0 +1,38 @@
+#! /usr/bin/python
+
+# Generate list of files to index with cscope.
+
+# From the m5 directory, run:
+# util/cscope-find.py > cscope.files
+# cscope -b
+
+import os
+
+# absolute paths to skip
+skipdirs = [ 'src/unittest', 'src/doxygen' ]
+
+# suffixes of files to index
+suffixes = [ '.cc', '.hh', '.c', '.h' ]
+
+def oksuffix(f):
+ for s in suffixes:
+ if f.endswith(s):
+ return True
+ return False
+
+for dirpath,subdirs,files in os.walk('src'):
+ # filter out undesirable subdirectories
+ for i,dir in enumerate(subdirs):
+ if dir == 'SCCS':
+ del subdirs[i]
+ break
+
+ # filter out undesriable absolute paths
+ if dirpath in skipdirs:
+ del subdirs[:]
+ continue
+
+ # find C/C++ sources
+ okfiles = [f for f in files if oksuffix(f)]
+ if okfiles:
+ print '\n'.join([os.path.join(dirpath, f) for f in okfiles])
diff --git a/util/regress b/util/regress
index 27880d5..8e60b6f 100755
--- a/util/regress
+++ b/util/regress
@@ -32,39 +32,22 @@
import optparse
import datetime
-#
-# Regression invocation:
-#
-# regress \
-# --workdir poolfs \
-# --scons-opts 'BATCH=yes USE_MYSQL=no -j 30 -Q' \
-# --recurse
-
progname = os.path.basename(sys.argv[0])
optparser = optparse.OptionParser()
optparser.add_option('-v', '--verbose', dest='verbose', action='store_true',
default=False,
help='echo commands before executing')
-optparser.add_option('--scratch', dest='scratch', action='store_true',
- default=False,
- help='rebuld from scratch')
optparser.add_option('--builds', dest='builds',
default='ALPHA_SE,ALPHA_FS,MIPS_SE,SPARC_SE',
- help='comma-separated list of builds to test')
+ help='comma-separated list of build targets to test '
+ " (default: '%default')" )
optparser.add_option('--variants', dest='variants',
default='opt',
- help='comma-separated list of build variants to test')
-optparser.add_option('--workdir', dest='workdir',
- help='directory for checked-out source trees')
+ help='comma-separated list of build variants to test '
+ " (default: '%default')" )
optparser.add_option('--scons-opts', dest='scons_opts', default='',
- help='scons options')
-optparser.add_option('--no-pull', dest='pull', action='store_false',
- default=True,
- help="don't pull changes from repository")
-optparser.add_option('--recurse', dest='recurse', action='store_true',
- default=False,
- help='call recursively to get summary up front')
+ help='scons options', metavar='OPTS')
(options, tests) = optparser.parse_args()
@@ -73,9 +56,6 @@
builds = options.builds.split(',')
variants = options.variants.split(',')
-# Repositories to clone/update
-repos = ['m5']
-
# Call os.system() and raise exception if return status is non-zero
def system(cmd):
if options.verbose:
@@ -93,56 +73,11 @@
s = "'%s'" % s
return s
-# The '--recurse' option invokes scons once to perform any necessary
-# rebuilds/test runs with the (possibly verbose) output placed in a
-# log file, then (if the buld was successful) returns scons to print a
-# summary of the results.
-if options.recurse:
- sys.argv.remove('--recurse') # avoid infinite recursion...
- timestr = datetime.datetime.now().isoformat('-')[:19]
- logfile = '%s-%s' % (progname, timestr)
- # quote args for shell
- qargs = [shellquote(a) for a in sys.argv]
- # always run the sub-job in verbose mode
- qargs.append('-v')
- cmd = '%s > %s 2>&1' % (' '.join(qargs), logfile)
- try:
- system(cmd)
- except OSError, exc:
- print "Error: recursive invocation failed, aborting."
- print exc
- print "======================="
- os.system('cat %s' % logfile)
- sys.exit(1)
- # recursive call succeeded... re-run to generate summary
- # don't *re*-build from scratch now
- options.scratch = False
- # no need to re-pull since the recursive call shoudl have done that
- options.pull = False
- print "Recursive invocation successful, see %s for output." % logfile
-
try:
- if options.workdir:
- if options.verbose:
- print 'cd', options.workdir
- os.chdir(options.workdir)
-
- if options.scratch:
- for dir in repos:
- system('rm -rf %s' % dir)
- system('bk clone /bk/%s' % dir)
- elif options.pull:
- for dir in repos:
- system('cd %s; bk pull' % dir)
-
if not tests:
print "No tests specified."
sys.exit(1)
- if options.verbose:
- print 'cd m5'
- os.chdir('m5')
-
if 'all' in tests:
targets = ['build/%s/tests/%s' % (build, variant)
for build in builds
