resources: update the parsec and gapbs configs
This change updates the cache configs in parsec and
gapbs scripts to not use cpu.itb/dtb.
Change-Id: I232fc486f20a09b937b5f3ea0a977626d3046f66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/46699
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>
diff --git a/src/gapbs/configs/system/caches.py b/src/gapbs/configs/system/caches.py
index 6f82baa..a58f3af 100644
--- a/src/gapbs/configs/system/caches.py
+++ b/src/gapbs/configs/system/caches.py
@@ -118,8 +118,8 @@
"""
self.mmubus = L2XBar()
self.cpu_side = self.mmubus.mem_side_ports
- for tlb in [cpu.itb, cpu.dtb]:
- self.mmubus.cpu_side_ports = tlb.walker.port
+ cpu.mmu.connectWalkerPorts(
+ self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
diff --git a/src/parsec/configs/system/caches.py b/src/parsec/configs/system/caches.py
index 497c7e4..4316aa1 100644
--- a/src/parsec/configs/system/caches.py
+++ b/src/parsec/configs/system/caches.py
@@ -114,8 +114,8 @@
"""
self.mmubus = L2XBar()
self.cpu_side = self.mmubus.mem_side_ports
- for tlb in [cpu.itb, cpu.dtb]:
- self.mmubus.cpu_side_ports = tlb.walker.port
+ cpu.mmu.connectWalkerPorts(
+ self.mmubus.cpu_side_ports, self.mmubus.cpu_side_ports)
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
