commit 7089bff223b6fca85546f3f527d5f7518c7fddf0
author Hoa Nguyen <hoanguyen@ucdavis.edu> Mon Dec 07 23:06:09 2020 -0800
committer Hoa Nguyen <hoanguyen@ucdavis.edu> Tue Dec 08 23:05:50 2020 +0000
tree ebbe2fec3d83c64f1af74cd8c7e8136c9e228541
parent d75fecf8471d966a8451a2427fe02cd378a36a92

resources: Fix typos in gem5 ruby configs of npb and spec-2006

Sequencer objects have "in_ports", and do not have "in_port" param.

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I86201c85338b176c95ce9bda8d9b68427e4fe870
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5-resources/+/38390
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>

src/npb/configs/system/MESI_Two_Level.py

diff --git a/src/npb/configs/system/MESI_Two_Level.py b/src/npb/configs/system/MESI_Two_Level.py
index eac0834..bc72d00 100755
--- a/src/npb/configs/system/MESI_Two_Level.py
+++ b/src/npb/configs/system/MESI_Two_Level.py
@@ -88,7 +88,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]
 

src/npb/configs/system/MI_example_caches.py

diff --git a/src/npb/configs/system/MI_example_caches.py b/src/npb/configs/system/MI_example_caches.py
index 907c3f0..cdc8771 100755
--- a/src/npb/configs/system/MI_example_caches.py
+++ b/src/npb/configs/system/MI_example_caches.py
@@ -89,7 +89,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]
 

src/npb/configs/system/MOESI_CMP_directory.py

diff --git a/src/npb/configs/system/MOESI_CMP_directory.py b/src/npb/configs/system/MOESI_CMP_directory.py
index bf31ab7..1aec746 100755
--- a/src/npb/configs/system/MOESI_CMP_directory.py
+++ b/src/npb/configs/system/MOESI_CMP_directory.py
@@ -92,7 +92,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]
 

src/spec-2006/configs/system/MESI_Two_Level.py

diff --git a/src/spec-2006/configs/system/MESI_Two_Level.py b/src/spec-2006/configs/system/MESI_Two_Level.py
index 0513041..c200b5e 100644
--- a/src/spec-2006/configs/system/MESI_Two_Level.py
+++ b/src/spec-2006/configs/system/MESI_Two_Level.py
@@ -91,7 +91,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]
 

src/spec-2006/configs/system/MI_example_caches.py

diff --git a/src/spec-2006/configs/system/MI_example_caches.py b/src/spec-2006/configs/system/MI_example_caches.py
index b8fd7b4..8435924 100644
--- a/src/spec-2006/configs/system/MI_example_caches.py
+++ b/src/spec-2006/configs/system/MI_example_caches.py
@@ -92,7 +92,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]
 

src/spec-2006/configs/system/MOESI_CMP_directory.py

diff --git a/src/spec-2006/configs/system/MOESI_CMP_directory.py b/src/spec-2006/configs/system/MOESI_CMP_directory.py
index c657df7..ec13fda 100644
--- a/src/spec-2006/configs/system/MOESI_CMP_directory.py
+++ b/src/spec-2006/configs/system/MOESI_CMP_directory.py
@@ -92,7 +92,7 @@
                                 pio_response_port = iobus.mem_side_ports
                                 ) for i in range(len(cpus))] + \
                           [DMASequencer(version = i,
-                                        in_port = port)
+                                        in_ports = port)
                             for i,port in enumerate(dma_ports)
                           ]