1. 2dd0eed cpu: Fix fast build broken due to unused variable by Giacomo Travaglini · 3 days ago master
  2. 9e340ba systemc: Add a systemc_home directory which maps to the ext headers. by Gabe Black · 9 days ago
  3. 95c0aef systemc: Make an include in src/systemc/ext use a relative path. by Gabe Black · 9 days ago
  4. d39573a cpu: Added 8KB and 64KB TAGE-SC-L branch predictor by Javier Bueno · 3 weeks ago
  5. 224f2d5 configs: simpoint-profile usable with NonCachingCPUs only by Giacomo Travaglini · 4 weeks ago
  6. e67a3d1 python: Remove uses of tuple unpacking in function params by Andreas Sandberg · 3 weeks ago
  7. 23af972 python: Replace deprecated repr syntax by Andreas Sandberg · 3 weeks ago
  8. ac00ec1 python: Switch from using compare to key in list sort by Andreas Sandberg · 3 weeks ago
  9. c5e8e0e tests: add cpu tests to the new testing infrastructure by Ayaz Akram · 4 weeks ago
  10. 308a558 tests: Move test programs paths to related test scripts by Ayaz Akram · 4 weeks ago
  11. fe29653 sim-se: update the arm kernel version by Ayaz Akram · 4 weeks ago
  12. 9ac977d tests: Convert memtest to new framework by Jason Lowe-Power · 6 months ago
  13. 3086d51 tests: Convert tgen-simple-memory to new framework by Jason Lowe-Power · 6 months ago
  14. 5cd4248 python: Replace dict.has_key with 'key in dict' by Andreas Sandberg · 3 weeks ago
  15. 5cf312e python: Add missing defines import by Andreas Sandberg · 6 days ago
  16. 6e08be1 python: Replace DictMixin with Mapping / MutableMapping by Andreas Sandberg · 3 weeks ago
  17. bc42d2f python: Replace orderdict with collections.OrderedDict by Andreas Sandberg · 6 days ago
  18. 31dff7f python: Update use of exec to work with Python 3 by Andreas Sandberg · 3 weeks ago
  19. b3195c4 python: Switch to using open instead of file by Andreas Sandberg · 3 weeks ago
  20. 626e8fa mem-cache: Irregular Stream Buffer Prefetcher by Javier Bueno · 2 months ago
  21. 9d4d620 system-arm: Fix dtsi dependencies in Makefile by Kevin Brodsky · 14 days ago
  22. ee9293d mem-cache: Added the Delta Correlating Prediction Tables Prefetcher by Javier Bueno · 12 days ago
  23. 1f008aa tests: Rewrite Makefiles for pthreads test by Andreas Sandberg · 6 weeks ago
  24. ef71a98 python: Don't assume SimObjects live in the global namespace by Andreas Sandberg · 3 weeks ago
  25. 9fbfb45 arch-mips: Remove unused Python file by Andreas Sandberg · 6 days ago
  26. fa21127 python: Make exception handling Python 3 safe by Andreas Sandberg · 3 weeks ago
  27. 6ba4545 python: Fix native module initialisation on Python 3 by Andreas Sandberg · 3 weeks ago
  28. 15e497d mem-ruby: Fixing Topology by Pouya Fotouhi · 4 weeks ago
  29. 8d79332 mem-ruby: Fixing MESI Three Level by Pouya Fotouhi · 4 weeks ago
  30. 502af7c systemc: config: Don't inject a custom argv[0] in sc_main.py. by Gabe Black · 6 days ago
  31. eb5e99e systemc: configs: Add a very simple config which just runs sc_main. by Gabe Black · 9 days ago
  32. bdef435 systemc: Change the type of a loop counter to avoid a warning. by Gabe Black · 9 days ago
  33. 8174d7c scons: Change an = to a += when accumulating sources from filters. by Gabe Black · 9 days ago
  34. da6e8b0 systemc: scons: Specify RPATH as a list. by Gabe Black · 9 days ago
  35. bcf6983 cpu: Proposal for changing the indirect branch predictor interface by Jairo Balart · 6 weeks ago
  36. 4f4846c riscv: fix AMO, LR and SC instructions by Tuan Ta · 1 year ago
  37. 25dc765 cpu: support atomic memory request type with AtomicOpFunctor by Tuan Ta · 1 year, 1 month ago
  38. 165a7da kern,sim: implement FUTEX_WAKE_OP by Moyang Wang · 11 months ago
  39. 758b62c sim, kern: support FUTEX_CMP_REQUEUE by Moyang Wang · 11 months ago
  40. 42b063a sim: handle the case when there're not enough HW thread contexts by Tuan Ta · 11 months ago
  41. 2eb57c7 riscv: fixed syscall return value by Tuan Ta · 11 months ago
  42. e437086 cpu: fix how branching is handled when a thread is suspended in MinorCPU by Tuan Ta · 11 months ago
  43. 6a6668b cpu: stop scheduling suspended threads in all stages of MinorCPU by Tuan Ta · 11 months ago
  44. e74921e riscv: ignore nanosleep syscall by Tuan Ta · 11 months ago
  45. bae0edb sim,cpu: make exit_group halt all threads in a group by Tuan Ta · 11 months ago
  46. 72d1d29 arch-riscv: initialize RISC-V's thread pointer register in clone syscall by Tuan Ta · 11 months ago
  47. cf45f22 sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET ops by Tuan Ta · 11 months ago
  48. e541567 cpu: fixed how O3 CPU executes an exit system call by Tuan Ta · 11 months ago
  49. aefae9d arch-arm: Fix Virtual interrupts in AArch64 by Giacomo Travaglini · 3 weeks ago
  50. 5508866 arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30 by Giacomo Travaglini · 10 days ago
  51. b7ce897 arch-arm: Allow ArmPPI usage for PMU by Giacomo Travaglini · 3 weeks ago
  52. c2b6aac arch-arm: Fix initialization of PMU counters by Ruben Ayrapetyan · 3 weeks ago
  53. 34b73de configs, arch-arm: Using AddrRange for Realview mem_regions by Giacomo Travaglini · 14 days ago
  54. 53eadea configs: Unifiy interpretation of Realview mem_regions by Giacomo Travaglini · 14 days ago
  55. 9c5373c arch-riscv: Enable support for riscv 32-bit in SE mode. by Austin Harris · 8 weeks ago
  56. ea487f9 riscv: remove NonSpeculative flag from fence inst by Tuan Ta · 11 months ago
  57. 02dafc5 cpu: fix how a thread starts up in MinorCPU by Tuan Ta · 11 months ago
  58. 8efcc0f arch-riscv: Initialize interrupt mask by Tuan Ta · 13 days ago
  59. ff5ad43 scons: fix unused auto-generated blob variable in clang by Ciro Santilli · 3 weeks ago
  60. 9309797 sim: added missed macro definition on MacOS by Andrea Mondelli · 13 days ago
  61. 1989ce9 misc: added missing override specifier by Andrea Mondelli · 13 days ago
  62. 02d2d7b cpu: Made the Loop Predictor a SimObject by Javier Bueno · 3 weeks ago
  63. 4ba8923 cpu: Made TAGE a SimObject that can be used by other predictors by Jairo Balart · 6 weeks ago
  64. f0e2caf riscv: Get rid of ISA specific register types in Interrupts. by Austin Harris · 13 days ago
  65. 2775f55 mem-cache: Updated version of the Signature Path Prefetcher by Javier Bueno · 10 weeks ago
  66. 6684d61 dev, arm: Removed contextId variable by Anouk Van Laer · 4 weeks ago
  67. a119a96 cpu, arch: Replace the CCReg type with RegVal. by Gabe Black · 3 months ago
  68. fbdf0b6 python: Remove getCode() type workaround by Andreas Sandberg · 3 weeks ago
  69. 244a984 sim: Prepare C++ side for Python 3 by Andreas Sandberg · 3 weeks ago
  70. 2d1723a tests: Add a helper to run external scripts by Andreas Sandberg · 3 weeks ago
  71. cc59815 tests: Don't override tick rate in Ruby tests by Andreas Sandberg · 3 weeks ago
  72. b6a124d power: Get rid of some ISA specific register types. by Gabe Black · 3 months ago
  73. 6ba2888 null: Get rid of some register type definitions. by Gabe Black · 3 months ago
  74. cdfb486 mips: Stop using architecture specific register types. by Gabe Black · 3 months ago
  75. c8a744f alpha: Stop using architecture specific register types. by Gabe Black · 3 months ago
  76. b859a70 x86: Stop using/defining some ISA specific register types. by Gabe Black · 3 months ago
  77. ad775e0 riscv: Get rid of some ISA specific register types. by Gabe Black · 3 months ago
  78. 5edfb67 arch: cpu: Rename *FloatRegBits* to *FloatReg*. by Gabe Black · 3 months ago
  79. 2547416 arch,cpu: Add vector predicate registers by Giacomo Gabrielli · 4 months ago
  80. c6f5db8 configs: Enable DTB autogeneration in starter_fs.py by Giacomo Travaglini · 3 weeks ago
  81. 00ef23b arch-arm, configs: Create single instance of DTB autogeneration by Giacomo Travaglini · 3 weeks ago
  82. b2d24ff tests: fix arm regression due to kernel not found by Ciro Santilli · 3 weeks ago
  83. 9048ef0 configs: fs.py remove --generate-dtb and enable it by default by Ciro Santilli · 4 weeks ago
  84. 12eca7a configs, arch-arm: don't search for default DTB and kernel by Ciro Santilli · 3 months ago
  85. 9b6f0a9 arch-arm: Remove floatReg operand type by Giacomo Travaglini · 5 weeks ago
  86. 96e72d6 arch-arm: Use VecElem instead of FloatReg for FP instruction by Giacomo Travaglini · 9 weeks ago
  87. d8dd86d arch: Fix VecElem Operand generation in ISA parser by Giacomo Travaglini · 9 weeks ago
  88. 3d15150 cpu, arch, arch-arm: Wire unused VecElem code in the O3 model by Giacomo Travaglini · 6 weeks ago
  89. 204e932 cpu: O3 rename using the flatIndex instead of index by Giacomo Travaglini · 6 weeks ago
  90. 47fd797 arch-arm: Inital vector rename mode depending on A32/A64 by Giacomo Travaglini · 6 weeks ago
  91. b045de7 cpu: Fix VecElemClass bugs in cpu models by Giacomo Travaglini · 6 weeks ago
  92. e7c8154 cpu: Add VecElem entries in MinorCPU Scoreboard by Giacomo Travaglini · 6 weeks ago
  93. 4d44889 arch-arm: Remove unused float operands by Giacomo Travaglini · 10 weeks ago
  94. 3ec5afd arch: Provide traceback when parsing ISA code by Giacomo Travaglini · 9 weeks ago
  95. 48f3829 python: Always throw TypeError on slave-slave connections by Nicholas Lindsay · 8 months ago
  96. db190b8 hsail: Remove the MiscReg type. by Gabe Black · 3 months ago
  97. d65f3f9 base: arch: Get rid of the now unused FloatRegVal type. by Gabe Black · 3 months ago
  98. 34064c4 dev-arm: fix --generate-dtb for ARM by Ciro Santilli · 4 weeks ago
  99. 51becd2 cpu-o3: O3 LSQ Generalisation by Rekai Gonzalez-Alberquilla · 2 years ago
  100. 6379beb arch-arm: Implement LoadAcquire/StoreRelease in AArch32 by Giacomo Travaglini · 4 weeks ago