1. ca24f3e tests: Update jenkins presubmit by Jason Lowe-Power · 9 days ago master
  2. d81e7ca tests: Rebase/squash jenkins changes by Jason Lowe-Power · 3 months ago
  3. bcf6983 cpu: Proposal for changing the indirect branch predictor interface by Jairo Balart · 6 weeks ago
  4. 4f4846c riscv: fix AMO, LR and SC instructions by Tuan Ta · 1 year ago
  5. 25dc765 cpu: support atomic memory request type with AtomicOpFunctor by Tuan Ta · 1 year, 1 month ago
  6. 165a7da kern,sim: implement FUTEX_WAKE_OP by Moyang Wang · 11 months ago
  7. 758b62c sim, kern: support FUTEX_CMP_REQUEUE by Moyang Wang · 11 months ago
  8. 42b063a sim: handle the case when there're not enough HW thread contexts by Tuan Ta · 11 months ago
  9. 2eb57c7 riscv: fixed syscall return value by Tuan Ta · 11 months ago
  10. e437086 cpu: fix how branching is handled when a thread is suspended in MinorCPU by Tuan Ta · 11 months ago
  11. 6a6668b cpu: stop scheduling suspended threads in all stages of MinorCPU by Tuan Ta · 11 months ago
  12. e74921e riscv: ignore nanosleep syscall by Tuan Ta · 11 months ago
  13. bae0edb sim,cpu: make exit_group halt all threads in a group by Tuan Ta · 11 months ago
  14. 72d1d29 arch-riscv: initialize RISC-V's thread pointer register in clone syscall by Tuan Ta · 11 months ago
  15. cf45f22 sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET ops by Tuan Ta · 11 months ago
  16. e541567 cpu: fixed how O3 CPU executes an exit system call by Tuan Ta · 11 months ago
  17. aefae9d arch-arm: Fix Virtual interrupts in AArch64 by Giacomo Travaglini · 3 weeks ago
  18. 5508866 arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30 by Giacomo Travaglini · 10 days ago
  19. b7ce897 arch-arm: Allow ArmPPI usage for PMU by Giacomo Travaglini · 3 weeks ago
  20. c2b6aac arch-arm: Fix initialization of PMU counters by Ruben Ayrapetyan · 3 weeks ago
  21. 34b73de configs, arch-arm: Using AddrRange for Realview mem_regions by Giacomo Travaglini · 14 days ago
  22. 53eadea configs: Unifiy interpretation of Realview mem_regions by Giacomo Travaglini · 14 days ago
  23. 9c5373c arch-riscv: Enable support for riscv 32-bit in SE mode. by Austin Harris · 8 weeks ago
  24. ea487f9 riscv: remove NonSpeculative flag from fence inst by Tuan Ta · 11 months ago
  25. 02dafc5 cpu: fix how a thread starts up in MinorCPU by Tuan Ta · 11 months ago
  26. 8efcc0f arch-riscv: Initialize interrupt mask by Tuan Ta · 13 days ago
  27. ff5ad43 scons: fix unused auto-generated blob variable in clang by Ciro Santilli · 3 weeks ago
  28. 9309797 sim: added missed macro definition on MacOS by Andrea Mondelli · 13 days ago
  29. 1989ce9 misc: added missing override specifier by Andrea Mondelli · 13 days ago
  30. 02d2d7b cpu: Made the Loop Predictor a SimObject by Javier Bueno · 3 weeks ago
  31. 4ba8923 cpu: Made TAGE a SimObject that can be used by other predictors by Jairo Balart · 6 weeks ago
  32. f0e2caf riscv: Get rid of ISA specific register types in Interrupts. by Austin Harris · 13 days ago
  33. 2775f55 mem-cache: Updated version of the Signature Path Prefetcher by Javier Bueno · 10 weeks ago
  34. 6684d61 dev, arm: Removed contextId variable by Anouk Van Laer · 4 weeks ago
  35. a119a96 cpu, arch: Replace the CCReg type with RegVal. by Gabe Black · 3 months ago
  36. fbdf0b6 python: Remove getCode() type workaround by Andreas Sandberg · 3 weeks ago
  37. 244a984 sim: Prepare C++ side for Python 3 by Andreas Sandberg · 3 weeks ago
  38. 2d1723a tests: Add a helper to run external scripts by Andreas Sandberg · 3 weeks ago
  39. cc59815 tests: Don't override tick rate in Ruby tests by Andreas Sandberg · 3 weeks ago
  40. b6a124d power: Get rid of some ISA specific register types. by Gabe Black · 3 months ago
  41. 6ba2888 null: Get rid of some register type definitions. by Gabe Black · 3 months ago
  42. cdfb486 mips: Stop using architecture specific register types. by Gabe Black · 3 months ago
  43. c8a744f alpha: Stop using architecture specific register types. by Gabe Black · 3 months ago
  44. b859a70 x86: Stop using/defining some ISA specific register types. by Gabe Black · 3 months ago
  45. ad775e0 riscv: Get rid of some ISA specific register types. by Gabe Black · 3 months ago
  46. 5edfb67 arch: cpu: Rename *FloatRegBits* to *FloatReg*. by Gabe Black · 3 months ago
  47. 2547416 arch,cpu: Add vector predicate registers by Giacomo Gabrielli · 4 months ago
  48. c6f5db8 configs: Enable DTB autogeneration in starter_fs.py by Giacomo Travaglini · 3 weeks ago
  49. 00ef23b arch-arm, configs: Create single instance of DTB autogeneration by Giacomo Travaglini · 3 weeks ago
  50. b2d24ff tests: fix arm regression due to kernel not found by Ciro Santilli · 3 weeks ago
  51. 9048ef0 configs: fs.py remove --generate-dtb and enable it by default by Ciro Santilli · 4 weeks ago
  52. 12eca7a configs, arch-arm: don't search for default DTB and kernel by Ciro Santilli · 3 months ago
  53. 9b6f0a9 arch-arm: Remove floatReg operand type by Giacomo Travaglini · 5 weeks ago
  54. 96e72d6 arch-arm: Use VecElem instead of FloatReg for FP instruction by Giacomo Travaglini · 9 weeks ago
  55. d8dd86d arch: Fix VecElem Operand generation in ISA parser by Giacomo Travaglini · 9 weeks ago
  56. 3d15150 cpu, arch, arch-arm: Wire unused VecElem code in the O3 model by Giacomo Travaglini · 6 weeks ago
  57. 204e932 cpu: O3 rename using the flatIndex instead of index by Giacomo Travaglini · 6 weeks ago
  58. 47fd797 arch-arm: Inital vector rename mode depending on A32/A64 by Giacomo Travaglini · 6 weeks ago
  59. b045de7 cpu: Fix VecElemClass bugs in cpu models by Giacomo Travaglini · 6 weeks ago
  60. e7c8154 cpu: Add VecElem entries in MinorCPU Scoreboard by Giacomo Travaglini · 6 weeks ago
  61. 4d44889 arch-arm: Remove unused float operands by Giacomo Travaglini · 10 weeks ago
  62. 3ec5afd arch: Provide traceback when parsing ISA code by Giacomo Travaglini · 9 weeks ago
  63. 48f3829 python: Always throw TypeError on slave-slave connections by Nicholas Lindsay · 8 months ago
  64. db190b8 hsail: Remove the MiscReg type. by Gabe Black · 3 months ago
  65. d65f3f9 base: arch: Get rid of the now unused FloatRegVal type. by Gabe Black · 3 months ago
  66. 34064c4 dev-arm: fix --generate-dtb for ARM by Ciro Santilli · 4 weeks ago
  67. 51becd2 cpu-o3: O3 LSQ Generalisation by Rekai Gonzalez-Alberquilla · 2 years ago
  68. 6379beb arch-arm: Implement LoadAcquire/StoreRelease in AArch32 by Giacomo Travaglini · 4 weeks ago
  69. 163065d arch-arm: IsStoreConditional flag set depending on flavor by Giacomo Travaglini · 4 weeks ago
  70. 51aba75 arch-arm: Remove SWP and SWPB instructions by Giacomo Travaglini · 4 weeks ago
  71. e1ef027 systemc: Fix TLM related includes. by Gabe Black · 4 weeks ago
  72. 298e8b8 arm: Replace MiscReg with RegVal in utility.(hh|cc). by Gabe Black · 4 weeks ago
  73. 964e610 mem-ruby: Fix missing TBE allocation and deallocation by Zicong Wang · 5 weeks ago
  74. 1ab1500 sparc: Get rid of some register type definitions. by Gabe Black · 4 months ago
  75. 230b892 arch: cpu: Stop passing around misc registers by reference. by Gabe Black · 4 months ago
  76. 774770a arm: Get rid of some register type definitions. by Gabe Black · 4 months ago
  77. 2b80f58 arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model. by Gabe Black · 4 weeks ago
  78. 0f024be arch-arm: implement the GDB XML target description for ARM by Ciro Santilli · 8 weeks ago
  79. 6064582 ext: import GDB XML target description files for arm by Ciro Santilli · 8 weeks ago
  80. 9712a63 scons: add helpers to access GDB XML description files by Ciro Santilli · 8 weeks ago
  81. f2bda87 scons: allow embedding arbitrary blobs into the gem5 executable by Ciro Santilli · 3 months ago
  82. af5a23a base: add support for GDB's XML architecture definition by Ciro Santilli · 3 months ago
  83. 12eac0c arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers by Giacomo Travaglini · 4 months ago
  84. a0649ee mem: Add tryTiming suppport to CommMonitor by Sascha Bischoff · 3 months ago
  85. e9d9575 sim-se add readv and modifies writev by Brandon Potter · 10 months ago
  86. 7936e63 sim-se: add ability to get/set sock metadata by Brandon Potter · 10 months ago
  87. bc74c58 sim-se: add syscalls related to polling by Brandon Potter · 10 months ago
  88. c4e67f6 sim-se: add calls for network transmissions by Brandon Potter · 10 months ago
  89. a2ed7d5 sim-se: add socket-based functionality by Brandon Potter · 10 months ago
  90. 2c9f7eb base: Fix unitialized storage by Daniel R. Carvalho · 5 weeks ago
  91. 5dda7fb tests: Fix tests/main.py so it can be run from anywhere. by Gabe Black · 5 weeks ago
  92. fa0c2bd mem: Allow inserts in the begining of a packet queue by Nikos Nikoleris · 3 months ago
  93. ccc50b7 mem: Determine if a packet queue forces ordering at construction by Nikos Nikoleris · 3 months ago
  94. 1e9f653 cpu-o3: Make the smtCommitPolicy a Param.ScopedEnum by Nikos Nikoleris · 6 weeks ago
  95. 8c54922 cpu-o3: Make the smtROBPolicy a Param.ScopedEnum by Nikos Nikoleris · 7 weeks ago
  96. 6825ef1 cpu-o3: Make the smtIQPolicy a Param.ScopedEnum by Nikos Nikoleris · 7 weeks ago
  97. 7b4e441 cpu-o3: Make the smtLSQPolicy a Param.ScopedEnum by Nikos Nikoleris · 8 weeks ago
  98. 38339e0 cpu-o3: Make the smtFetchPolicy a Param.ScopedEnum by Nikos Nikoleris · 7 weeks ago
  99. 8ddec57 python: Add support for scoped enums by Nikos Nikoleris · 8 weeks ago
  100. cf0f625 cpu: dev: sim: gpu-compute: Banish some ISA specific register types. by Gabe Black · 4 months ago